2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
33 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
34 struct pb_buffer
*buf
,
35 enum radeon_bo_usage usage
)
37 if (ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, buf
, usage
)) {
40 if (ctx
->dma
.cs
&& ctx
->dma
.cs
->cdw
&&
41 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, buf
, usage
)) {
47 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
48 struct r600_resource
*resource
,
51 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
54 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
55 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
58 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
59 /* have to wait for the last write */
60 rusage
= RADEON_USAGE_WRITE
;
63 if (ctx
->gfx
.cs
->cdw
!= ctx
->initial_gfx_cs_size
&&
64 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
65 resource
->buf
, rusage
)) {
66 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
67 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
70 ctx
->gfx
.flush(ctx
, 0, NULL
);
76 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
77 resource
->buf
, rusage
)) {
78 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
79 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
82 ctx
->dma
.flush(ctx
, 0, NULL
);
87 if (busy
|| !ctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
88 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
91 /* We will be wait for the GPU. Wait for any offloaded
92 * CS flush to complete to avoid busy-waiting in the winsys. */
93 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
95 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
99 /* Setting the CS to NULL will prevent doing checks we have done already. */
100 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
103 bool r600_init_resource(struct r600_common_screen
*rscreen
,
104 struct r600_resource
*res
,
105 unsigned size
, unsigned alignment
,
106 bool use_reusable_pool
)
108 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
109 struct pb_buffer
*old_buf
, *new_buf
;
110 enum radeon_bo_flag flags
= 0;
112 switch (res
->b
.b
.usage
) {
113 case PIPE_USAGE_STREAM
:
114 flags
= RADEON_FLAG_GTT_WC
;
116 case PIPE_USAGE_STAGING
:
117 /* Transfers are likely to occur more often with these resources. */
118 res
->domains
= RADEON_DOMAIN_GTT
;
120 case PIPE_USAGE_DYNAMIC
:
121 /* Older kernels didn't always flush the HDP cache before
124 if (rscreen
->info
.drm_major
== 2 &&
125 rscreen
->info
.drm_minor
< 40) {
126 res
->domains
= RADEON_DOMAIN_GTT
;
127 flags
|= RADEON_FLAG_GTT_WC
;
130 flags
|= RADEON_FLAG_CPU_ACCESS
;
132 case PIPE_USAGE_DEFAULT
:
133 case PIPE_USAGE_IMMUTABLE
:
135 /* Not listing GTT here improves performance in some apps. */
136 res
->domains
= RADEON_DOMAIN_VRAM
;
137 flags
|= RADEON_FLAG_GTT_WC
;
141 if (res
->b
.b
.target
== PIPE_BUFFER
&&
142 res
->b
.b
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
143 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
144 /* Use GTT for all persistent mappings with older kernels,
145 * because they didn't always flush the HDP cache before CS
148 * Write-combined CPU mappings are fine, the kernel ensures all CPU
149 * writes finish before the GPU executes a command stream.
151 if (rscreen
->info
.drm_major
== 2 &&
152 rscreen
->info
.drm_minor
< 40)
153 res
->domains
= RADEON_DOMAIN_GTT
;
154 else if (res
->domains
& RADEON_DOMAIN_VRAM
)
155 flags
|= RADEON_FLAG_CPU_ACCESS
;
158 /* Tiled textures are unmappable. Always put them in VRAM. */
159 if (res
->b
.b
.target
!= PIPE_BUFFER
&&
160 rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
) {
161 res
->domains
= RADEON_DOMAIN_VRAM
;
162 flags
&= ~RADEON_FLAG_CPU_ACCESS
;
163 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
166 if (rscreen
->debug_flags
& DBG_NO_WC
)
167 flags
&= ~RADEON_FLAG_GTT_WC
;
169 /* Allocate a new resource. */
170 new_buf
= rscreen
->ws
->buffer_create(rscreen
->ws
, size
, alignment
,
172 res
->domains
, flags
);
177 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
178 * NULL. This should prevent crashes with multiple contexts using
179 * the same buffer where one of the contexts invalidates it while
180 * the others are using it. */
182 res
->buf
= new_buf
; /* should be atomic */
184 if (rscreen
->info
.has_virtual_memory
)
185 res
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(res
->buf
);
187 res
->gpu_address
= 0;
189 pb_reference(&old_buf
, NULL
);
191 util_range_set_empty(&res
->valid_buffer_range
);
192 res
->TC_L2_dirty
= false;
194 if (rscreen
->debug_flags
& DBG_VM
&& res
->b
.b
.target
== PIPE_BUFFER
) {
195 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %u bytes\n",
196 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
202 static void r600_buffer_destroy(struct pipe_screen
*screen
,
203 struct pipe_resource
*buf
)
205 struct r600_resource
*rbuffer
= r600_resource(buf
);
207 util_range_destroy(&rbuffer
->valid_buffer_range
);
208 pb_reference(&rbuffer
->buf
, NULL
);
213 r600_invalidate_buffer(struct r600_common_context
*rctx
,
214 struct r600_resource
*rbuffer
)
216 /* In AMD_pinned_memory, the user pointer association only gets
217 * broken when the buffer is explicitly re-allocated.
219 if (rctx
->ws
->buffer_is_user_ptr(rbuffer
->buf
))
222 /* Check if mapping this buffer would cause waiting for the GPU. */
223 if (r600_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
224 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
225 rctx
->invalidate_buffer(&rctx
->b
, &rbuffer
->b
.b
);
227 util_range_set_empty(&rbuffer
->valid_buffer_range
);
233 void r600_invalidate_resource(struct pipe_context
*ctx
,
234 struct pipe_resource
*resource
)
236 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
237 struct r600_resource
*rbuffer
= r600_resource(resource
);
239 /* We currently only do anyting here for buffers */
240 if (resource
->target
== PIPE_BUFFER
)
241 (void)r600_invalidate_buffer(rctx
, rbuffer
);
244 static void *r600_buffer_get_transfer(struct pipe_context
*ctx
,
245 struct pipe_resource
*resource
,
248 const struct pipe_box
*box
,
249 struct pipe_transfer
**ptransfer
,
250 void *data
, struct r600_resource
*staging
,
253 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
254 struct r600_transfer
*transfer
= util_slab_alloc(&rctx
->pool_transfers
);
256 transfer
->transfer
.resource
= resource
;
257 transfer
->transfer
.level
= level
;
258 transfer
->transfer
.usage
= usage
;
259 transfer
->transfer
.box
= *box
;
260 transfer
->transfer
.stride
= 0;
261 transfer
->transfer
.layer_stride
= 0;
262 transfer
->offset
= offset
;
263 transfer
->staging
= staging
;
264 *ptransfer
= &transfer
->transfer
;
268 static bool r600_can_dma_copy_buffer(struct r600_common_context
*rctx
,
269 unsigned dstx
, unsigned srcx
, unsigned size
)
271 bool dword_aligned
= !(dstx
% 4) && !(srcx
% 4) && !(size
% 4);
273 return rctx
->screen
->has_cp_dma
||
274 (dword_aligned
&& (rctx
->dma
.cs
||
275 rctx
->screen
->has_streamout
));
279 static void *r600_buffer_transfer_map(struct pipe_context
*ctx
,
280 struct pipe_resource
*resource
,
283 const struct pipe_box
*box
,
284 struct pipe_transfer
**ptransfer
)
286 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
287 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
288 struct r600_resource
*rbuffer
= r600_resource(resource
);
291 assert(box
->x
+ box
->width
<= resource
->width0
);
293 /* See if the buffer range being mapped has never been initialized,
294 * in which case it can be mapped unsynchronized. */
295 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
296 usage
& PIPE_TRANSFER_WRITE
&&
297 !util_ranges_intersect(&rbuffer
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
298 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
301 /* If discarding the entire range, discard the whole resource instead. */
302 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
303 box
->x
== 0 && box
->width
== resource
->width0
) {
304 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
307 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
308 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
309 assert(usage
& PIPE_TRANSFER_WRITE
);
311 if (r600_invalidate_buffer(rctx
, rbuffer
)) {
312 /* At this point, the buffer is always idle. */
313 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
316 else if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
317 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
318 !(rscreen
->debug_flags
& DBG_NO_DISCARD_RANGE
) &&
319 r600_can_dma_copy_buffer(rctx
, box
->x
, 0, box
->width
)) {
320 assert(usage
& PIPE_TRANSFER_WRITE
);
322 /* Check if mapping this buffer would cause waiting for the GPU. */
323 if (r600_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
324 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
325 /* Do a wait-free write-only transfer using a temporary buffer. */
327 struct r600_resource
*staging
= NULL
;
329 u_upload_alloc(rctx
->uploader
, 0, box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
),
330 256, &offset
, (struct pipe_resource
**)&staging
, (void**)&data
);
333 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
334 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
335 ptransfer
, data
, staging
, offset
);
338 /* At this point, the buffer is always idle (we checked it above). */
339 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
342 /* Using a staging buffer in GTT for larger reads is much faster. */
343 else if ((usage
& PIPE_TRANSFER_READ
) &&
344 !(usage
& PIPE_TRANSFER_WRITE
) &&
345 rbuffer
->domains
== RADEON_DOMAIN_VRAM
&&
346 r600_can_dma_copy_buffer(rctx
, 0, box
->x
, box
->width
)) {
347 struct r600_resource
*staging
;
349 staging
= (struct r600_resource
*) pipe_buffer_create(
350 ctx
->screen
, PIPE_BIND_TRANSFER_READ
, PIPE_USAGE_STAGING
,
351 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
));
353 /* Copy the VRAM buffer to the staging buffer. */
354 rctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
355 box
->x
% R600_MAP_BUFFER_ALIGNMENT
,
356 0, 0, resource
, level
, box
);
358 data
= r600_buffer_map_sync_with_rings(rctx
, staging
, PIPE_TRANSFER_READ
);
359 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
361 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
362 ptransfer
, data
, staging
, 0);
366 data
= r600_buffer_map_sync_with_rings(rctx
, rbuffer
, usage
);
372 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
373 ptransfer
, data
, NULL
, 0);
376 static void r600_buffer_do_flush_region(struct pipe_context
*ctx
,
377 struct pipe_transfer
*transfer
,
378 const struct pipe_box
*box
)
380 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
381 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
382 struct r600_resource
*rbuffer
= r600_resource(transfer
->resource
);
384 if (rtransfer
->staging
) {
385 struct pipe_resource
*dst
, *src
;
387 struct pipe_box dma_box
;
389 dst
= transfer
->resource
;
390 src
= &rtransfer
->staging
->b
.b
;
391 soffset
= rtransfer
->offset
+ box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
393 u_box_1d(soffset
, box
->width
, &dma_box
);
395 /* Copy the staging buffer into the original one. */
396 rctx
->dma_copy(ctx
, dst
, 0, box
->x
, 0, 0, src
, 0, &dma_box
);
399 util_range_add(&rbuffer
->valid_buffer_range
, box
->x
,
400 box
->x
+ box
->width
);
403 static void r600_buffer_flush_region(struct pipe_context
*ctx
,
404 struct pipe_transfer
*transfer
,
405 const struct pipe_box
*rel_box
)
407 if (transfer
->usage
& (PIPE_TRANSFER_WRITE
|
408 PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
411 u_box_1d(transfer
->box
.x
+ rel_box
->x
, rel_box
->width
, &box
);
412 r600_buffer_do_flush_region(ctx
, transfer
, &box
);
416 static void r600_buffer_transfer_unmap(struct pipe_context
*ctx
,
417 struct pipe_transfer
*transfer
)
419 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
420 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
422 if (transfer
->usage
& PIPE_TRANSFER_WRITE
&&
423 !(transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
))
424 r600_buffer_do_flush_region(ctx
, transfer
, &transfer
->box
);
426 if (rtransfer
->staging
)
427 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
429 util_slab_free(&rctx
->pool_transfers
, transfer
);
432 static const struct u_resource_vtbl r600_buffer_vtbl
=
434 NULL
, /* get_handle */
435 r600_buffer_destroy
, /* resource_destroy */
436 r600_buffer_transfer_map
, /* transfer_map */
437 r600_buffer_flush_region
, /* transfer_flush_region */
438 r600_buffer_transfer_unmap
, /* transfer_unmap */
439 NULL
/* transfer_inline_write */
442 static struct r600_resource
*
443 r600_alloc_buffer_struct(struct pipe_screen
*screen
,
444 const struct pipe_resource
*templ
)
446 struct r600_resource
*rbuffer
;
448 rbuffer
= MALLOC_STRUCT(r600_resource
);
450 rbuffer
->b
.b
= *templ
;
451 pipe_reference_init(&rbuffer
->b
.b
.reference
, 1);
452 rbuffer
->b
.b
.screen
= screen
;
453 rbuffer
->b
.vtbl
= &r600_buffer_vtbl
;
455 rbuffer
->TC_L2_dirty
= false;
456 util_range_init(&rbuffer
->valid_buffer_range
);
460 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
461 const struct pipe_resource
*templ
,
464 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
465 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
467 if (!r600_init_resource(rscreen
, rbuffer
, templ
->width0
, alignment
, TRUE
)) {
471 return &rbuffer
->b
.b
;
474 struct pipe_resource
*r600_aligned_buffer_create(struct pipe_screen
*screen
,
480 struct pipe_resource buffer
;
482 memset(&buffer
, 0, sizeof buffer
);
483 buffer
.target
= PIPE_BUFFER
;
484 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
486 buffer
.usage
= usage
;
488 buffer
.width0
= size
;
491 buffer
.array_size
= 1;
492 return r600_buffer_create(screen
, &buffer
, alignment
);
495 struct pipe_resource
*
496 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
497 const struct pipe_resource
*templ
,
500 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
501 struct radeon_winsys
*ws
= rscreen
->ws
;
502 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
504 rbuffer
->domains
= RADEON_DOMAIN_GTT
;
505 util_range_add(&rbuffer
->valid_buffer_range
, 0, templ
->width0
);
507 /* Convert a user pointer to a buffer. */
508 rbuffer
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
514 if (rscreen
->info
.has_virtual_memory
)
515 rbuffer
->gpu_address
=
516 ws
->buffer_get_virtual_address(rbuffer
->buf
);
518 rbuffer
->gpu_address
= 0;
520 return &rbuffer
->b
.b
;