src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "r600_cs.h"
  25 #include "util/u_memory.h"
  26 #include "util/u_upload_mgr.h"
  27 #include <inttypes.h>
  28 #include <stdio.h>
  29
  30 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
  31                                    struct pb_buffer *buf,
  32                                    enum radeon_bo_usage usage)
  33 {
  34         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  35                 return true;
  36         }
  37         if (radeon_emitted(ctx->dma.cs, 0) &&
  38             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  39                 return true;
  40         }
  41         return false;
  42 }
  43
  44 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  45                                     struct r600_resource *resource,
  46                                     unsigned usage)
  47 {
  48         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  49         bool busy = false;
  50
  51         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  52
  53         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  54                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  55         }
  56
  57         if (!(usage & PIPE_TRANSFER_WRITE)) {
  58                 /* have to wait for the last write */
  59                 rusage = RADEON_USAGE_WRITE;
  60         }
  61
  62         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  63             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  64                                              resource->buf, rusage)) {
  65                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  66                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  67                         return NULL;
  68                 } else {
  69                         ctx->gfx.flush(ctx, 0, NULL);
  70                         busy = true;
  71                 }
  72         }
  73         if (radeon_emitted(ctx->dma.cs, 0) &&
  74             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  75                                              resource->buf, rusage)) {
  76                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  77                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  78                         return NULL;
  79                 } else {
  80                         ctx->dma.flush(ctx, 0, NULL);
  81                         busy = true;
  82                 }
  83         }
  84
  85         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  86                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  87                         return NULL;
  88                 } else {
  89                         /* We will be wait for the GPU. Wait for any offloaded
  90                          * CS flush to complete to avoid busy-waiting in the winsys. */
  91                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  92                         if (ctx->dma.cs)
  93                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  94                 }
  95         }
  96
  97         /* Setting the CS to NULL will prevent doing checks we have done already. */
  98         return ctx->ws->buffer_map(resource->buf, NULL, usage);
  99 }
 100
 101 void si_init_resource_fields(struct r600_common_screen *rscreen,
 102                              struct r600_resource *res,
 103                              uint64_t size, unsigned alignment)
 104 {
 105         struct r600_texture *rtex = (struct r600_texture*)res;
 106
 107         res->bo_size = size;
 108         res->bo_alignment = alignment;
 109         res->flags = 0;
 110         res->texture_handle_allocated = false;
 111         res->image_handle_allocated = false;
 112
 113         switch (res->b.b.usage) {
 114         case PIPE_USAGE_STREAM:
 115                 res->flags = RADEON_FLAG_GTT_WC;
 116                 /* fall through */
 117         case PIPE_USAGE_STAGING:
 118                 /* Transfers are likely to occur more often with these
 119                  * resources. */
 120                 res->domains = RADEON_DOMAIN_GTT;
 121                 break;
 122         case PIPE_USAGE_DYNAMIC:
 123                 /* Older kernels didn't always flush the HDP cache before
 124                  * CS execution
 125                  */
 126                 if (rscreen->info.drm_major == 2 &&
 127                     rscreen->info.drm_minor < 40) {
 128                         res->domains = RADEON_DOMAIN_GTT;
 129                         res->flags |= RADEON_FLAG_GTT_WC;
 130                         break;
 131                 }
 132                 /* fall through */
 133         case PIPE_USAGE_DEFAULT:
 134         case PIPE_USAGE_IMMUTABLE:
 135         default:
 136                 /* Not listing GTT here improves performance in some
 137                  * apps. */
 138                 res->domains = RADEON_DOMAIN_VRAM;
 139                 res->flags |= RADEON_FLAG_GTT_WC;
 140                 break;
 141         }
 142
 143         if (res->b.b.target == PIPE_BUFFER &&
 144             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 145                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 146                 /* Use GTT for all persistent mappings with older
 147                  * kernels, because they didn't always flush the HDP
 148                  * cache before CS execution.
 149                  *
 150                  * Write-combined CPU mappings are fine, the kernel
 151                  * ensures all CPU writes finish before the GPU
 152                  * executes a command stream.
 153                  */
 154                 if (rscreen->info.drm_major == 2 &&
 155                     rscreen->info.drm_minor < 40)
 156                         res->domains = RADEON_DOMAIN_GTT;
 157         }
 158
 159         /* Tiled textures are unmappable. Always put them in VRAM. */
 160         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 161             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 162                 res->domains = RADEON_DOMAIN_VRAM;
 163                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 164                          RADEON_FLAG_GTT_WC;
 165         }
 166
 167         /* Displayable and shareable surfaces are not suballocated. */
 168         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 169                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 170         else
 171                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 172
 173         /* If VRAM is just stolen system memory, allow both VRAM and
 174          * GTT, whichever has free space. If a buffer is evicted from
 175          * VRAM to GTT, it will stay there.
 176          *
 177          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 178          * placements even with a low amount of stolen VRAM.
 179          */
 180         if (!rscreen->info.has_dedicated_vram &&
 181             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 182             res->domains == RADEON_DOMAIN_VRAM) {
 183                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 184                 res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
 185         }
 186
 187         if (rscreen->debug_flags & DBG(NO_WC))
 188                 res->flags &= ~RADEON_FLAG_GTT_WC;
 189
 190         /* Set expected VRAM and GART usage for the buffer. */
 191         res->vram_usage = 0;
 192         res->gart_usage = 0;
 193
 194         if (res->domains & RADEON_DOMAIN_VRAM) {
 195                 res->vram_usage = size;
 196
 197                 res->max_forced_staging_uploads =
 198                 res->b.max_forced_staging_uploads =
 199                         rscreen->info.has_dedicated_vram &&
 200                         size >= rscreen->info.vram_vis_size / 4 ? 1 : 0;
 201         } else if (res->domains & RADEON_DOMAIN_GTT) {
 202                 res->gart_usage = size;
 203         }
 204 }
 205
 206 bool si_alloc_resource(struct r600_common_screen *rscreen,
 207                        struct r600_resource *res)
 208 {
 209         struct pb_buffer *old_buf, *new_buf;
 210
 211         /* Allocate a new resource. */
 212         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 213                                              res->bo_alignment,
 214                                              res->domains, res->flags);
 215         if (!new_buf) {
 216                 return false;
 217         }
 218
 219         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 220          * NULL. This should prevent crashes with multiple contexts using
 221          * the same buffer where one of the contexts invalidates it while
 222          * the others are using it. */
 223         old_buf = res->buf;
 224         res->buf = new_buf; /* should be atomic */
 225
 226         if (rscreen->info.has_virtual_memory)
 227                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 228         else
 229                 res->gpu_address = 0;
 230
 231         pb_reference(&old_buf, NULL);
 232
 233         util_range_set_empty(&res->valid_buffer_range);
 234         res->TC_L2_dirty = false;
 235
 236         /* Print debug information. */
 237         if (rscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 238                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 239                         res->gpu_address, res->gpu_address + res->buf->size,
 240                         res->buf->size);
 241         }
 242         return true;
 243 }
 244
 245 static void r600_buffer_destroy(struct pipe_screen *screen,
 246                                 struct pipe_resource *buf)
 247 {
 248         struct r600_resource *rbuffer = r600_resource(buf);
 249
 250         threaded_resource_deinit(buf);
 251         util_range_destroy(&rbuffer->valid_buffer_range);
 252         pb_reference(&rbuffer->buf, NULL);
 253         FREE(rbuffer);
 254 }
 255
 256 static bool
 257 r600_invalidate_buffer(struct r600_common_context *rctx,
 258                        struct r600_resource *rbuffer)
 259 {
 260         /* Shared buffers can't be reallocated. */
 261         if (rbuffer->b.is_shared)
 262                 return false;
 263
 264         /* Sparse buffers can't be reallocated. */
 265         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 266                 return false;
 267
 268         /* In AMD_pinned_memory, the user pointer association only gets
 269          * broken when the buffer is explicitly re-allocated.
 270          */
 271         if (rbuffer->b.is_user_ptr)
 272                 return false;
 273
 274         /* Check if mapping this buffer would cause waiting for the GPU. */
 275         if (si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 276             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 277                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 278         } else {
 279                 util_range_set_empty(&rbuffer->valid_buffer_range);
 280         }
 281
 282         return true;
 283 }
 284
 285 /* Replace the storage of dst with src. */
 286 void si_replace_buffer_storage(struct pipe_context *ctx,
 287                                  struct pipe_resource *dst,
 288                                  struct pipe_resource *src)
 289 {
 290         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 291         struct r600_resource *rdst = r600_resource(dst);
 292         struct r600_resource *rsrc = r600_resource(src);
 293         uint64_t old_gpu_address = rdst->gpu_address;
 294
 295         pb_reference(&rdst->buf, rsrc->buf);
 296         rdst->gpu_address = rsrc->gpu_address;
 297         rdst->b.b.bind = rsrc->b.b.bind;
 298         rdst->b.max_forced_staging_uploads = rsrc->b.max_forced_staging_uploads;
 299         rdst->max_forced_staging_uploads = rsrc->max_forced_staging_uploads;
 300         rdst->flags = rsrc->flags;
 301
 302         assert(rdst->vram_usage == rsrc->vram_usage);
 303         assert(rdst->gart_usage == rsrc->gart_usage);
 304         assert(rdst->bo_size == rsrc->bo_size);
 305         assert(rdst->bo_alignment == rsrc->bo_alignment);
 306         assert(rdst->domains == rsrc->domains);
 307
 308         rctx->rebind_buffer(ctx, dst, old_gpu_address);
 309 }
 310
 311 void si_invalidate_resource(struct pipe_context *ctx,
 312                             struct pipe_resource *resource)
 313 {
 314         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 315         struct r600_resource *rbuffer = r600_resource(resource);
 316
 317         /* We currently only do anyting here for buffers */
 318         if (resource->target == PIPE_BUFFER)
 319                 (void)r600_invalidate_buffer(rctx, rbuffer);
 320 }
 321
 322 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 323                                       struct pipe_resource *resource,
 324                                       unsigned usage,
 325                                       const struct pipe_box *box,
 326                                       struct pipe_transfer **ptransfer,
 327                                       void *data, struct r600_resource *staging,
 328                                       unsigned offset)
 329 {
 330         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 331         struct r600_transfer *transfer;
 332
 333         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 334                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 335         else
 336                 transfer = slab_alloc(&rctx->pool_transfers);
 337
 338         transfer->b.b.resource = NULL;
 339         pipe_resource_reference(&transfer->b.b.resource, resource);
 340         transfer->b.b.level = 0;
 341         transfer->b.b.usage = usage;
 342         transfer->b.b.box = *box;
 343         transfer->b.b.stride = 0;
 344         transfer->b.b.layer_stride = 0;
 345         transfer->b.staging = NULL;
 346         transfer->offset = offset;
 347         transfer->staging = staging;
 348         *ptransfer = &transfer->b.b;
 349         return data;
 350 }
 351
 352 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 353                                      unsigned dstx, unsigned srcx, unsigned size)
 354 {
 355         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 356
 357         return rctx->screen->has_cp_dma ||
 358                (dword_aligned && (rctx->dma.cs ||
 359                                   rctx->screen->has_streamout));
 360
 361 }
 362
 363 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 364                                       struct pipe_resource *resource,
 365                                       unsigned level,
 366                                       unsigned usage,
 367                                       const struct pipe_box *box,
 368                                       struct pipe_transfer **ptransfer)
 369 {
 370         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 371         struct r600_resource *rbuffer = r600_resource(resource);
 372         uint8_t *data;
 373
 374         assert(box->x + box->width <= resource->width0);
 375
 376         /* From GL_AMD_pinned_memory issues:
 377          *
 378          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 379          *        same system address which was specified at creation time?
 380          *
 381          *        RESOLVED: NO. The GL implementation might return a different
 382          *        virtual mapping of that memory, although the same physical
 383          *        page will be used.
 384          *
 385          * So don't ever use staging buffers.
 386          */
 387         if (rbuffer->b.is_user_ptr)
 388                 usage |= PIPE_TRANSFER_PERSISTENT;
 389
 390         /* See if the buffer range being mapped has never been initialized,
 391          * in which case it can be mapped unsynchronized. */
 392         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 393                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 394             usage & PIPE_TRANSFER_WRITE &&
 395             !rbuffer->b.is_shared &&
 396             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 397                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 398         }
 399
 400         /* If discarding the entire range, discard the whole resource instead. */
 401         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 402             box->x == 0 && box->width == resource->width0) {
 403                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 404         }
 405
 406         /* If a buffer in VRAM is too large and the range is discarded, don't
 407          * map it directly. This makes sure that the buffer stays in VRAM.
 408          */
 409         bool force_discard_range = false;
 410         if (usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 411                      PIPE_TRANSFER_DISCARD_RANGE) &&
 412             !(usage & PIPE_TRANSFER_PERSISTENT) &&
 413             /* Try not to decrement the counter if it's not positive. Still racy,
 414              * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
 415             rbuffer->max_forced_staging_uploads > 0 &&
 416             p_atomic_dec_return(&rbuffer->max_forced_staging_uploads) >= 0) {
 417                 usage &= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
 418                            PIPE_TRANSFER_UNSYNCHRONIZED);
 419                 usage |= PIPE_TRANSFER_DISCARD_RANGE;
 420                 force_discard_range = true;
 421         }
 422
 423         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 424             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 425                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 426                 assert(usage & PIPE_TRANSFER_WRITE);
 427
 428                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 429                         /* At this point, the buffer is always idle. */
 430                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 431                 } else {
 432                         /* Fall back to a temporary buffer. */
 433                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 434                 }
 435         }
 436
 437         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 438             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 439                          PIPE_TRANSFER_PERSISTENT)) &&
 440               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 441              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 442                 assert(usage & PIPE_TRANSFER_WRITE);
 443
 444                 /* Check if mapping this buffer would cause waiting for the GPU.
 445                  */
 446                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 447                     force_discard_range ||
 448                     si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 449                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 450                         /* Do a wait-free write-only transfer using a temporary buffer. */
 451                         unsigned offset;
 452                         struct r600_resource *staging = NULL;
 453
 454                         u_upload_alloc(ctx->stream_uploader, 0,
 455                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 456                                        rctx->screen->info.tcc_cache_line_size,
 457                                        &offset, (struct pipe_resource**)&staging,
 458                                        (void**)&data);
 459
 460                         if (staging) {
 461                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 462                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 463                                                                 ptransfer, data, staging, offset);
 464                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 465                                 return NULL;
 466                         }
 467                 } else {
 468                         /* At this point, the buffer is always idle (we checked it above). */
 469                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 470                 }
 471         }
 472         /* Use a staging buffer in cached GTT for reads. */
 473         else if (((usage & PIPE_TRANSFER_READ) &&
 474                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 475                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 476                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 477                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 478                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 479                 struct r600_resource *staging;
 480
 481                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 482                 staging = (struct r600_resource*) pipe_buffer_create(
 483                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 484                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 485                 if (staging) {
 486                         /* Copy the VRAM buffer to the staging buffer. */
 487                         rctx->dma_copy(ctx, &staging->b.b, 0,
 488                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 489                                        0, 0, resource, 0, box);
 490
 491                         data = si_buffer_map_sync_with_rings(rctx, staging,
 492                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 493                         if (!data) {
 494                                 r600_resource_reference(&staging, NULL);
 495                                 return NULL;
 496                         }
 497                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 498
 499                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 500                                                         ptransfer, data, staging, 0);
 501                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 502                         return NULL;
 503                 }
 504         }
 505
 506         data = si_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 507         if (!data) {
 508                 return NULL;
 509         }
 510         data += box->x;
 511
 512         return r600_buffer_get_transfer(ctx, resource, usage, box,
 513                                         ptransfer, data, NULL, 0);
 514 }
 515
 516 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 517                                         struct pipe_transfer *transfer,
 518                                         const struct pipe_box *box)
 519 {
 520         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 521         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 522
 523         if (rtransfer->staging) {
 524                 struct pipe_resource *dst, *src;
 525                 unsigned soffset;
 526                 struct pipe_box dma_box;
 527
 528                 dst = transfer->resource;
 529                 src = &rtransfer->staging->b.b;
 530                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 531
 532                 u_box_1d(soffset, box->width, &dma_box);
 533
 534                 /* Copy the staging buffer into the original one. */
 535                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 536         }
 537
 538         util_range_add(&rbuffer->valid_buffer_range, box->x,
 539                        box->x + box->width);
 540 }
 541
 542 static void r600_buffer_flush_region(struct pipe_context *ctx,
 543                                      struct pipe_transfer *transfer,
 544                                      const struct pipe_box *rel_box)
 545 {
 546         unsigned required_usage = PIPE_TRANSFER_WRITE |
 547                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 548
 549         if ((transfer->usage & required_usage) == required_usage) {
 550                 struct pipe_box box;
 551
 552                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 553                 r600_buffer_do_flush_region(ctx, transfer, &box);
 554         }
 555 }
 556
 557 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 558                                        struct pipe_transfer *transfer)
 559 {
 560         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 561         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 562
 563         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 564             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 565                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 566
 567         r600_resource_reference(&rtransfer->staging, NULL);
 568         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 569         pipe_resource_reference(&transfer->resource, NULL);
 570
 571         /* Don't use pool_transfers_unsync. We are always in the driver
 572          * thread. */
 573         slab_free(&rctx->pool_transfers, transfer);
 574 }
 575
 576 void si_buffer_subdata(struct pipe_context *ctx,
 577                        struct pipe_resource *buffer,
 578                        unsigned usage, unsigned offset,
 579                        unsigned size, const void *data)
 580 {
 581         struct pipe_transfer *transfer = NULL;
 582         struct pipe_box box;
 583         uint8_t *map = NULL;
 584
 585         u_box_1d(offset, size, &box);
 586         map = r600_buffer_transfer_map(ctx, buffer, 0,
 587                                        PIPE_TRANSFER_WRITE |
 588                                        PIPE_TRANSFER_DISCARD_RANGE |
 589                                        usage,
 590                                        &box, &transfer);
 591         if (!map)
 592                 return;
 593
 594         memcpy(map, data, size);
 595         r600_buffer_transfer_unmap(ctx, transfer);
 596 }
 597
 598 static const struct u_resource_vtbl r600_buffer_vtbl =
 599 {
 600         NULL,                           /* get_handle */
 601         r600_buffer_destroy,            /* resource_destroy */
 602         r600_buffer_transfer_map,       /* transfer_map */
 603         r600_buffer_flush_region,       /* transfer_flush_region */
 604         r600_buffer_transfer_unmap,     /* transfer_unmap */
 605 };
 606
 607 static struct r600_resource *
 608 r600_alloc_buffer_struct(struct pipe_screen *screen,
 609                          const struct pipe_resource *templ)
 610 {
 611         struct r600_resource *rbuffer;
 612
 613         rbuffer = MALLOC_STRUCT(r600_resource);
 614
 615         rbuffer->b.b = *templ;
 616         rbuffer->b.b.next = NULL;
 617         pipe_reference_init(&rbuffer->b.b.reference, 1);
 618         rbuffer->b.b.screen = screen;
 619
 620         rbuffer->b.vtbl = &r600_buffer_vtbl;
 621         threaded_resource_init(&rbuffer->b.b);
 622
 623         rbuffer->buf = NULL;
 624         rbuffer->bind_history = 0;
 625         rbuffer->TC_L2_dirty = false;
 626         util_range_init(&rbuffer->valid_buffer_range);
 627         return rbuffer;
 628 }
 629
 630 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 631                                        const struct pipe_resource *templ,
 632                                        unsigned alignment)
 633 {
 634         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 635         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 636
 637         si_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 638
 639         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 640                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 641
 642         if (!si_alloc_resource(rscreen, rbuffer)) {
 643                 FREE(rbuffer);
 644                 return NULL;
 645         }
 646         return &rbuffer->b.b;
 647 }
 648
 649 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 650                                                unsigned flags,
 651                                                unsigned usage,
 652                                                unsigned size,
 653                                                unsigned alignment)
 654 {
 655         struct pipe_resource buffer;
 656
 657         memset(&buffer, 0, sizeof buffer);
 658         buffer.target = PIPE_BUFFER;
 659         buffer.format = PIPE_FORMAT_R8_UNORM;
 660         buffer.bind = 0;
 661         buffer.usage = usage;
 662         buffer.flags = flags;
 663         buffer.width0 = size;
 664         buffer.height0 = 1;
 665         buffer.depth0 = 1;
 666         buffer.array_size = 1;
 667         return si_buffer_create(screen, &buffer, alignment);
 668 }
 669
 670 struct pipe_resource *
 671 si_buffer_from_user_memory(struct pipe_screen *screen,
 672                            const struct pipe_resource *templ,
 673                            void *user_memory)
 674 {
 675         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 676         struct radeon_winsys *ws = rscreen->ws;
 677         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 678
 679         rbuffer->domains = RADEON_DOMAIN_GTT;
 680         rbuffer->flags = 0;
 681         rbuffer->b.is_user_ptr = true;
 682         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 683         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 684
 685         /* Convert a user pointer to a buffer. */
 686         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 687         if (!rbuffer->buf) {
 688                 FREE(rbuffer);
 689                 return NULL;
 690         }
 691
 692         if (rscreen->info.has_virtual_memory)
 693                 rbuffer->gpu_address =
 694                         ws->buffer_get_virtual_address(rbuffer->buf);
 695         else
 696                 rbuffer->gpu_address = 0;
 697
 698         rbuffer->vram_usage = 0;
 699         rbuffer->gart_usage = templ->width0;
 700
 701         return &rbuffer->b.b;
 702 }