2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
31 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
32 struct pb_buffer
*buf
,
33 enum radeon_bo_usage usage
)
35 if (ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, buf
, usage
)) {
38 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
39 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, buf
, usage
)) {
45 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
46 struct r600_resource
*resource
,
49 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
52 assert(!(resource
->flags
& RADEON_FLAG_SPARSE
));
54 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
55 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
58 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
59 /* have to wait for the last write */
60 rusage
= RADEON_USAGE_WRITE
;
63 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
64 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
65 resource
->buf
, rusage
)) {
66 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
67 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
70 ctx
->gfx
.flush(ctx
, 0, NULL
);
74 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
75 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
76 resource
->buf
, rusage
)) {
77 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
78 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
81 ctx
->dma
.flush(ctx
, 0, NULL
);
86 if (busy
|| !ctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
87 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
90 /* We will be wait for the GPU. Wait for any offloaded
91 * CS flush to complete to avoid busy-waiting in the winsys. */
92 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
94 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
98 /* Setting the CS to NULL will prevent doing checks we have done already. */
99 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
102 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
103 struct r600_resource
*res
,
104 uint64_t size
, unsigned alignment
)
106 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
109 res
->bo_alignment
= alignment
;
111 res
->texture_handle_allocated
= false;
112 res
->image_handle_allocated
= false;
114 switch (res
->b
.b
.usage
) {
115 case PIPE_USAGE_STREAM
:
116 res
->flags
= RADEON_FLAG_GTT_WC
;
118 case PIPE_USAGE_STAGING
:
119 /* Transfers are likely to occur more often with these
121 res
->domains
= RADEON_DOMAIN_GTT
;
123 case PIPE_USAGE_DYNAMIC
:
124 /* Older kernels didn't always flush the HDP cache before
127 if (rscreen
->info
.drm_major
== 2 &&
128 rscreen
->info
.drm_minor
< 40) {
129 res
->domains
= RADEON_DOMAIN_GTT
;
130 res
->flags
|= RADEON_FLAG_GTT_WC
;
134 case PIPE_USAGE_DEFAULT
:
135 case PIPE_USAGE_IMMUTABLE
:
137 /* Not listing GTT here improves performance in some
139 res
->domains
= RADEON_DOMAIN_VRAM
;
140 res
->flags
|= RADEON_FLAG_GTT_WC
;
144 if (res
->b
.b
.target
== PIPE_BUFFER
&&
145 res
->b
.b
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
146 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
147 /* Use GTT for all persistent mappings with older
148 * kernels, because they didn't always flush the HDP
149 * cache before CS execution.
151 * Write-combined CPU mappings are fine, the kernel
152 * ensures all CPU writes finish before the GPU
153 * executes a command stream.
155 if (rscreen
->info
.drm_major
== 2 &&
156 rscreen
->info
.drm_minor
< 40)
157 res
->domains
= RADEON_DOMAIN_GTT
;
160 /* Tiled textures are unmappable. Always put them in VRAM. */
161 if ((res
->b
.b
.target
!= PIPE_BUFFER
&& !rtex
->surface
.is_linear
) ||
162 res
->flags
& R600_RESOURCE_FLAG_UNMAPPABLE
) {
163 res
->domains
= RADEON_DOMAIN_VRAM
;
164 res
->flags
|= RADEON_FLAG_NO_CPU_ACCESS
|
168 /* Displayable and shareable surfaces are not suballocated. */
169 if (res
->b
.b
.bind
& (PIPE_BIND_SHARED
| PIPE_BIND_SCANOUT
))
170 res
->flags
|= RADEON_FLAG_NO_SUBALLOC
; /* shareable */
172 res
->flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
174 /* If VRAM is just stolen system memory, allow both VRAM and
175 * GTT, whichever has free space. If a buffer is evicted from
176 * VRAM to GTT, it will stay there.
178 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
179 * placements even with a low amount of stolen VRAM.
181 if (!rscreen
->info
.has_dedicated_vram
&&
182 (rscreen
->info
.drm_major
< 3 || rscreen
->info
.drm_minor
< 6) &&
183 res
->domains
== RADEON_DOMAIN_VRAM
) {
184 res
->domains
= RADEON_DOMAIN_VRAM_GTT
;
185 res
->flags
&= ~RADEON_FLAG_NO_CPU_ACCESS
; /* disallowed with VRAM_GTT */
188 if (rscreen
->debug_flags
& DBG(NO_WC
))
189 res
->flags
&= ~RADEON_FLAG_GTT_WC
;
191 /* Set expected VRAM and GART usage for the buffer. */
194 res
->max_forced_staging_uploads
= 0;
195 res
->b
.max_forced_staging_uploads
= 0;
197 if (res
->domains
& RADEON_DOMAIN_VRAM
) {
198 res
->vram_usage
= size
;
200 res
->max_forced_staging_uploads
=
201 res
->b
.max_forced_staging_uploads
=
202 rscreen
->info
.has_dedicated_vram
&&
203 size
>= rscreen
->info
.vram_vis_size
/ 4 ? 1 : 0;
204 } else if (res
->domains
& RADEON_DOMAIN_GTT
) {
205 res
->gart_usage
= size
;
209 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
210 struct r600_resource
*res
)
212 struct pb_buffer
*old_buf
, *new_buf
;
214 /* Allocate a new resource. */
215 new_buf
= rscreen
->ws
->buffer_create(rscreen
->ws
, res
->bo_size
,
217 res
->domains
, res
->flags
);
222 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
223 * NULL. This should prevent crashes with multiple contexts using
224 * the same buffer where one of the contexts invalidates it while
225 * the others are using it. */
227 res
->buf
= new_buf
; /* should be atomic */
229 if (rscreen
->info
.has_virtual_memory
)
230 res
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(res
->buf
);
232 res
->gpu_address
= 0;
234 pb_reference(&old_buf
, NULL
);
236 util_range_set_empty(&res
->valid_buffer_range
);
237 res
->TC_L2_dirty
= false;
239 /* Print debug information. */
240 if (rscreen
->debug_flags
& DBG(VM
) && res
->b
.b
.target
== PIPE_BUFFER
) {
241 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %"PRIu64
" bytes\n",
242 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
248 static void r600_buffer_destroy(struct pipe_screen
*screen
,
249 struct pipe_resource
*buf
)
251 struct r600_resource
*rbuffer
= r600_resource(buf
);
253 threaded_resource_deinit(buf
);
254 util_range_destroy(&rbuffer
->valid_buffer_range
);
255 pb_reference(&rbuffer
->buf
, NULL
);
260 r600_invalidate_buffer(struct r600_common_context
*rctx
,
261 struct r600_resource
*rbuffer
)
263 /* Shared buffers can't be reallocated. */
264 if (rbuffer
->b
.is_shared
)
267 /* Sparse buffers can't be reallocated. */
268 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
)
271 /* In AMD_pinned_memory, the user pointer association only gets
272 * broken when the buffer is explicitly re-allocated.
274 if (rbuffer
->b
.is_user_ptr
)
277 /* Check if mapping this buffer would cause waiting for the GPU. */
278 if (si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
279 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
280 rctx
->invalidate_buffer(&rctx
->b
, &rbuffer
->b
.b
);
282 util_range_set_empty(&rbuffer
->valid_buffer_range
);
288 /* Replace the storage of dst with src. */
289 void si_replace_buffer_storage(struct pipe_context
*ctx
,
290 struct pipe_resource
*dst
,
291 struct pipe_resource
*src
)
293 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
294 struct r600_resource
*rdst
= r600_resource(dst
);
295 struct r600_resource
*rsrc
= r600_resource(src
);
296 uint64_t old_gpu_address
= rdst
->gpu_address
;
298 pb_reference(&rdst
->buf
, rsrc
->buf
);
299 rdst
->gpu_address
= rsrc
->gpu_address
;
300 rdst
->b
.b
.bind
= rsrc
->b
.b
.bind
;
301 rdst
->b
.max_forced_staging_uploads
= rsrc
->b
.max_forced_staging_uploads
;
302 rdst
->max_forced_staging_uploads
= rsrc
->max_forced_staging_uploads
;
303 rdst
->flags
= rsrc
->flags
;
305 assert(rdst
->vram_usage
== rsrc
->vram_usage
);
306 assert(rdst
->gart_usage
== rsrc
->gart_usage
);
307 assert(rdst
->bo_size
== rsrc
->bo_size
);
308 assert(rdst
->bo_alignment
== rsrc
->bo_alignment
);
309 assert(rdst
->domains
== rsrc
->domains
);
311 rctx
->rebind_buffer(ctx
, dst
, old_gpu_address
);
314 static void si_invalidate_resource(struct pipe_context
*ctx
,
315 struct pipe_resource
*resource
)
317 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
318 struct r600_resource
*rbuffer
= r600_resource(resource
);
320 /* We currently only do anyting here for buffers */
321 if (resource
->target
== PIPE_BUFFER
)
322 (void)r600_invalidate_buffer(rctx
, rbuffer
);
325 static void *r600_buffer_get_transfer(struct pipe_context
*ctx
,
326 struct pipe_resource
*resource
,
328 const struct pipe_box
*box
,
329 struct pipe_transfer
**ptransfer
,
330 void *data
, struct r600_resource
*staging
,
333 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
334 struct r600_transfer
*transfer
;
336 if (usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
)
337 transfer
= slab_alloc(&rctx
->pool_transfers_unsync
);
339 transfer
= slab_alloc(&rctx
->pool_transfers
);
341 transfer
->b
.b
.resource
= NULL
;
342 pipe_resource_reference(&transfer
->b
.b
.resource
, resource
);
343 transfer
->b
.b
.level
= 0;
344 transfer
->b
.b
.usage
= usage
;
345 transfer
->b
.b
.box
= *box
;
346 transfer
->b
.b
.stride
= 0;
347 transfer
->b
.b
.layer_stride
= 0;
348 transfer
->b
.staging
= NULL
;
349 transfer
->offset
= offset
;
350 transfer
->staging
= staging
;
351 *ptransfer
= &transfer
->b
.b
;
355 static void *r600_buffer_transfer_map(struct pipe_context
*ctx
,
356 struct pipe_resource
*resource
,
359 const struct pipe_box
*box
,
360 struct pipe_transfer
**ptransfer
)
362 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
363 struct r600_resource
*rbuffer
= r600_resource(resource
);
366 assert(box
->x
+ box
->width
<= resource
->width0
);
368 /* From GL_AMD_pinned_memory issues:
370 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
371 * same system address which was specified at creation time?
373 * RESOLVED: NO. The GL implementation might return a different
374 * virtual mapping of that memory, although the same physical
377 * So don't ever use staging buffers.
379 if (rbuffer
->b
.is_user_ptr
)
380 usage
|= PIPE_TRANSFER_PERSISTENT
;
382 /* See if the buffer range being mapped has never been initialized,
383 * in which case it can be mapped unsynchronized. */
384 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
385 TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
)) &&
386 usage
& PIPE_TRANSFER_WRITE
&&
387 !rbuffer
->b
.is_shared
&&
388 !util_ranges_intersect(&rbuffer
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
389 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
392 /* If discarding the entire range, discard the whole resource instead. */
393 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
394 box
->x
== 0 && box
->width
== resource
->width0
) {
395 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
398 /* If a buffer in VRAM is too large and the range is discarded, don't
399 * map it directly. This makes sure that the buffer stays in VRAM.
401 bool force_discard_range
= false;
402 if (usage
& (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
403 PIPE_TRANSFER_DISCARD_RANGE
) &&
404 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
405 /* Try not to decrement the counter if it's not positive. Still racy,
406 * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
407 rbuffer
->max_forced_staging_uploads
> 0 &&
408 p_atomic_dec_return(&rbuffer
->max_forced_staging_uploads
) >= 0) {
409 usage
&= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
410 PIPE_TRANSFER_UNSYNCHRONIZED
);
411 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
412 force_discard_range
= true;
415 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
416 !(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
417 TC_TRANSFER_MAP_NO_INVALIDATE
))) {
418 assert(usage
& PIPE_TRANSFER_WRITE
);
420 if (r600_invalidate_buffer(rctx
, rbuffer
)) {
421 /* At this point, the buffer is always idle. */
422 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
424 /* Fall back to a temporary buffer. */
425 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
429 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
430 ((!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
431 PIPE_TRANSFER_PERSISTENT
))) ||
432 (rbuffer
->flags
& RADEON_FLAG_SPARSE
))) {
433 assert(usage
& PIPE_TRANSFER_WRITE
);
435 /* Check if mapping this buffer would cause waiting for the GPU.
437 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
||
438 force_discard_range
||
439 si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
440 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
441 /* Do a wait-free write-only transfer using a temporary buffer. */
443 struct r600_resource
*staging
= NULL
;
445 u_upload_alloc(ctx
->stream_uploader
, 0,
446 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
),
447 rctx
->screen
->info
.tcc_cache_line_size
,
448 &offset
, (struct pipe_resource
**)&staging
,
452 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
453 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
454 ptransfer
, data
, staging
, offset
);
455 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
459 /* At this point, the buffer is always idle (we checked it above). */
460 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
463 /* Use a staging buffer in cached GTT for reads. */
464 else if (((usage
& PIPE_TRANSFER_READ
) &&
465 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
466 (rbuffer
->domains
& RADEON_DOMAIN_VRAM
||
467 rbuffer
->flags
& RADEON_FLAG_GTT_WC
)) ||
468 (rbuffer
->flags
& RADEON_FLAG_SPARSE
)) {
469 struct r600_resource
*staging
;
471 assert(!(usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
));
472 staging
= (struct r600_resource
*) pipe_buffer_create(
473 ctx
->screen
, 0, PIPE_USAGE_STAGING
,
474 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
));
476 /* Copy the VRAM buffer to the staging buffer. */
477 rctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
478 box
->x
% R600_MAP_BUFFER_ALIGNMENT
,
479 0, 0, resource
, 0, box
);
481 data
= si_buffer_map_sync_with_rings(rctx
, staging
,
482 usage
& ~PIPE_TRANSFER_UNSYNCHRONIZED
);
484 r600_resource_reference(&staging
, NULL
);
487 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
489 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
490 ptransfer
, data
, staging
, 0);
491 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
496 data
= si_buffer_map_sync_with_rings(rctx
, rbuffer
, usage
);
502 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
503 ptransfer
, data
, NULL
, 0);
506 static void r600_buffer_do_flush_region(struct pipe_context
*ctx
,
507 struct pipe_transfer
*transfer
,
508 const struct pipe_box
*box
)
510 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
511 struct r600_resource
*rbuffer
= r600_resource(transfer
->resource
);
513 if (rtransfer
->staging
) {
514 struct pipe_resource
*dst
, *src
;
516 struct pipe_box dma_box
;
518 dst
= transfer
->resource
;
519 src
= &rtransfer
->staging
->b
.b
;
520 soffset
= rtransfer
->offset
+ box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
522 u_box_1d(soffset
, box
->width
, &dma_box
);
524 /* Copy the staging buffer into the original one. */
525 ctx
->resource_copy_region(ctx
, dst
, 0, box
->x
, 0, 0, src
, 0, &dma_box
);
528 util_range_add(&rbuffer
->valid_buffer_range
, box
->x
,
529 box
->x
+ box
->width
);
532 static void r600_buffer_flush_region(struct pipe_context
*ctx
,
533 struct pipe_transfer
*transfer
,
534 const struct pipe_box
*rel_box
)
536 unsigned required_usage
= PIPE_TRANSFER_WRITE
|
537 PIPE_TRANSFER_FLUSH_EXPLICIT
;
539 if ((transfer
->usage
& required_usage
) == required_usage
) {
542 u_box_1d(transfer
->box
.x
+ rel_box
->x
, rel_box
->width
, &box
);
543 r600_buffer_do_flush_region(ctx
, transfer
, &box
);
547 static void r600_buffer_transfer_unmap(struct pipe_context
*ctx
,
548 struct pipe_transfer
*transfer
)
550 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
551 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
553 if (transfer
->usage
& PIPE_TRANSFER_WRITE
&&
554 !(transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
))
555 r600_buffer_do_flush_region(ctx
, transfer
, &transfer
->box
);
557 r600_resource_reference(&rtransfer
->staging
, NULL
);
558 assert(rtransfer
->b
.staging
== NULL
); /* for threaded context only */
559 pipe_resource_reference(&transfer
->resource
, NULL
);
561 /* Don't use pool_transfers_unsync. We are always in the driver
563 slab_free(&rctx
->pool_transfers
, transfer
);
566 static void si_buffer_subdata(struct pipe_context
*ctx
,
567 struct pipe_resource
*buffer
,
568 unsigned usage
, unsigned offset
,
569 unsigned size
, const void *data
)
571 struct pipe_transfer
*transfer
= NULL
;
575 u_box_1d(offset
, size
, &box
);
576 map
= r600_buffer_transfer_map(ctx
, buffer
, 0,
577 PIPE_TRANSFER_WRITE
|
578 PIPE_TRANSFER_DISCARD_RANGE
|
584 memcpy(map
, data
, size
);
585 r600_buffer_transfer_unmap(ctx
, transfer
);
588 static const struct u_resource_vtbl r600_buffer_vtbl
=
590 NULL
, /* get_handle */
591 r600_buffer_destroy
, /* resource_destroy */
592 r600_buffer_transfer_map
, /* transfer_map */
593 r600_buffer_flush_region
, /* transfer_flush_region */
594 r600_buffer_transfer_unmap
, /* transfer_unmap */
597 static struct r600_resource
*
598 r600_alloc_buffer_struct(struct pipe_screen
*screen
,
599 const struct pipe_resource
*templ
)
601 struct r600_resource
*rbuffer
;
603 rbuffer
= MALLOC_STRUCT(r600_resource
);
605 rbuffer
->b
.b
= *templ
;
606 rbuffer
->b
.b
.next
= NULL
;
607 pipe_reference_init(&rbuffer
->b
.b
.reference
, 1);
608 rbuffer
->b
.b
.screen
= screen
;
610 rbuffer
->b
.vtbl
= &r600_buffer_vtbl
;
611 threaded_resource_init(&rbuffer
->b
.b
);
614 rbuffer
->bind_history
= 0;
615 rbuffer
->TC_L2_dirty
= false;
616 util_range_init(&rbuffer
->valid_buffer_range
);
620 static struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
621 const struct pipe_resource
*templ
,
624 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
625 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
627 si_init_resource_fields(rscreen
, rbuffer
, templ
->width0
, alignment
);
629 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
630 rbuffer
->flags
|= RADEON_FLAG_SPARSE
;
632 if (!si_alloc_resource(rscreen
, rbuffer
)) {
636 return &rbuffer
->b
.b
;
639 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
645 struct pipe_resource buffer
;
647 memset(&buffer
, 0, sizeof buffer
);
648 buffer
.target
= PIPE_BUFFER
;
649 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
651 buffer
.usage
= usage
;
652 buffer
.flags
= flags
;
653 buffer
.width0
= size
;
656 buffer
.array_size
= 1;
657 return si_buffer_create(screen
, &buffer
, alignment
);
660 static struct pipe_resource
*
661 si_buffer_from_user_memory(struct pipe_screen
*screen
,
662 const struct pipe_resource
*templ
,
665 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
666 struct radeon_winsys
*ws
= rscreen
->ws
;
667 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
669 rbuffer
->domains
= RADEON_DOMAIN_GTT
;
671 rbuffer
->b
.is_user_ptr
= true;
672 util_range_add(&rbuffer
->valid_buffer_range
, 0, templ
->width0
);
673 util_range_add(&rbuffer
->b
.valid_buffer_range
, 0, templ
->width0
);
675 /* Convert a user pointer to a buffer. */
676 rbuffer
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
682 if (rscreen
->info
.has_virtual_memory
)
683 rbuffer
->gpu_address
=
684 ws
->buffer_get_virtual_address(rbuffer
->buf
);
686 rbuffer
->gpu_address
= 0;
688 rbuffer
->vram_usage
= 0;
689 rbuffer
->gart_usage
= templ
->width0
;
691 return &rbuffer
->b
.b
;
694 static struct pipe_resource
*si_resource_create(struct pipe_screen
*screen
,
695 const struct pipe_resource
*templ
)
697 if (templ
->target
== PIPE_BUFFER
) {
698 return si_buffer_create(screen
, templ
, 256);
700 return si_texture_create(screen
, templ
);
704 void si_init_screen_buffer_functions(struct si_screen
*sscreen
)
706 sscreen
->b
.b
.resource_create
= si_resource_create
;
707 sscreen
->b
.b
.resource_destroy
= u_resource_destroy_vtbl
;
708 sscreen
->b
.b
.resource_from_user_memory
= si_buffer_from_user_memory
;
711 void si_init_buffer_functions(struct si_context
*sctx
)
713 sctx
->b
.b
.invalidate_resource
= si_invalidate_resource
;
714 sctx
->b
.b
.transfer_map
= u_transfer_map_vtbl
;
715 sctx
->b
.b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
716 sctx
->b
.b
.transfer_unmap
= u_transfer_unmap_vtbl
;
717 sctx
->b
.b
.texture_subdata
= u_default_texture_subdata
;
718 sctx
->b
.b
.buffer_subdata
= si_buffer_subdata
;