src/gallium/drivers/radeon/r600_cs.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * This file contains helpers for writing commands to commands streams.
  27  */
  28
  29 #ifndef R600_CS_H
  30 #define R600_CS_H
  31
  32 #include "radeonsi/si_pipe.h"
  33 #include "amd/common/sid.h"
  34
  35 /**
  36  * Return true if there is enough memory in VRAM and GTT for the buffers
  37  * added so far.
  38  *
  39  * \param vram      VRAM memory size not added to the buffer list yet
  40  * \param gtt       GTT memory size not added to the buffer list yet
  41  */
  42 static inline bool
  43 radeon_cs_memory_below_limit(struct si_screen *screen,
  44                              struct radeon_winsys_cs *cs,
  45                              uint64_t vram, uint64_t gtt)
  46 {
  47         vram += cs->used_vram;
  48         gtt += cs->used_gart;
  49
  50         /* Anything that goes above the VRAM size should go to GTT. */
  51         if (vram > screen->info.vram_size)
  52                 gtt += vram - screen->info.vram_size;
  53
  54         /* Now we just need to check if we have enough GTT. */
  55         return gtt < screen->info.gart_size * 0.7;
  56 }
  57
  58 /**
  59  * Add a buffer to the buffer list for the given command stream (CS).
  60  *
  61  * All buffers used by a CS must be added to the list. This tells the kernel
  62  * driver which buffers are used by GPU commands. Other buffers can
  63  * be swapped out (not accessible) during execution.
  64  *
  65  * The buffer list becomes empty after every context flush and must be
  66  * rebuilt.
  67  */
  68 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
  69                                              struct radeon_winsys_cs *cs,
  70                                              struct r600_resource *rbo,
  71                                              enum radeon_bo_usage usage,
  72                                              enum radeon_bo_priority priority)
  73 {
  74         assert(usage);
  75         sctx->b.ws->cs_add_buffer(
  76                 cs, rbo->buf,
  77                 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
  78                 rbo->domains, priority);
  79 }
  80
  81 /**
  82  * Same as above, but also checks memory usage and flushes the context
  83  * accordingly.
  84  *
  85  * When this SHOULD NOT be used:
  86  *
  87  * - if r600_context_add_resource_size has been called for the buffer
  88  *   followed by *_need_cs_space for checking the memory usage
  89  *
  90  * - if r600_need_dma_space has been called for the buffer
  91  *
  92  * - when emitting state packets and draw packets (because preceding packets
  93  *   can't be re-emitted at that point)
  94  *
  95  * - if shader resource "enabled_mask" is not up-to-date or there is
  96  *   a different constraint disallowing a context flush
  97  */
  98 static inline void
  99 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
 100                                         struct r600_resource *rbo,
 101                                         enum radeon_bo_usage usage,
 102                                         enum radeon_bo_priority priority,
 103                                         bool check_mem)
 104 {
 105         if (check_mem &&
 106             !radeon_cs_memory_below_limit(sctx->screen, sctx->b.gfx_cs,
 107                                           sctx->b.vram + rbo->vram_usage,
 108                                           sctx->b.gtt + rbo->gart_usage))
 109                 si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
 110
 111         radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, rbo, usage, priority);
 112 }
 113
 114 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 115 {
 116         assert(reg < SI_CONTEXT_REG_OFFSET);
 117         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 118         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
 119         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 120 }
 121
 122 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 123 {
 124         radeon_set_config_reg_seq(cs, reg, 1);
 125         radeon_emit(cs, value);
 126 }
 127
 128 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 129 {
 130         assert(reg >= SI_CONTEXT_REG_OFFSET);
 131         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 132         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
 133         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 134 }
 135
 136 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 137 {
 138         radeon_set_context_reg_seq(cs, reg, 1);
 139         radeon_emit(cs, value);
 140 }
 141
 142 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 143                                               unsigned reg, unsigned idx,
 144                                               unsigned value)
 145 {
 146         assert(reg >= SI_CONTEXT_REG_OFFSET);
 147         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 148         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
 149         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
 150         radeon_emit(cs, value);
 151 }
 152
 153 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 154 {
 155         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 156         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 157         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 158         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 159 }
 160
 161 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 162 {
 163         radeon_set_sh_reg_seq(cs, reg, 1);
 164         radeon_emit(cs, value);
 165 }
 166
 167 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 168 {
 169         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 170         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 171         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 172         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 173 }
 174
 175 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 176 {
 177         radeon_set_uconfig_reg_seq(cs, reg, 1);
 178         radeon_emit(cs, value);
 179 }
 180
 181 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
 182                                               unsigned reg, unsigned idx,
 183                                               unsigned value)
 184 {
 185         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 186         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 187         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
 188         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
 189         radeon_emit(cs, value);
 190 }
 191
 192 #endif