src/gallium/drivers/radeon/r600_cs.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  */
  25
  26 /**
  27  * This file contains helpers for writing commands to commands streams.
  28  */
  29
  30 #ifndef R600_CS_H
  31 #define R600_CS_H
  32
  33 #include "r600_pipe_common.h"
  34 #include "r600d_common.h"
  35
  36 /**
  37  * Add a buffer to the buffer list for the given command stream (CS).
  38  *
  39  * All buffers used by a CS must be added to the list. This tells the kernel
  40  * driver which buffers are used by GPU commands. Other buffers can
  41  * be swapped out (not accessible) during execution.
  42  *
  43  * The buffer list becomes empty after every context flush and must be
  44  * rebuilt.
  45  */
  46 static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
  47                                                  struct r600_ring *ring,
  48                                                  struct r600_resource *rbo,
  49                                                  enum radeon_bo_usage usage,
  50                                                  enum radeon_bo_priority priority)
  51 {
  52         assert(usage);
  53         return rctx->ws->cs_add_buffer(ring->cs, rbo->buf, usage,
  54                                       rbo->domains, priority) * 4;
  55 }
  56
  57 /**
  58  * Same as above, but also checks memory usage and flushes the context
  59  * accordingly.
  60  *
  61  * When this SHOULD NOT be used:
  62  *
  63  * - if r600_context_add_resource_size has been called for the buffer
  64  *   followed by *_need_cs_space for checking the memory usage
  65  *
  66  * - if r600_need_dma_space has been called for the buffer
  67  *
  68  * - when emitting state packets and draw packets (because preceding packets
  69  *   can't be re-emitted at that point)
  70  *
  71  * - if shader resource "enabled_mask" is not up-to-date or there is
  72  *   a different constraint disallowing a context flush
  73  */
  74 static inline unsigned
  75 radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
  76                                     struct r600_ring *ring,
  77                                     struct r600_resource *rbo,
  78                                     enum radeon_bo_usage usage,
  79                                     enum radeon_bo_priority priority,
  80                                     bool check_mem)
  81 {
  82         if (check_mem &&
  83             !rctx->ws->cs_memory_below_limit(ring->cs,
  84                                              rctx->vram + rbo->vram_usage,
  85                                              rctx->gtt + rbo->gart_usage))
  86                 ring->flush(rctx, RADEON_FLUSH_ASYNC, NULL);
  87
  88         return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
  89 }
  90
  91 static inline void r600_emit_reloc(struct r600_common_context *rctx,
  92                                    struct r600_ring *ring, struct r600_resource *rbo,
  93                                    enum radeon_bo_usage usage,
  94                                    enum radeon_bo_priority priority)
  95 {
  96         struct radeon_winsys_cs *cs = ring->cs;
  97         bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.has_virtual_memory;
  98         unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
  99
 100         if (!has_vm) {
 101                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 102                 radeon_emit(cs, reloc);
 103         }
 104 }
 105
 106 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 107 {
 108         assert(reg < R600_CONTEXT_REG_OFFSET);
 109         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 110         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
 111         radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
 112 }
 113
 114 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 115 {
 116         radeon_set_config_reg_seq(cs, reg, 1);
 117         radeon_emit(cs, value);
 118 }
 119
 120 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 121 {
 122         assert(reg >= R600_CONTEXT_REG_OFFSET);
 123         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 124         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
 125         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
 126 }
 127
 128 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 129 {
 130         radeon_set_context_reg_seq(cs, reg, 1);
 131         radeon_emit(cs, value);
 132 }
 133
 134 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 135                                               unsigned reg, unsigned idx,
 136                                               unsigned value)
 137 {
 138         assert(reg >= R600_CONTEXT_REG_OFFSET);
 139         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 140         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
 141         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
 142         radeon_emit(cs, value);
 143 }
 144
 145 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 146 {
 147         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 148         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 149         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 150         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 151 }
 152
 153 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 154 {
 155         radeon_set_sh_reg_seq(cs, reg, 1);
 156         radeon_emit(cs, value);
 157 }
 158
 159 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 160 {
 161         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 162         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 163         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 164         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 165 }
 166
 167 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 168 {
 169         radeon_set_uconfig_reg_seq(cs, reg, 1);
 170         radeon_emit(cs, value);
 171 }
 172
 173 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
 174                                               unsigned reg, unsigned idx,
 175                                               unsigned value)
 176 {
 177         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 178         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 179         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
 180         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
 181         radeon_emit(cs, value);
 182 }
 183
 184 #endif