src/gallium/drivers/radeon/r600_cs.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  */
  25
  26 /**
  27  * This file contains helpers for writing commands to commands streams.
  28  */
  29
  30 #ifndef R600_CS_H
  31 #define R600_CS_H
  32
  33 #include "r600_pipe_common.h"
  34 #include "r600d_common.h"
  35
  36 static INLINE unsigned r600_context_bo_reloc(struct r600_common_context *rctx,
  37                                              struct r600_ring *ring,
  38                                              struct r600_resource *rbo,
  39                                              enum radeon_bo_usage usage,
  40                                              enum radeon_bo_priority priority)
  41 {
  42         assert(usage);
  43
  44         /* Make sure that all previous rings are flushed so that everything
  45          * looks serialized from the driver point of view.
  46          */
  47         if (!ring->flushing) {
  48                 if (ring == &rctx->rings.gfx) {
  49                         if (rctx->rings.dma.cs) {
  50                                 /* flush dma ring */
  51                                 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
  52                         }
  53                 } else {
  54                         /* flush gfx ring */
  55                         rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
  56                 }
  57         }
  58         return rctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage,
  59                                       rbo->domains, priority) * 4;
  60 }
  61
  62 static INLINE void r600_emit_reloc(struct r600_common_context *rctx,
  63                                    struct r600_ring *ring, struct r600_resource *rbo,
  64                                    enum radeon_bo_usage usage,
  65                                    enum radeon_bo_priority priority)
  66 {
  67         struct radeon_winsys_cs *cs = ring->cs;
  68         bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_virtual_address;
  69         unsigned reloc = r600_context_bo_reloc(rctx, ring, rbo, usage, priority);
  70
  71         if (!has_vm) {
  72                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
  73                 radeon_emit(cs, reloc);
  74         }
  75 }
  76
  77 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  78 {
  79         assert(reg < R600_CONTEXT_REG_OFFSET);
  80         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
  81         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
  82         radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
  83 }
  84
  85 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  86 {
  87         r600_write_config_reg_seq(cs, reg, 1);
  88         radeon_emit(cs, value);
  89 }
  90
  91 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  92 {
  93         assert(reg >= R600_CONTEXT_REG_OFFSET);
  94         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
  95         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
  96         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
  97 }
  98
  99 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 100 {
 101         r600_write_context_reg_seq(cs, reg, 1);
 102         radeon_emit(cs, value);
 103 }
 104
 105 static INLINE void si_write_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 106 {
 107         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 108         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 109         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 110         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 111 }
 112
 113 static INLINE void si_write_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 114 {
 115         si_write_sh_reg_seq(cs, reg, 1);
 116         radeon_emit(cs, value);
 117 }
 118
 119 static INLINE void cik_write_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 120 {
 121         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 122         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 123         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 124         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 125 }
 126
 127 static INLINE void cik_write_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 128 {
 129         cik_write_uconfig_reg_seq(cs, reg, 1);
 130         radeon_emit(cs, value);
 131 }
 132
 133 #endif