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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50 };
51
52 /*
53 * shader binary helpers.
54 */
55 void radeon_shader_binary_init(struct radeon_shader_binary *b)
56 {
57 memset(b, 0, sizeof(*b));
58 }
59
60 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
61 {
62 if (!b)
63 return;
64 FREE(b->code);
65 FREE(b->config);
66 FREE(b->rodata);
67 FREE(b->global_symbol_offsets);
68 FREE(b->relocs);
69 FREE(b->disasm_string);
70 }
71
72 /*
73 * pipe_context
74 */
75
76 void r600_draw_rectangle(struct blitter_context *blitter,
77 int x1, int y1, int x2, int y2, float depth,
78 enum blitter_attrib_type type,
79 const union pipe_color_union *attrib)
80 {
81 struct r600_common_context *rctx =
82 (struct r600_common_context*)util_blitter_get_pipe(blitter);
83 struct pipe_viewport_state viewport;
84 struct pipe_resource *buf = NULL;
85 unsigned offset = 0;
86 float *vb;
87
88 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
89 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
90 return;
91 }
92
93 /* Some operations (like color resolve on r6xx) don't work
94 * with the conventional primitive types.
95 * One that works is PT_RECTLIST, which we use here. */
96
97 /* setup viewport */
98 viewport.scale[0] = 1.0f;
99 viewport.scale[1] = 1.0f;
100 viewport.scale[2] = 1.0f;
101 viewport.translate[0] = 0.0f;
102 viewport.translate[1] = 0.0f;
103 viewport.translate[2] = 0.0f;
104 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
105
106 /* Upload vertices. The hw rectangle has only 3 vertices,
107 * I guess the 4th one is derived from the first 3.
108 * The vertex specification should match u_blitter's vertex element state. */
109 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
110 if (!buf)
111 return;
112
113 vb[0] = x1;
114 vb[1] = y1;
115 vb[2] = depth;
116 vb[3] = 1;
117
118 vb[8] = x1;
119 vb[9] = y2;
120 vb[10] = depth;
121 vb[11] = 1;
122
123 vb[16] = x2;
124 vb[17] = y1;
125 vb[18] = depth;
126 vb[19] = 1;
127
128 if (attrib) {
129 memcpy(vb+4, attrib->f, sizeof(float)*4);
130 memcpy(vb+12, attrib->f, sizeof(float)*4);
131 memcpy(vb+20, attrib->f, sizeof(float)*4);
132 }
133
134 /* draw */
135 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
136 R600_PRIM_RECTANGLE_LIST, 3, 2);
137 pipe_resource_reference(&buf, NULL);
138 }
139
140 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
141 struct r600_resource *dst, struct r600_resource *src)
142 {
143 uint64_t vram = 0, gtt = 0;
144
145 if (dst) {
146 if (dst->domains & RADEON_DOMAIN_VRAM)
147 vram += dst->buf->size;
148 else if (dst->domains & RADEON_DOMAIN_GTT)
149 gtt += dst->buf->size;
150 }
151 if (src) {
152 if (src->domains & RADEON_DOMAIN_VRAM)
153 vram += src->buf->size;
154 else if (src->domains & RADEON_DOMAIN_GTT)
155 gtt += src->buf->size;
156 }
157
158 /* Flush the GFX IB if DMA depends on it. */
159 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
160 ((dst &&
161 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
162 RADEON_USAGE_READWRITE)) ||
163 (src &&
164 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
165 RADEON_USAGE_WRITE))))
166 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
167
168 /* Flush if there's not enough space, or if the memory usage per IB
169 * is too large.
170 */
171 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
172 !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
173 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
174 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
175 }
176
177 /* If GPUVM is not supported, the CS checker needs 2 entries
178 * in the buffer list per packet, which has to be done manually.
179 */
180 if (ctx->screen->info.has_virtual_memory) {
181 if (dst)
182 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
183 RADEON_USAGE_WRITE,
184 RADEON_PRIO_SDMA_BUFFER);
185 if (src)
186 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
187 RADEON_USAGE_READ,
188 RADEON_PRIO_SDMA_BUFFER);
189 }
190 }
191
192 /* This is required to prevent read-after-write hazards. */
193 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
194 {
195 struct radeon_winsys_cs *cs = rctx->dma.cs;
196
197 /* done at the end of DMA calls, so increment this. */
198 rctx->num_dma_calls++;
199
200 /* IBs using too little memory are limited by the IB submission overhead.
201 * IBs using too much memory are limited by the kernel/TTM overhead.
202 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
203 *
204 * This heuristic makes sure that DMA requests are executed
205 * very soon after the call is made and lowers memory usage.
206 * It improves texture upload performance by keeping the DMA
207 * engine busy while uploads are being submitted.
208 */
209 if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
210 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
211 return;
212 }
213
214 r600_need_dma_space(rctx, 1, NULL, NULL);
215
216 if (!radeon_emitted(cs, 0)) /* empty queue */
217 return;
218
219 /* NOP waits for idle on Evergreen and later. */
220 if (rctx->chip_class >= CIK)
221 radeon_emit(cs, 0x00000000); /* NOP */
222 else if (rctx->chip_class >= EVERGREEN)
223 radeon_emit(cs, 0xf0000000); /* NOP */
224 else {
225 /* TODO: R600-R700 should use the FENCE packet.
226 * CS checker support is required. */
227 }
228 }
229
230 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
231 {
232 }
233
234 void r600_preflush_suspend_features(struct r600_common_context *ctx)
235 {
236 /* suspend queries */
237 if (!LIST_IS_EMPTY(&ctx->active_queries))
238 r600_suspend_queries(ctx);
239
240 ctx->streamout.suspended = false;
241 if (ctx->streamout.begin_emitted) {
242 r600_emit_streamout_end(ctx);
243 ctx->streamout.suspended = true;
244 }
245 }
246
247 void r600_postflush_resume_features(struct r600_common_context *ctx)
248 {
249 if (ctx->streamout.suspended) {
250 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
251 r600_streamout_buffers_dirty(ctx);
252 }
253
254 /* resume queries */
255 if (!LIST_IS_EMPTY(&ctx->active_queries))
256 r600_resume_queries(ctx);
257 }
258
259 static void r600_flush_from_st(struct pipe_context *ctx,
260 struct pipe_fence_handle **fence,
261 unsigned flags)
262 {
263 struct pipe_screen *screen = ctx->screen;
264 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
265 unsigned rflags = 0;
266 struct pipe_fence_handle *gfx_fence = NULL;
267 struct pipe_fence_handle *sdma_fence = NULL;
268
269 if (flags & PIPE_FLUSH_END_OF_FRAME)
270 rflags |= RADEON_FLUSH_END_OF_FRAME;
271
272 if (rctx->dma.cs) {
273 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
274 }
275 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
276
277 /* Both engines can signal out of order, so we need to keep both fences. */
278 if (gfx_fence || sdma_fence) {
279 struct r600_multi_fence *multi_fence =
280 CALLOC_STRUCT(r600_multi_fence);
281 if (!multi_fence)
282 return;
283
284 multi_fence->reference.count = 1;
285 multi_fence->gfx = gfx_fence;
286 multi_fence->sdma = sdma_fence;
287
288 screen->fence_reference(screen, fence, NULL);
289 *fence = (struct pipe_fence_handle*)multi_fence;
290 }
291 }
292
293 static void r600_flush_dma_ring(void *ctx, unsigned flags,
294 struct pipe_fence_handle **fence)
295 {
296 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
297 struct radeon_winsys_cs *cs = rctx->dma.cs;
298 struct radeon_saved_cs saved;
299 bool check_vm =
300 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
301 rctx->check_vm_faults;
302
303 if (!radeon_emitted(cs, 0)) {
304 if (fence)
305 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
306 return;
307 }
308
309 if (check_vm)
310 radeon_save_cs(rctx->ws, cs, &saved);
311
312 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
313 if (fence)
314 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
315
316 if (check_vm) {
317 /* Use conservative timeout 800ms, after which we won't wait any
318 * longer and assume the GPU is hung.
319 */
320 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
321
322 rctx->check_vm_faults(rctx, &saved, RING_DMA);
323 radeon_clear_saved_cs(&saved);
324 }
325 }
326
327 /**
328 * Store a linearized copy of all chunks of \p cs together with the buffer
329 * list in \p saved.
330 */
331 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
332 struct radeon_saved_cs *saved)
333 {
334 void *buf;
335 unsigned i;
336
337 /* Save the IB chunks. */
338 saved->num_dw = cs->prev_dw + cs->current.cdw;
339 saved->ib = MALLOC(4 * saved->num_dw);
340 if (!saved->ib)
341 goto oom;
342
343 buf = saved->ib;
344 for (i = 0; i < cs->num_prev; ++i) {
345 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
346 buf += cs->prev[i].cdw;
347 }
348 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
349
350 /* Save the buffer list. */
351 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
352 saved->bo_list = CALLOC(saved->bo_count,
353 sizeof(saved->bo_list[0]));
354 if (!saved->bo_list) {
355 FREE(saved->ib);
356 goto oom;
357 }
358 ws->cs_get_buffer_list(cs, saved->bo_list);
359
360 return;
361
362 oom:
363 fprintf(stderr, "%s: out of memory\n", __func__);
364 memset(saved, 0, sizeof(*saved));
365 }
366
367 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
368 {
369 unsigned i;
370
371 FREE(saved->ib);
372
373 for (i = 0; i < saved->bo_count; i++)
374 pb_reference(&saved->bo_list[i].buf, NULL);
375 FREE(saved->bo_list);
376
377 memset(saved, 0, sizeof(*saved));
378 }
379
380 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
381 {
382 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
383 unsigned latest = rctx->ws->query_value(rctx->ws,
384 RADEON_GPU_RESET_COUNTER);
385
386 if (rctx->gpu_reset_counter == latest)
387 return PIPE_NO_RESET;
388
389 rctx->gpu_reset_counter = latest;
390 return PIPE_UNKNOWN_CONTEXT_RESET;
391 }
392
393 static void r600_set_debug_callback(struct pipe_context *ctx,
394 const struct pipe_debug_callback *cb)
395 {
396 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
397
398 if (cb)
399 rctx->debug = *cb;
400 else
401 memset(&rctx->debug, 0, sizeof(rctx->debug));
402 }
403
404 bool r600_common_context_init(struct r600_common_context *rctx,
405 struct r600_common_screen *rscreen)
406 {
407 util_slab_create(&rctx->pool_transfers,
408 sizeof(struct r600_transfer), 64,
409 UTIL_SLAB_SINGLETHREADED);
410
411 rctx->screen = rscreen;
412 rctx->ws = rscreen->ws;
413 rctx->family = rscreen->family;
414 rctx->chip_class = rscreen->chip_class;
415
416 if (rscreen->chip_class >= CIK)
417 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
418 else if (rscreen->chip_class >= EVERGREEN)
419 rctx->max_db = 8;
420 else
421 rctx->max_db = 4;
422
423 rctx->b.invalidate_resource = r600_invalidate_resource;
424 rctx->b.transfer_map = u_transfer_map_vtbl;
425 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
426 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
427 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
428 rctx->b.memory_barrier = r600_memory_barrier;
429 rctx->b.flush = r600_flush_from_st;
430 rctx->b.set_debug_callback = r600_set_debug_callback;
431
432 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
433 rctx->b.get_device_reset_status = r600_get_reset_status;
434 rctx->gpu_reset_counter =
435 rctx->ws->query_value(rctx->ws,
436 RADEON_GPU_RESET_COUNTER);
437 }
438
439 LIST_INITHEAD(&rctx->texture_buffers);
440
441 r600_init_context_texture_functions(rctx);
442 r600_init_viewport_functions(rctx);
443 r600_streamout_init(rctx);
444 r600_query_init(rctx);
445 cayman_init_msaa(&rctx->b);
446
447 rctx->allocator_zeroed_memory =
448 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
449 0, PIPE_USAGE_DEFAULT, true);
450 if (!rctx->allocator_zeroed_memory)
451 return false;
452
453 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
454 PIPE_BIND_INDEX_BUFFER |
455 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
456 if (!rctx->uploader)
457 return false;
458
459 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
460 if (!rctx->ctx)
461 return false;
462
463 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
464 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
465 r600_flush_dma_ring,
466 rctx);
467 rctx->dma.flush = r600_flush_dma_ring;
468 }
469
470 return true;
471 }
472
473 void r600_common_context_cleanup(struct r600_common_context *rctx)
474 {
475 if (rctx->gfx.cs)
476 rctx->ws->cs_destroy(rctx->gfx.cs);
477 if (rctx->dma.cs)
478 rctx->ws->cs_destroy(rctx->dma.cs);
479 if (rctx->ctx)
480 rctx->ws->ctx_destroy(rctx->ctx);
481
482 if (rctx->uploader) {
483 u_upload_destroy(rctx->uploader);
484 }
485
486 util_slab_destroy(&rctx->pool_transfers);
487
488 if (rctx->allocator_zeroed_memory) {
489 u_suballocator_destroy(rctx->allocator_zeroed_memory);
490 }
491 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
492 }
493
494 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
495 {
496 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
497 struct r600_resource *rr = (struct r600_resource *)r;
498
499 if (!r) {
500 return;
501 }
502
503 /*
504 * The idea is to compute a gross estimate of memory requirement of
505 * each draw call. After each draw call, memory will be precisely
506 * accounted. So the uncertainty is only on the current draw call.
507 * In practice this gave very good estimate (+/- 10% of the target
508 * memory limit).
509 */
510 if (rr->domains & RADEON_DOMAIN_VRAM)
511 rctx->vram += rr->buf->size;
512 else if (rr->domains & RADEON_DOMAIN_GTT)
513 rctx->gtt += rr->buf->size;
514 }
515
516 /*
517 * pipe_screen
518 */
519
520 static const struct debug_named_value common_debug_options[] = {
521 /* logging */
522 { "tex", DBG_TEX, "Print texture info" },
523 { "compute", DBG_COMPUTE, "Print compute info" },
524 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
525 { "info", DBG_INFO, "Print driver information" },
526
527 /* shaders */
528 { "fs", DBG_FS, "Print fetch shaders" },
529 { "vs", DBG_VS, "Print vertex shaders" },
530 { "gs", DBG_GS, "Print geometry shaders" },
531 { "ps", DBG_PS, "Print pixel shaders" },
532 { "cs", DBG_CS, "Print compute shaders" },
533 { "tcs", DBG_TCS, "Print tessellation control shaders" },
534 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
535 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
536 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
537 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
538 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
539
540 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
541
542 /* features */
543 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
544 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
545 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
546 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
547 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
548 { "notiling", DBG_NO_TILING, "Disable tiling" },
549 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
550 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
551 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
552 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
553 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
554 { "nodcc", DBG_NO_DCC, "Disable DCC." },
555 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
556 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
557 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
558 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
559 { "noce", DBG_NO_CE, "Disable the constant engine"},
560 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
561
562 DEBUG_NAMED_VALUE_END /* must be last */
563 };
564
565 static const char* r600_get_vendor(struct pipe_screen* pscreen)
566 {
567 return "X.Org";
568 }
569
570 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
571 {
572 return "AMD";
573 }
574
575 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
576 {
577 switch (rscreen->info.family) {
578 case CHIP_R600: return "AMD R600";
579 case CHIP_RV610: return "AMD RV610";
580 case CHIP_RV630: return "AMD RV630";
581 case CHIP_RV670: return "AMD RV670";
582 case CHIP_RV620: return "AMD RV620";
583 case CHIP_RV635: return "AMD RV635";
584 case CHIP_RS780: return "AMD RS780";
585 case CHIP_RS880: return "AMD RS880";
586 case CHIP_RV770: return "AMD RV770";
587 case CHIP_RV730: return "AMD RV730";
588 case CHIP_RV710: return "AMD RV710";
589 case CHIP_RV740: return "AMD RV740";
590 case CHIP_CEDAR: return "AMD CEDAR";
591 case CHIP_REDWOOD: return "AMD REDWOOD";
592 case CHIP_JUNIPER: return "AMD JUNIPER";
593 case CHIP_CYPRESS: return "AMD CYPRESS";
594 case CHIP_HEMLOCK: return "AMD HEMLOCK";
595 case CHIP_PALM: return "AMD PALM";
596 case CHIP_SUMO: return "AMD SUMO";
597 case CHIP_SUMO2: return "AMD SUMO2";
598 case CHIP_BARTS: return "AMD BARTS";
599 case CHIP_TURKS: return "AMD TURKS";
600 case CHIP_CAICOS: return "AMD CAICOS";
601 case CHIP_CAYMAN: return "AMD CAYMAN";
602 case CHIP_ARUBA: return "AMD ARUBA";
603 case CHIP_TAHITI: return "AMD TAHITI";
604 case CHIP_PITCAIRN: return "AMD PITCAIRN";
605 case CHIP_VERDE: return "AMD CAPE VERDE";
606 case CHIP_OLAND: return "AMD OLAND";
607 case CHIP_HAINAN: return "AMD HAINAN";
608 case CHIP_BONAIRE: return "AMD BONAIRE";
609 case CHIP_KAVERI: return "AMD KAVERI";
610 case CHIP_KABINI: return "AMD KABINI";
611 case CHIP_HAWAII: return "AMD HAWAII";
612 case CHIP_MULLINS: return "AMD MULLINS";
613 case CHIP_TONGA: return "AMD TONGA";
614 case CHIP_ICELAND: return "AMD ICELAND";
615 case CHIP_CARRIZO: return "AMD CARRIZO";
616 case CHIP_FIJI: return "AMD FIJI";
617 case CHIP_POLARIS10: return "AMD POLARIS10";
618 case CHIP_POLARIS11: return "AMD POLARIS11";
619 case CHIP_STONEY: return "AMD STONEY";
620 default: return "AMD unknown";
621 }
622 }
623
624 static const char* r600_get_name(struct pipe_screen* pscreen)
625 {
626 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
627
628 return rscreen->renderer_string;
629 }
630
631 static float r600_get_paramf(struct pipe_screen* pscreen,
632 enum pipe_capf param)
633 {
634 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
635
636 switch (param) {
637 case PIPE_CAPF_MAX_LINE_WIDTH:
638 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
639 case PIPE_CAPF_MAX_POINT_WIDTH:
640 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
641 if (rscreen->family >= CHIP_CEDAR)
642 return 16384.0f;
643 else
644 return 8192.0f;
645 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
646 return 16.0f;
647 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
648 return 16.0f;
649 case PIPE_CAPF_GUARD_BAND_LEFT:
650 case PIPE_CAPF_GUARD_BAND_TOP:
651 case PIPE_CAPF_GUARD_BAND_RIGHT:
652 case PIPE_CAPF_GUARD_BAND_BOTTOM:
653 return 0.0f;
654 }
655 return 0.0f;
656 }
657
658 static int r600_get_video_param(struct pipe_screen *screen,
659 enum pipe_video_profile profile,
660 enum pipe_video_entrypoint entrypoint,
661 enum pipe_video_cap param)
662 {
663 switch (param) {
664 case PIPE_VIDEO_CAP_SUPPORTED:
665 return vl_profile_supported(screen, profile, entrypoint);
666 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
667 return 1;
668 case PIPE_VIDEO_CAP_MAX_WIDTH:
669 case PIPE_VIDEO_CAP_MAX_HEIGHT:
670 return vl_video_buffer_max_size(screen);
671 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
672 return PIPE_FORMAT_NV12;
673 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
674 return false;
675 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
676 return false;
677 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
678 return true;
679 case PIPE_VIDEO_CAP_MAX_LEVEL:
680 return vl_level_supported(screen, profile);
681 default:
682 return 0;
683 }
684 }
685
686 const char *r600_get_llvm_processor_name(enum radeon_family family)
687 {
688 switch (family) {
689 case CHIP_R600:
690 case CHIP_RV630:
691 case CHIP_RV635:
692 case CHIP_RV670:
693 return "r600";
694 case CHIP_RV610:
695 case CHIP_RV620:
696 case CHIP_RS780:
697 case CHIP_RS880:
698 return "rs880";
699 case CHIP_RV710:
700 return "rv710";
701 case CHIP_RV730:
702 return "rv730";
703 case CHIP_RV740:
704 case CHIP_RV770:
705 return "rv770";
706 case CHIP_PALM:
707 case CHIP_CEDAR:
708 return "cedar";
709 case CHIP_SUMO:
710 case CHIP_SUMO2:
711 return "sumo";
712 case CHIP_REDWOOD:
713 return "redwood";
714 case CHIP_JUNIPER:
715 return "juniper";
716 case CHIP_HEMLOCK:
717 case CHIP_CYPRESS:
718 return "cypress";
719 case CHIP_BARTS:
720 return "barts";
721 case CHIP_TURKS:
722 return "turks";
723 case CHIP_CAICOS:
724 return "caicos";
725 case CHIP_CAYMAN:
726 case CHIP_ARUBA:
727 return "cayman";
728
729 case CHIP_TAHITI: return "tahiti";
730 case CHIP_PITCAIRN: return "pitcairn";
731 case CHIP_VERDE: return "verde";
732 case CHIP_OLAND: return "oland";
733 case CHIP_HAINAN: return "hainan";
734 case CHIP_BONAIRE: return "bonaire";
735 case CHIP_KABINI: return "kabini";
736 case CHIP_KAVERI: return "kaveri";
737 case CHIP_HAWAII: return "hawaii";
738 case CHIP_MULLINS:
739 return "mullins";
740 case CHIP_TONGA: return "tonga";
741 case CHIP_ICELAND: return "iceland";
742 case CHIP_CARRIZO: return "carrizo";
743 #if HAVE_LLVM <= 0x0307
744 case CHIP_FIJI: return "tonga";
745 case CHIP_STONEY: return "carrizo";
746 #else
747 case CHIP_FIJI: return "fiji";
748 case CHIP_STONEY: return "stoney";
749 #endif
750 #if HAVE_LLVM <= 0x0308
751 case CHIP_POLARIS10: return "tonga";
752 case CHIP_POLARIS11: return "tonga";
753 #else
754 case CHIP_POLARIS10: return "polaris10";
755 case CHIP_POLARIS11: return "polaris11";
756 #endif
757 default: return "";
758 }
759 }
760
761 static int r600_get_compute_param(struct pipe_screen *screen,
762 enum pipe_shader_ir ir_type,
763 enum pipe_compute_cap param,
764 void *ret)
765 {
766 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
767
768 //TODO: select these params by asic
769 switch (param) {
770 case PIPE_COMPUTE_CAP_IR_TARGET: {
771 const char *gpu;
772 const char *triple;
773 if (rscreen->family <= CHIP_ARUBA) {
774 triple = "r600--";
775 } else {
776 triple = "amdgcn--";
777 }
778 switch(rscreen->family) {
779 /* Clang < 3.6 is missing Hainan in its list of
780 * GPUs, so we need to use the name of a similar GPU.
781 */
782 default:
783 gpu = r600_get_llvm_processor_name(rscreen->family);
784 break;
785 }
786 if (ret) {
787 sprintf(ret, "%s-%s", gpu, triple);
788 }
789 /* +2 for dash and terminating NIL byte */
790 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
791 }
792 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
793 if (ret) {
794 uint64_t *grid_dimension = ret;
795 grid_dimension[0] = 3;
796 }
797 return 1 * sizeof(uint64_t);
798
799 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
800 if (ret) {
801 uint64_t *grid_size = ret;
802 grid_size[0] = 65535;
803 grid_size[1] = 65535;
804 grid_size[2] = 65535;
805 }
806 return 3 * sizeof(uint64_t) ;
807
808 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
809 if (ret) {
810 uint64_t *block_size = ret;
811 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
812 ir_type == PIPE_SHADER_IR_TGSI) {
813 block_size[0] = 2048;
814 block_size[1] = 2048;
815 block_size[2] = 2048;
816 } else {
817 block_size[0] = 256;
818 block_size[1] = 256;
819 block_size[2] = 256;
820 }
821 }
822 return 3 * sizeof(uint64_t);
823
824 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
825 if (ret) {
826 uint64_t *max_threads_per_block = ret;
827 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
828 ir_type == PIPE_SHADER_IR_TGSI)
829 *max_threads_per_block = 2048;
830 else
831 *max_threads_per_block = 256;
832 }
833 return sizeof(uint64_t);
834
835 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
836 if (ret) {
837 uint64_t *max_global_size = ret;
838 uint64_t max_mem_alloc_size;
839
840 r600_get_compute_param(screen, ir_type,
841 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
842 &max_mem_alloc_size);
843
844 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
845 * 1/4 of the MAX_GLOBAL_SIZE. Since the
846 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
847 * make sure we never report more than
848 * 4 * MAX_MEM_ALLOC_SIZE.
849 */
850 *max_global_size = MIN2(4 * max_mem_alloc_size,
851 rscreen->info.gart_size +
852 rscreen->info.vram_size);
853 }
854 return sizeof(uint64_t);
855
856 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
857 if (ret) {
858 uint64_t *max_local_size = ret;
859 /* Value reported by the closed source driver. */
860 *max_local_size = 32768;
861 }
862 return sizeof(uint64_t);
863
864 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
865 if (ret) {
866 uint64_t *max_input_size = ret;
867 /* Value reported by the closed source driver. */
868 *max_input_size = 1024;
869 }
870 return sizeof(uint64_t);
871
872 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
873 if (ret) {
874 uint64_t *max_mem_alloc_size = ret;
875
876 /* XXX: The limit in older kernels is 256 MB. We
877 * should add a query here for newer kernels.
878 */
879 *max_mem_alloc_size = 256 * 1024 * 1024;
880 }
881 return sizeof(uint64_t);
882
883 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
884 if (ret) {
885 uint32_t *max_clock_frequency = ret;
886 *max_clock_frequency = rscreen->info.max_shader_clock;
887 }
888 return sizeof(uint32_t);
889
890 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
891 if (ret) {
892 uint32_t *max_compute_units = ret;
893 *max_compute_units = rscreen->info.num_good_compute_units;
894 }
895 return sizeof(uint32_t);
896
897 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
898 if (ret) {
899 uint32_t *images_supported = ret;
900 *images_supported = 0;
901 }
902 return sizeof(uint32_t);
903 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
904 break; /* unused */
905 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
906 if (ret) {
907 uint32_t *subgroup_size = ret;
908 *subgroup_size = r600_wavefront_size(rscreen->family);
909 }
910 return sizeof(uint32_t);
911 }
912
913 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
914 return 0;
915 }
916
917 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
918 {
919 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
920
921 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
922 rscreen->info.clock_crystal_freq;
923 }
924
925 static void r600_fence_reference(struct pipe_screen *screen,
926 struct pipe_fence_handle **dst,
927 struct pipe_fence_handle *src)
928 {
929 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
930 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
931 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
932
933 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
934 ws->fence_reference(&(*rdst)->gfx, NULL);
935 ws->fence_reference(&(*rdst)->sdma, NULL);
936 FREE(*rdst);
937 }
938 *rdst = rsrc;
939 }
940
941 static boolean r600_fence_finish(struct pipe_screen *screen,
942 struct pipe_fence_handle *fence,
943 uint64_t timeout)
944 {
945 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
946 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
947 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
948
949 if (rfence->sdma) {
950 if (!rws->fence_wait(rws, rfence->sdma, timeout))
951 return false;
952
953 /* Recompute the timeout after waiting. */
954 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
955 int64_t time = os_time_get_nano();
956 timeout = abs_timeout > time ? abs_timeout - time : 0;
957 }
958 }
959
960 if (!rfence->gfx)
961 return true;
962
963 return rws->fence_wait(rws, rfence->gfx, timeout);
964 }
965
966 static void r600_query_memory_info(struct pipe_screen *screen,
967 struct pipe_memory_info *info)
968 {
969 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
970 struct radeon_winsys *ws = rscreen->ws;
971 unsigned vram_usage, gtt_usage;
972
973 info->total_device_memory = rscreen->info.vram_size / 1024;
974 info->total_staging_memory = rscreen->info.gart_size / 1024;
975
976 /* The real TTM memory usage is somewhat random, because:
977 *
978 * 1) TTM delays freeing memory, because it can only free it after
979 * fences expire.
980 *
981 * 2) The memory usage can be really low if big VRAM evictions are
982 * taking place, but the real usage is well above the size of VRAM.
983 *
984 * Instead, return statistics of this process.
985 */
986 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
987 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
988
989 info->avail_device_memory =
990 vram_usage <= info->total_device_memory ?
991 info->total_device_memory - vram_usage : 0;
992 info->avail_staging_memory =
993 gtt_usage <= info->total_staging_memory ?
994 info->total_staging_memory - gtt_usage : 0;
995
996 info->device_memory_evicted =
997 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
998 /* Just return the number of evicted 64KB pages. */
999 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1000 }
1001
1002 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1003 const struct pipe_resource *templ)
1004 {
1005 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1006
1007 if (templ->target == PIPE_BUFFER) {
1008 return r600_buffer_create(screen, templ,
1009 rscreen->info.gart_page_size);
1010 } else {
1011 return r600_texture_create(screen, templ);
1012 }
1013 }
1014
1015 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1016 struct radeon_winsys *ws)
1017 {
1018 char llvm_string[32] = {}, kernel_version[128] = {};
1019 struct utsname uname_data;
1020
1021 ws->query_info(ws, &rscreen->info);
1022
1023 if (uname(&uname_data) == 0)
1024 snprintf(kernel_version, sizeof(kernel_version),
1025 " / %s", uname_data.release);
1026
1027 #if HAVE_LLVM
1028 snprintf(llvm_string, sizeof(llvm_string),
1029 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1030 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1031 #endif
1032
1033 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1034 "%s (DRM %i.%i.%i%s%s)",
1035 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1036 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1037 kernel_version, llvm_string);
1038
1039 rscreen->b.get_name = r600_get_name;
1040 rscreen->b.get_vendor = r600_get_vendor;
1041 rscreen->b.get_device_vendor = r600_get_device_vendor;
1042 rscreen->b.get_compute_param = r600_get_compute_param;
1043 rscreen->b.get_paramf = r600_get_paramf;
1044 rscreen->b.get_timestamp = r600_get_timestamp;
1045 rscreen->b.fence_finish = r600_fence_finish;
1046 rscreen->b.fence_reference = r600_fence_reference;
1047 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1048 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1049 rscreen->b.query_memory_info = r600_query_memory_info;
1050
1051 if (rscreen->info.has_uvd) {
1052 rscreen->b.get_video_param = rvid_get_video_param;
1053 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1054 } else {
1055 rscreen->b.get_video_param = r600_get_video_param;
1056 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1057 }
1058
1059 r600_init_screen_texture_functions(rscreen);
1060 r600_init_screen_query_functions(rscreen);
1061
1062 rscreen->ws = ws;
1063 rscreen->family = rscreen->info.family;
1064 rscreen->chip_class = rscreen->info.chip_class;
1065 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1066
1067 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1068 if (rscreen->force_aniso >= 0) {
1069 printf("radeon: Forcing anisotropy filter to %ix\n",
1070 /* round down to a power of two */
1071 1 << util_logbase2(rscreen->force_aniso));
1072 }
1073
1074 util_format_s3tc_init();
1075 pipe_mutex_init(rscreen->aux_context_lock);
1076 pipe_mutex_init(rscreen->gpu_load_mutex);
1077
1078 if (rscreen->debug_flags & DBG_INFO) {
1079 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1080 printf("family = %i (%s)\n", rscreen->info.family,
1081 r600_get_chip_name(rscreen));
1082 printf("chip_class = %i\n", rscreen->info.chip_class);
1083 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1084 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1085 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1086 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1087 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1088 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1089 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1090 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1091 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1092 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1093 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1094 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1095
1096 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1097 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1098 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1099 printf("max_se = %i\n", rscreen->info.max_se);
1100 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1101
1102 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1103 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1104 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1105 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1106 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1107 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1108 }
1109 return true;
1110 }
1111
1112 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1113 {
1114 r600_perfcounters_destroy(rscreen);
1115 r600_gpu_load_kill_thread(rscreen);
1116
1117 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1118 pipe_mutex_destroy(rscreen->aux_context_lock);
1119 rscreen->aux_context->destroy(rscreen->aux_context);
1120
1121 rscreen->ws->destroy(rscreen->ws);
1122 FREE(rscreen);
1123 }
1124
1125 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1126 unsigned processor)
1127 {
1128 switch (processor) {
1129 case PIPE_SHADER_VERTEX:
1130 return (rscreen->debug_flags & DBG_VS) != 0;
1131 case PIPE_SHADER_TESS_CTRL:
1132 return (rscreen->debug_flags & DBG_TCS) != 0;
1133 case PIPE_SHADER_TESS_EVAL:
1134 return (rscreen->debug_flags & DBG_TES) != 0;
1135 case PIPE_SHADER_GEOMETRY:
1136 return (rscreen->debug_flags & DBG_GS) != 0;
1137 case PIPE_SHADER_FRAGMENT:
1138 return (rscreen->debug_flags & DBG_PS) != 0;
1139 case PIPE_SHADER_COMPUTE:
1140 return (rscreen->debug_flags & DBG_CS) != 0;
1141 default:
1142 return false;
1143 }
1144 }
1145
1146 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1147 uint64_t offset, uint64_t size, unsigned value,
1148 enum r600_coherency coher)
1149 {
1150 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1151
1152 pipe_mutex_lock(rscreen->aux_context_lock);
1153 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1154 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1155 pipe_mutex_unlock(rscreen->aux_context_lock);
1156 }