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gallium/radeon: use r600_gfx_write_event_eop everywhere
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 /**
84 * Write an EOP event.
85 *
86 * \param event EVENT_TYPE_*
87 * \param event_flags Optional cache flush flags (TC)
88 * \param data_sel 1 = fence, 3 = timestamp
89 * \param buf Buffer
90 * \param va GPU address
91 * \param old_value Previous fence value (for a bug workaround)
92 * \param new_value Fence value to write for this event.
93 */
94 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
95 unsigned event, unsigned event_flags,
96 unsigned data_sel,
97 struct r600_resource *buf, uint64_t va,
98 uint32_t old_fence, uint32_t new_fence)
99 {
100 struct radeon_winsys_cs *cs = ctx->gfx.cs;
101 unsigned op = EVENT_TYPE(event) |
102 EVENT_INDEX(5) |
103 event_flags;
104
105 if (ctx->chip_class == CIK) {
106 /* Two EOP events are required to make all engines go idle
107 * (and optional cache flushes executed) before the timestamp
108 * is written.
109 */
110 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
111 radeon_emit(cs, op);
112 radeon_emit(cs, va);
113 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
114 radeon_emit(cs, old_fence); /* immediate data */
115 radeon_emit(cs, 0); /* unused */
116 }
117
118 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
119 radeon_emit(cs, op);
120 radeon_emit(cs, va);
121 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
122 radeon_emit(cs, new_fence); /* immediate data */
123 radeon_emit(cs, 0); /* unused */
124
125 if (buf)
126 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
127 RADEON_PRIO_QUERY);
128 }
129
130 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
131 {
132 unsigned dwords = 6;
133
134 if (screen->chip_class == CIK)
135 dwords *= 2;
136
137 if (!screen->info.has_virtual_memory)
138 dwords += 2;
139
140 return dwords;
141 }
142
143 void r600_gfx_wait_fence(struct r600_common_context *ctx,
144 uint64_t va, uint32_t ref, uint32_t mask)
145 {
146 struct radeon_winsys_cs *cs = ctx->gfx.cs;
147
148 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
149 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
150 radeon_emit(cs, va);
151 radeon_emit(cs, va >> 32);
152 radeon_emit(cs, ref); /* reference value */
153 radeon_emit(cs, mask); /* mask */
154 radeon_emit(cs, 4); /* poll interval */
155 }
156
157 void r600_draw_rectangle(struct blitter_context *blitter,
158 int x1, int y1, int x2, int y2, float depth,
159 enum blitter_attrib_type type,
160 const union pipe_color_union *attrib)
161 {
162 struct r600_common_context *rctx =
163 (struct r600_common_context*)util_blitter_get_pipe(blitter);
164 struct pipe_viewport_state viewport;
165 struct pipe_resource *buf = NULL;
166 unsigned offset = 0;
167 float *vb;
168
169 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
170 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
171 return;
172 }
173
174 /* Some operations (like color resolve on r6xx) don't work
175 * with the conventional primitive types.
176 * One that works is PT_RECTLIST, which we use here. */
177
178 /* setup viewport */
179 viewport.scale[0] = 1.0f;
180 viewport.scale[1] = 1.0f;
181 viewport.scale[2] = 1.0f;
182 viewport.translate[0] = 0.0f;
183 viewport.translate[1] = 0.0f;
184 viewport.translate[2] = 0.0f;
185 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
186
187 /* Upload vertices. The hw rectangle has only 3 vertices,
188 * I guess the 4th one is derived from the first 3.
189 * The vertex specification should match u_blitter's vertex element state. */
190 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
191 if (!buf)
192 return;
193
194 vb[0] = x1;
195 vb[1] = y1;
196 vb[2] = depth;
197 vb[3] = 1;
198
199 vb[8] = x1;
200 vb[9] = y2;
201 vb[10] = depth;
202 vb[11] = 1;
203
204 vb[16] = x2;
205 vb[17] = y1;
206 vb[18] = depth;
207 vb[19] = 1;
208
209 if (attrib) {
210 memcpy(vb+4, attrib->f, sizeof(float)*4);
211 memcpy(vb+12, attrib->f, sizeof(float)*4);
212 memcpy(vb+20, attrib->f, sizeof(float)*4);
213 }
214
215 /* draw */
216 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
217 R600_PRIM_RECTANGLE_LIST, 3, 2);
218 pipe_resource_reference(&buf, NULL);
219 }
220
221 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
222 struct r600_resource *dst, struct r600_resource *src)
223 {
224 uint64_t vram = 0, gtt = 0;
225
226 if (dst) {
227 vram += dst->vram_usage;
228 gtt += dst->gart_usage;
229 }
230 if (src) {
231 vram += src->vram_usage;
232 gtt += src->gart_usage;
233 }
234
235 /* Flush the GFX IB if DMA depends on it. */
236 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
237 ((dst &&
238 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
239 RADEON_USAGE_READWRITE)) ||
240 (src &&
241 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
242 RADEON_USAGE_WRITE))))
243 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
244
245 /* Flush if there's not enough space, or if the memory usage per IB
246 * is too large.
247 */
248 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
249 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
250 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
251 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
252 }
253
254 /* If GPUVM is not supported, the CS checker needs 2 entries
255 * in the buffer list per packet, which has to be done manually.
256 */
257 if (ctx->screen->info.has_virtual_memory) {
258 if (dst)
259 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
260 RADEON_USAGE_WRITE,
261 RADEON_PRIO_SDMA_BUFFER);
262 if (src)
263 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
264 RADEON_USAGE_READ,
265 RADEON_PRIO_SDMA_BUFFER);
266 }
267 }
268
269 /* This is required to prevent read-after-write hazards. */
270 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
271 {
272 struct radeon_winsys_cs *cs = rctx->dma.cs;
273
274 /* done at the end of DMA calls, so increment this. */
275 rctx->num_dma_calls++;
276
277 /* IBs using too little memory are limited by the IB submission overhead.
278 * IBs using too much memory are limited by the kernel/TTM overhead.
279 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
280 *
281 * This heuristic makes sure that DMA requests are executed
282 * very soon after the call is made and lowers memory usage.
283 * It improves texture upload performance by keeping the DMA
284 * engine busy while uploads are being submitted.
285 */
286 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
287 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
288 return;
289 }
290
291 r600_need_dma_space(rctx, 1, NULL, NULL);
292
293 if (!radeon_emitted(cs, 0)) /* empty queue */
294 return;
295
296 /* NOP waits for idle on Evergreen and later. */
297 if (rctx->chip_class >= CIK)
298 radeon_emit(cs, 0x00000000); /* NOP */
299 else if (rctx->chip_class >= EVERGREEN)
300 radeon_emit(cs, 0xf0000000); /* NOP */
301 else {
302 /* TODO: R600-R700 should use the FENCE packet.
303 * CS checker support is required. */
304 }
305 }
306
307 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
308 {
309 }
310
311 void r600_preflush_suspend_features(struct r600_common_context *ctx)
312 {
313 /* suspend queries */
314 if (!LIST_IS_EMPTY(&ctx->active_queries))
315 r600_suspend_queries(ctx);
316
317 ctx->streamout.suspended = false;
318 if (ctx->streamout.begin_emitted) {
319 r600_emit_streamout_end(ctx);
320 ctx->streamout.suspended = true;
321 }
322 }
323
324 void r600_postflush_resume_features(struct r600_common_context *ctx)
325 {
326 if (ctx->streamout.suspended) {
327 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
328 r600_streamout_buffers_dirty(ctx);
329 }
330
331 /* resume queries */
332 if (!LIST_IS_EMPTY(&ctx->active_queries))
333 r600_resume_queries(ctx);
334 }
335
336 static void r600_flush_from_st(struct pipe_context *ctx,
337 struct pipe_fence_handle **fence,
338 unsigned flags)
339 {
340 struct pipe_screen *screen = ctx->screen;
341 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
342 struct radeon_winsys *ws = rctx->ws;
343 unsigned rflags = 0;
344 struct pipe_fence_handle *gfx_fence = NULL;
345 struct pipe_fence_handle *sdma_fence = NULL;
346 bool deferred_fence = false;
347
348 if (flags & PIPE_FLUSH_END_OF_FRAME)
349 rflags |= RADEON_FLUSH_END_OF_FRAME;
350 if (flags & PIPE_FLUSH_DEFERRED)
351 rflags |= RADEON_FLUSH_ASYNC;
352
353 if (rctx->dma.cs) {
354 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
355 }
356
357 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
358 if (fence)
359 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
360 if (!(rflags & RADEON_FLUSH_ASYNC))
361 ws->cs_sync_flush(rctx->gfx.cs);
362 } else {
363 /* Instead of flushing, create a deferred fence. Constraints:
364 * - The state tracker must allow a deferred flush.
365 * - The state tracker must request a fence.
366 * Thread safety in fence_finish must be ensured by the state tracker.
367 */
368 if (flags & PIPE_FLUSH_DEFERRED && fence) {
369 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
370 deferred_fence = true;
371 } else {
372 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
373 }
374 }
375
376 /* Both engines can signal out of order, so we need to keep both fences. */
377 if (fence) {
378 struct r600_multi_fence *multi_fence =
379 CALLOC_STRUCT(r600_multi_fence);
380 if (!multi_fence)
381 return;
382
383 multi_fence->reference.count = 1;
384 /* If both fences are NULL, fence_finish will always return true. */
385 multi_fence->gfx = gfx_fence;
386 multi_fence->sdma = sdma_fence;
387
388 if (deferred_fence) {
389 multi_fence->gfx_unflushed.ctx = rctx;
390 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
391 }
392
393 screen->fence_reference(screen, fence, NULL);
394 *fence = (struct pipe_fence_handle*)multi_fence;
395 }
396 }
397
398 static void r600_flush_dma_ring(void *ctx, unsigned flags,
399 struct pipe_fence_handle **fence)
400 {
401 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
402 struct radeon_winsys_cs *cs = rctx->dma.cs;
403 struct radeon_saved_cs saved;
404 bool check_vm =
405 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
406 rctx->check_vm_faults;
407
408 if (!radeon_emitted(cs, 0)) {
409 if (fence)
410 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
411 return;
412 }
413
414 if (check_vm)
415 radeon_save_cs(rctx->ws, cs, &saved);
416
417 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
418 if (fence)
419 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
420
421 if (check_vm) {
422 /* Use conservative timeout 800ms, after which we won't wait any
423 * longer and assume the GPU is hung.
424 */
425 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
426
427 rctx->check_vm_faults(rctx, &saved, RING_DMA);
428 radeon_clear_saved_cs(&saved);
429 }
430 }
431
432 /**
433 * Store a linearized copy of all chunks of \p cs together with the buffer
434 * list in \p saved.
435 */
436 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
437 struct radeon_saved_cs *saved)
438 {
439 void *buf;
440 unsigned i;
441
442 /* Save the IB chunks. */
443 saved->num_dw = cs->prev_dw + cs->current.cdw;
444 saved->ib = MALLOC(4 * saved->num_dw);
445 if (!saved->ib)
446 goto oom;
447
448 buf = saved->ib;
449 for (i = 0; i < cs->num_prev; ++i) {
450 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
451 buf += cs->prev[i].cdw;
452 }
453 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
454
455 /* Save the buffer list. */
456 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
457 saved->bo_list = CALLOC(saved->bo_count,
458 sizeof(saved->bo_list[0]));
459 if (!saved->bo_list) {
460 FREE(saved->ib);
461 goto oom;
462 }
463 ws->cs_get_buffer_list(cs, saved->bo_list);
464
465 return;
466
467 oom:
468 fprintf(stderr, "%s: out of memory\n", __func__);
469 memset(saved, 0, sizeof(*saved));
470 }
471
472 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
473 {
474 FREE(saved->ib);
475 FREE(saved->bo_list);
476
477 memset(saved, 0, sizeof(*saved));
478 }
479
480 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
481 {
482 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
483 unsigned latest = rctx->ws->query_value(rctx->ws,
484 RADEON_GPU_RESET_COUNTER);
485
486 if (rctx->gpu_reset_counter == latest)
487 return PIPE_NO_RESET;
488
489 rctx->gpu_reset_counter = latest;
490 return PIPE_UNKNOWN_CONTEXT_RESET;
491 }
492
493 static void r600_set_debug_callback(struct pipe_context *ctx,
494 const struct pipe_debug_callback *cb)
495 {
496 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
497
498 if (cb)
499 rctx->debug = *cb;
500 else
501 memset(&rctx->debug, 0, sizeof(rctx->debug));
502 }
503
504 static void r600_set_device_reset_callback(struct pipe_context *ctx,
505 const struct pipe_device_reset_callback *cb)
506 {
507 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
508
509 if (cb)
510 rctx->device_reset_callback = *cb;
511 else
512 memset(&rctx->device_reset_callback, 0,
513 sizeof(rctx->device_reset_callback));
514 }
515
516 bool r600_check_device_reset(struct r600_common_context *rctx)
517 {
518 enum pipe_reset_status status;
519
520 if (!rctx->device_reset_callback.reset)
521 return false;
522
523 if (!rctx->b.get_device_reset_status)
524 return false;
525
526 status = rctx->b.get_device_reset_status(&rctx->b);
527 if (status == PIPE_NO_RESET)
528 return false;
529
530 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
531 return true;
532 }
533
534 bool r600_common_context_init(struct r600_common_context *rctx,
535 struct r600_common_screen *rscreen,
536 unsigned context_flags)
537 {
538 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
539
540 rctx->screen = rscreen;
541 rctx->ws = rscreen->ws;
542 rctx->family = rscreen->family;
543 rctx->chip_class = rscreen->chip_class;
544
545 if (rscreen->chip_class >= CIK)
546 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
547 else if (rscreen->chip_class >= EVERGREEN)
548 rctx->max_db = 8;
549 else
550 rctx->max_db = 4;
551
552 rctx->b.invalidate_resource = r600_invalidate_resource;
553 rctx->b.transfer_map = u_transfer_map_vtbl;
554 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
555 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
556 rctx->b.texture_subdata = u_default_texture_subdata;
557 rctx->b.memory_barrier = r600_memory_barrier;
558 rctx->b.flush = r600_flush_from_st;
559 rctx->b.set_debug_callback = r600_set_debug_callback;
560
561 /* evergreen_compute.c has a special codepath for global buffers.
562 * Everything else can use the direct path.
563 */
564 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
565 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
566 rctx->b.buffer_subdata = u_default_buffer_subdata;
567 else
568 rctx->b.buffer_subdata = r600_buffer_subdata;
569
570 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
571 rctx->b.get_device_reset_status = r600_get_reset_status;
572 rctx->gpu_reset_counter =
573 rctx->ws->query_value(rctx->ws,
574 RADEON_GPU_RESET_COUNTER);
575 }
576
577 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
578
579 r600_init_context_texture_functions(rctx);
580 r600_init_viewport_functions(rctx);
581 r600_streamout_init(rctx);
582 r600_query_init(rctx);
583 cayman_init_msaa(&rctx->b);
584
585 rctx->allocator_zeroed_memory =
586 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
587 0, PIPE_USAGE_DEFAULT, true);
588 if (!rctx->allocator_zeroed_memory)
589 return false;
590
591 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
592 PIPE_BIND_INDEX_BUFFER |
593 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
594 if (!rctx->uploader)
595 return false;
596
597 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
598 if (!rctx->ctx)
599 return false;
600
601 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
602 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
603 r600_flush_dma_ring,
604 rctx);
605 rctx->dma.flush = r600_flush_dma_ring;
606 }
607
608 return true;
609 }
610
611 void r600_common_context_cleanup(struct r600_common_context *rctx)
612 {
613 unsigned i,j;
614
615 /* Release DCC stats. */
616 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
617 assert(!rctx->dcc_stats[i].query_active);
618
619 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
620 if (rctx->dcc_stats[i].ps_stats[j])
621 rctx->b.destroy_query(&rctx->b,
622 rctx->dcc_stats[i].ps_stats[j]);
623
624 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
625 }
626
627 if (rctx->query_result_shader)
628 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
629
630 if (rctx->gfx.cs)
631 rctx->ws->cs_destroy(rctx->gfx.cs);
632 if (rctx->dma.cs)
633 rctx->ws->cs_destroy(rctx->dma.cs);
634 if (rctx->ctx)
635 rctx->ws->ctx_destroy(rctx->ctx);
636
637 if (rctx->uploader) {
638 u_upload_destroy(rctx->uploader);
639 }
640
641 slab_destroy_child(&rctx->pool_transfers);
642
643 if (rctx->allocator_zeroed_memory) {
644 u_suballocator_destroy(rctx->allocator_zeroed_memory);
645 }
646 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
647 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
648 }
649
650 /*
651 * pipe_screen
652 */
653
654 static const struct debug_named_value common_debug_options[] = {
655 /* logging */
656 { "tex", DBG_TEX, "Print texture info" },
657 { "compute", DBG_COMPUTE, "Print compute info" },
658 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
659 { "info", DBG_INFO, "Print driver information" },
660
661 /* shaders */
662 { "fs", DBG_FS, "Print fetch shaders" },
663 { "vs", DBG_VS, "Print vertex shaders" },
664 { "gs", DBG_GS, "Print geometry shaders" },
665 { "ps", DBG_PS, "Print pixel shaders" },
666 { "cs", DBG_CS, "Print compute shaders" },
667 { "tcs", DBG_TCS, "Print tessellation control shaders" },
668 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
669 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
670 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
671 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
672 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
673 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
674
675 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
676
677 /* features */
678 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
679 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
680 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
681 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
682 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
683 { "notiling", DBG_NO_TILING, "Disable tiling" },
684 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
685 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
686 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
687 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
688 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
689 { "nodcc", DBG_NO_DCC, "Disable DCC." },
690 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
691 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
692 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
693 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
694 { "noce", DBG_NO_CE, "Disable the constant engine"},
695 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
696 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
697
698 DEBUG_NAMED_VALUE_END /* must be last */
699 };
700
701 static const char* r600_get_vendor(struct pipe_screen* pscreen)
702 {
703 return "X.Org";
704 }
705
706 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
707 {
708 return "AMD";
709 }
710
711 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
712 {
713 switch (rscreen->info.family) {
714 case CHIP_R600: return "AMD R600";
715 case CHIP_RV610: return "AMD RV610";
716 case CHIP_RV630: return "AMD RV630";
717 case CHIP_RV670: return "AMD RV670";
718 case CHIP_RV620: return "AMD RV620";
719 case CHIP_RV635: return "AMD RV635";
720 case CHIP_RS780: return "AMD RS780";
721 case CHIP_RS880: return "AMD RS880";
722 case CHIP_RV770: return "AMD RV770";
723 case CHIP_RV730: return "AMD RV730";
724 case CHIP_RV710: return "AMD RV710";
725 case CHIP_RV740: return "AMD RV740";
726 case CHIP_CEDAR: return "AMD CEDAR";
727 case CHIP_REDWOOD: return "AMD REDWOOD";
728 case CHIP_JUNIPER: return "AMD JUNIPER";
729 case CHIP_CYPRESS: return "AMD CYPRESS";
730 case CHIP_HEMLOCK: return "AMD HEMLOCK";
731 case CHIP_PALM: return "AMD PALM";
732 case CHIP_SUMO: return "AMD SUMO";
733 case CHIP_SUMO2: return "AMD SUMO2";
734 case CHIP_BARTS: return "AMD BARTS";
735 case CHIP_TURKS: return "AMD TURKS";
736 case CHIP_CAICOS: return "AMD CAICOS";
737 case CHIP_CAYMAN: return "AMD CAYMAN";
738 case CHIP_ARUBA: return "AMD ARUBA";
739 case CHIP_TAHITI: return "AMD TAHITI";
740 case CHIP_PITCAIRN: return "AMD PITCAIRN";
741 case CHIP_VERDE: return "AMD CAPE VERDE";
742 case CHIP_OLAND: return "AMD OLAND";
743 case CHIP_HAINAN: return "AMD HAINAN";
744 case CHIP_BONAIRE: return "AMD BONAIRE";
745 case CHIP_KAVERI: return "AMD KAVERI";
746 case CHIP_KABINI: return "AMD KABINI";
747 case CHIP_HAWAII: return "AMD HAWAII";
748 case CHIP_MULLINS: return "AMD MULLINS";
749 case CHIP_TONGA: return "AMD TONGA";
750 case CHIP_ICELAND: return "AMD ICELAND";
751 case CHIP_CARRIZO: return "AMD CARRIZO";
752 case CHIP_FIJI: return "AMD FIJI";
753 case CHIP_POLARIS10: return "AMD POLARIS10";
754 case CHIP_POLARIS11: return "AMD POLARIS11";
755 case CHIP_STONEY: return "AMD STONEY";
756 default: return "AMD unknown";
757 }
758 }
759
760 static const char* r600_get_name(struct pipe_screen* pscreen)
761 {
762 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
763
764 return rscreen->renderer_string;
765 }
766
767 static float r600_get_paramf(struct pipe_screen* pscreen,
768 enum pipe_capf param)
769 {
770 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
771
772 switch (param) {
773 case PIPE_CAPF_MAX_LINE_WIDTH:
774 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
775 case PIPE_CAPF_MAX_POINT_WIDTH:
776 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
777 if (rscreen->family >= CHIP_CEDAR)
778 return 16384.0f;
779 else
780 return 8192.0f;
781 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
782 return 16.0f;
783 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
784 return 16.0f;
785 case PIPE_CAPF_GUARD_BAND_LEFT:
786 case PIPE_CAPF_GUARD_BAND_TOP:
787 case PIPE_CAPF_GUARD_BAND_RIGHT:
788 case PIPE_CAPF_GUARD_BAND_BOTTOM:
789 return 0.0f;
790 }
791 return 0.0f;
792 }
793
794 static int r600_get_video_param(struct pipe_screen *screen,
795 enum pipe_video_profile profile,
796 enum pipe_video_entrypoint entrypoint,
797 enum pipe_video_cap param)
798 {
799 switch (param) {
800 case PIPE_VIDEO_CAP_SUPPORTED:
801 return vl_profile_supported(screen, profile, entrypoint);
802 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
803 return 1;
804 case PIPE_VIDEO_CAP_MAX_WIDTH:
805 case PIPE_VIDEO_CAP_MAX_HEIGHT:
806 return vl_video_buffer_max_size(screen);
807 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
808 return PIPE_FORMAT_NV12;
809 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
810 return false;
811 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
812 return false;
813 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
814 return true;
815 case PIPE_VIDEO_CAP_MAX_LEVEL:
816 return vl_level_supported(screen, profile);
817 default:
818 return 0;
819 }
820 }
821
822 const char *r600_get_llvm_processor_name(enum radeon_family family)
823 {
824 switch (family) {
825 case CHIP_R600:
826 case CHIP_RV630:
827 case CHIP_RV635:
828 case CHIP_RV670:
829 return "r600";
830 case CHIP_RV610:
831 case CHIP_RV620:
832 case CHIP_RS780:
833 case CHIP_RS880:
834 return "rs880";
835 case CHIP_RV710:
836 return "rv710";
837 case CHIP_RV730:
838 return "rv730";
839 case CHIP_RV740:
840 case CHIP_RV770:
841 return "rv770";
842 case CHIP_PALM:
843 case CHIP_CEDAR:
844 return "cedar";
845 case CHIP_SUMO:
846 case CHIP_SUMO2:
847 return "sumo";
848 case CHIP_REDWOOD:
849 return "redwood";
850 case CHIP_JUNIPER:
851 return "juniper";
852 case CHIP_HEMLOCK:
853 case CHIP_CYPRESS:
854 return "cypress";
855 case CHIP_BARTS:
856 return "barts";
857 case CHIP_TURKS:
858 return "turks";
859 case CHIP_CAICOS:
860 return "caicos";
861 case CHIP_CAYMAN:
862 case CHIP_ARUBA:
863 return "cayman";
864
865 case CHIP_TAHITI: return "tahiti";
866 case CHIP_PITCAIRN: return "pitcairn";
867 case CHIP_VERDE: return "verde";
868 case CHIP_OLAND: return "oland";
869 case CHIP_HAINAN: return "hainan";
870 case CHIP_BONAIRE: return "bonaire";
871 case CHIP_KABINI: return "kabini";
872 case CHIP_KAVERI: return "kaveri";
873 case CHIP_HAWAII: return "hawaii";
874 case CHIP_MULLINS:
875 return "mullins";
876 case CHIP_TONGA: return "tonga";
877 case CHIP_ICELAND: return "iceland";
878 case CHIP_CARRIZO: return "carrizo";
879 #if HAVE_LLVM <= 0x0307
880 case CHIP_FIJI: return "tonga";
881 case CHIP_STONEY: return "carrizo";
882 #else
883 case CHIP_FIJI: return "fiji";
884 case CHIP_STONEY: return "stoney";
885 #endif
886 #if HAVE_LLVM <= 0x0308
887 case CHIP_POLARIS10: return "tonga";
888 case CHIP_POLARIS11: return "tonga";
889 #else
890 case CHIP_POLARIS10: return "polaris10";
891 case CHIP_POLARIS11: return "polaris11";
892 #endif
893 default: return "";
894 }
895 }
896
897 static int r600_get_compute_param(struct pipe_screen *screen,
898 enum pipe_shader_ir ir_type,
899 enum pipe_compute_cap param,
900 void *ret)
901 {
902 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
903
904 //TODO: select these params by asic
905 switch (param) {
906 case PIPE_COMPUTE_CAP_IR_TARGET: {
907 const char *gpu;
908 const char *triple;
909 if (rscreen->family <= CHIP_ARUBA) {
910 triple = "r600--";
911 } else {
912 if (HAVE_LLVM < 0x0400) {
913 triple = "amdgcn--";
914 } else {
915 triple = "amdgcn-mesa-mesa3d";
916 }
917 }
918 switch(rscreen->family) {
919 /* Clang < 3.6 is missing Hainan in its list of
920 * GPUs, so we need to use the name of a similar GPU.
921 */
922 default:
923 gpu = r600_get_llvm_processor_name(rscreen->family);
924 break;
925 }
926 if (ret) {
927 sprintf(ret, "%s-%s", gpu, triple);
928 }
929 /* +2 for dash and terminating NIL byte */
930 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
931 }
932 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
933 if (ret) {
934 uint64_t *grid_dimension = ret;
935 grid_dimension[0] = 3;
936 }
937 return 1 * sizeof(uint64_t);
938
939 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
940 if (ret) {
941 uint64_t *grid_size = ret;
942 grid_size[0] = 65535;
943 grid_size[1] = 65535;
944 grid_size[2] = 65535;
945 }
946 return 3 * sizeof(uint64_t) ;
947
948 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
949 if (ret) {
950 uint64_t *block_size = ret;
951 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
952 ir_type == PIPE_SHADER_IR_TGSI) {
953 block_size[0] = 2048;
954 block_size[1] = 2048;
955 block_size[2] = 2048;
956 } else {
957 block_size[0] = 256;
958 block_size[1] = 256;
959 block_size[2] = 256;
960 }
961 }
962 return 3 * sizeof(uint64_t);
963
964 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
965 if (ret) {
966 uint64_t *max_threads_per_block = ret;
967 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
968 ir_type == PIPE_SHADER_IR_TGSI)
969 *max_threads_per_block = 2048;
970 else
971 *max_threads_per_block = 256;
972 }
973 return sizeof(uint64_t);
974 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
975 if (ret) {
976 uint32_t *address_bits = ret;
977 address_bits[0] = 32;
978 if (rscreen->chip_class >= SI)
979 address_bits[0] = 64;
980 }
981 return 1 * sizeof(uint32_t);
982
983 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
984 if (ret) {
985 uint64_t *max_global_size = ret;
986 uint64_t max_mem_alloc_size;
987
988 r600_get_compute_param(screen, ir_type,
989 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
990 &max_mem_alloc_size);
991
992 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
993 * 1/4 of the MAX_GLOBAL_SIZE. Since the
994 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
995 * make sure we never report more than
996 * 4 * MAX_MEM_ALLOC_SIZE.
997 */
998 *max_global_size = MIN2(4 * max_mem_alloc_size,
999 MAX2(rscreen->info.gart_size,
1000 rscreen->info.vram_size));
1001 }
1002 return sizeof(uint64_t);
1003
1004 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1005 if (ret) {
1006 uint64_t *max_local_size = ret;
1007 /* Value reported by the closed source driver. */
1008 *max_local_size = 32768;
1009 }
1010 return sizeof(uint64_t);
1011
1012 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1013 if (ret) {
1014 uint64_t *max_input_size = ret;
1015 /* Value reported by the closed source driver. */
1016 *max_input_size = 1024;
1017 }
1018 return sizeof(uint64_t);
1019
1020 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1021 if (ret) {
1022 uint64_t *max_mem_alloc_size = ret;
1023
1024 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1025 }
1026 return sizeof(uint64_t);
1027
1028 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1029 if (ret) {
1030 uint32_t *max_clock_frequency = ret;
1031 *max_clock_frequency = rscreen->info.max_shader_clock;
1032 }
1033 return sizeof(uint32_t);
1034
1035 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1036 if (ret) {
1037 uint32_t *max_compute_units = ret;
1038 *max_compute_units = rscreen->info.num_good_compute_units;
1039 }
1040 return sizeof(uint32_t);
1041
1042 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1043 if (ret) {
1044 uint32_t *images_supported = ret;
1045 *images_supported = 0;
1046 }
1047 return sizeof(uint32_t);
1048 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1049 break; /* unused */
1050 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1051 if (ret) {
1052 uint32_t *subgroup_size = ret;
1053 *subgroup_size = r600_wavefront_size(rscreen->family);
1054 }
1055 return sizeof(uint32_t);
1056 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1057 if (ret) {
1058 uint64_t *max_variable_threads_per_block = ret;
1059 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1060 ir_type == PIPE_SHADER_IR_TGSI)
1061 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1062 else
1063 *max_variable_threads_per_block = 0;
1064 }
1065 return sizeof(uint64_t);
1066 }
1067
1068 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1069 return 0;
1070 }
1071
1072 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1073 {
1074 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1075
1076 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1077 rscreen->info.clock_crystal_freq;
1078 }
1079
1080 static void r600_fence_reference(struct pipe_screen *screen,
1081 struct pipe_fence_handle **dst,
1082 struct pipe_fence_handle *src)
1083 {
1084 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1085 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1086 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1087
1088 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1089 ws->fence_reference(&(*rdst)->gfx, NULL);
1090 ws->fence_reference(&(*rdst)->sdma, NULL);
1091 FREE(*rdst);
1092 }
1093 *rdst = rsrc;
1094 }
1095
1096 static boolean r600_fence_finish(struct pipe_screen *screen,
1097 struct pipe_context *ctx,
1098 struct pipe_fence_handle *fence,
1099 uint64_t timeout)
1100 {
1101 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1102 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1103 struct r600_common_context *rctx =
1104 ctx ? (struct r600_common_context*)ctx : NULL;
1105 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1106
1107 if (rfence->sdma) {
1108 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1109 return false;
1110
1111 /* Recompute the timeout after waiting. */
1112 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1113 int64_t time = os_time_get_nano();
1114 timeout = abs_timeout > time ? abs_timeout - time : 0;
1115 }
1116 }
1117
1118 if (!rfence->gfx)
1119 return true;
1120
1121 /* Flush the gfx IB if it hasn't been flushed yet. */
1122 if (rctx &&
1123 rfence->gfx_unflushed.ctx == rctx &&
1124 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1125 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1126 rfence->gfx_unflushed.ctx = NULL;
1127
1128 if (!timeout)
1129 return false;
1130
1131 /* Recompute the timeout after all that. */
1132 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1133 int64_t time = os_time_get_nano();
1134 timeout = abs_timeout > time ? abs_timeout - time : 0;
1135 }
1136 }
1137
1138 return rws->fence_wait(rws, rfence->gfx, timeout);
1139 }
1140
1141 static void r600_query_memory_info(struct pipe_screen *screen,
1142 struct pipe_memory_info *info)
1143 {
1144 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1145 struct radeon_winsys *ws = rscreen->ws;
1146 unsigned vram_usage, gtt_usage;
1147
1148 info->total_device_memory = rscreen->info.vram_size / 1024;
1149 info->total_staging_memory = rscreen->info.gart_size / 1024;
1150
1151 /* The real TTM memory usage is somewhat random, because:
1152 *
1153 * 1) TTM delays freeing memory, because it can only free it after
1154 * fences expire.
1155 *
1156 * 2) The memory usage can be really low if big VRAM evictions are
1157 * taking place, but the real usage is well above the size of VRAM.
1158 *
1159 * Instead, return statistics of this process.
1160 */
1161 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1162 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1163
1164 info->avail_device_memory =
1165 vram_usage <= info->total_device_memory ?
1166 info->total_device_memory - vram_usage : 0;
1167 info->avail_staging_memory =
1168 gtt_usage <= info->total_staging_memory ?
1169 info->total_staging_memory - gtt_usage : 0;
1170
1171 info->device_memory_evicted =
1172 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1173
1174 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1175 info->nr_device_memory_evictions =
1176 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1177 else
1178 /* Just return the number of evicted 64KB pages. */
1179 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1180 }
1181
1182 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1183 const struct pipe_resource *templ)
1184 {
1185 if (templ->target == PIPE_BUFFER) {
1186 return r600_buffer_create(screen, templ, 256);
1187 } else {
1188 return r600_texture_create(screen, templ);
1189 }
1190 }
1191
1192 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1193 struct radeon_winsys *ws)
1194 {
1195 char llvm_string[32] = {}, kernel_version[128] = {};
1196 struct utsname uname_data;
1197
1198 ws->query_info(ws, &rscreen->info);
1199
1200 if (uname(&uname_data) == 0)
1201 snprintf(kernel_version, sizeof(kernel_version),
1202 " / %s", uname_data.release);
1203
1204 #if HAVE_LLVM
1205 snprintf(llvm_string, sizeof(llvm_string),
1206 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1207 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1208 #endif
1209
1210 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1211 "%s (DRM %i.%i.%i%s%s)",
1212 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1213 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1214 kernel_version, llvm_string);
1215
1216 rscreen->b.get_name = r600_get_name;
1217 rscreen->b.get_vendor = r600_get_vendor;
1218 rscreen->b.get_device_vendor = r600_get_device_vendor;
1219 rscreen->b.get_compute_param = r600_get_compute_param;
1220 rscreen->b.get_paramf = r600_get_paramf;
1221 rscreen->b.get_timestamp = r600_get_timestamp;
1222 rscreen->b.fence_finish = r600_fence_finish;
1223 rscreen->b.fence_reference = r600_fence_reference;
1224 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1225 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1226 rscreen->b.query_memory_info = r600_query_memory_info;
1227
1228 if (rscreen->info.has_uvd) {
1229 rscreen->b.get_video_param = rvid_get_video_param;
1230 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1231 } else {
1232 rscreen->b.get_video_param = r600_get_video_param;
1233 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1234 }
1235
1236 r600_init_screen_texture_functions(rscreen);
1237 r600_init_screen_query_functions(rscreen);
1238
1239 rscreen->ws = ws;
1240 rscreen->family = rscreen->info.family;
1241 rscreen->chip_class = rscreen->info.chip_class;
1242 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1243
1244 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1245
1246 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1247 if (rscreen->force_aniso >= 0) {
1248 printf("radeon: Forcing anisotropy filter to %ix\n",
1249 /* round down to a power of two */
1250 1 << util_logbase2(rscreen->force_aniso));
1251 }
1252
1253 util_format_s3tc_init();
1254 pipe_mutex_init(rscreen->aux_context_lock);
1255 pipe_mutex_init(rscreen->gpu_load_mutex);
1256
1257 if (rscreen->debug_flags & DBG_INFO) {
1258 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1259 printf("family = %i (%s)\n", rscreen->info.family,
1260 r600_get_chip_name(rscreen));
1261 printf("chip_class = %i\n", rscreen->info.chip_class);
1262 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1263 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1264 printf("max_alloc_size = %i MB\n",
1265 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1266 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1267 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1268 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1269 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1270 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1271 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1272 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1273 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1274 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1275 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1276 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1277 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1278 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1279
1280 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1281 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1282 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1283 printf("max_se = %i\n", rscreen->info.max_se);
1284 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1285
1286 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1287 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1288 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1289 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1290 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1291 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1292 }
1293 return true;
1294 }
1295
1296 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1297 {
1298 r600_perfcounters_destroy(rscreen);
1299 r600_gpu_load_kill_thread(rscreen);
1300
1301 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1302 pipe_mutex_destroy(rscreen->aux_context_lock);
1303 rscreen->aux_context->destroy(rscreen->aux_context);
1304
1305 slab_destroy_parent(&rscreen->pool_transfers);
1306
1307 rscreen->ws->destroy(rscreen->ws);
1308 FREE(rscreen);
1309 }
1310
1311 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1312 unsigned processor)
1313 {
1314 switch (processor) {
1315 case PIPE_SHADER_VERTEX:
1316 return (rscreen->debug_flags & DBG_VS) != 0;
1317 case PIPE_SHADER_TESS_CTRL:
1318 return (rscreen->debug_flags & DBG_TCS) != 0;
1319 case PIPE_SHADER_TESS_EVAL:
1320 return (rscreen->debug_flags & DBG_TES) != 0;
1321 case PIPE_SHADER_GEOMETRY:
1322 return (rscreen->debug_flags & DBG_GS) != 0;
1323 case PIPE_SHADER_FRAGMENT:
1324 return (rscreen->debug_flags & DBG_PS) != 0;
1325 case PIPE_SHADER_COMPUTE:
1326 return (rscreen->debug_flags & DBG_CS) != 0;
1327 default:
1328 return false;
1329 }
1330 }
1331
1332 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1333 {
1334 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1335 r600_can_dump_shader(rscreen, processor);
1336 }
1337
1338 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1339 uint64_t offset, uint64_t size, unsigned value,
1340 enum r600_coherency coher)
1341 {
1342 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1343
1344 pipe_mutex_lock(rscreen->aux_context_lock);
1345 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1346 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1347 pipe_mutex_unlock(rscreen->aux_context_lock);
1348 }