projects / mesa.git / blob
? search:


59fcb63fb7aea7514ea6ee6a482ddd558e22ad8e
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112 unsigned sel = EOP_DATA_SEL(data_sel);
113
114 /* Wait for write confirmation before writing data, but don't send
115 * an interrupt. */
116 if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
117 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
118
119 if (ctx->chip_class >= GFX9) {
120 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
121 * counters) must immediately precede every timestamp event to
122 * prevent a GPU hang on GFX9.
123 *
124 * Occlusion queries don't need to do it here, because they
125 * always do ZPASS_DONE before the timestamp.
126 */
127 if (ctx->chip_class == GFX9 &&
128 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
129 query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
130 query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
131 struct r600_resource *scratch = ctx->eop_bug_scratch;
132
133 assert(16 * ctx->screen->info.num_render_backends <=
134 scratch->b.b.width0);
135 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
136 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
137 radeon_emit(cs, scratch->gpu_address);
138 radeon_emit(cs, scratch->gpu_address >> 32);
139
140 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
141 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
142 }
143
144 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
145 radeon_emit(cs, op);
146 radeon_emit(cs, sel);
147 radeon_emit(cs, va); /* address lo */
148 radeon_emit(cs, va >> 32); /* address hi */
149 radeon_emit(cs, new_fence); /* immediate data lo */
150 radeon_emit(cs, 0); /* immediate data hi */
151 radeon_emit(cs, 0); /* unused */
152 } else {
153 if (ctx->chip_class == CIK ||
154 ctx->chip_class == VI) {
155 struct r600_resource *scratch = ctx->eop_bug_scratch;
156 uint64_t va = scratch->gpu_address;
157
158 /* Two EOP events are required to make all engines go idle
159 * (and optional cache flushes executed) before the timestamp
160 * is written.
161 */
162 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
163 radeon_emit(cs, op);
164 radeon_emit(cs, va);
165 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
166 radeon_emit(cs, 0); /* immediate data */
167 radeon_emit(cs, 0); /* unused */
168
169 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
170 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
171 }
172
173 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
174 radeon_emit(cs, op);
175 radeon_emit(cs, va);
176 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
177 radeon_emit(cs, new_fence); /* immediate data */
178 radeon_emit(cs, 0); /* unused */
179 }
180
181 if (buf)
182 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
183 RADEON_PRIO_QUERY);
184 }
185
186 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
187 {
188 unsigned dwords = 6;
189
190 if (screen->chip_class == CIK ||
191 screen->chip_class == VI)
192 dwords *= 2;
193
194 if (!screen->info.has_virtual_memory)
195 dwords += 2;
196
197 return dwords;
198 }
199
200 void r600_gfx_wait_fence(struct r600_common_context *ctx,
201 uint64_t va, uint32_t ref, uint32_t mask)
202 {
203 struct radeon_winsys_cs *cs = ctx->gfx.cs;
204
205 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
206 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
207 radeon_emit(cs, va);
208 radeon_emit(cs, va >> 32);
209 radeon_emit(cs, ref); /* reference value */
210 radeon_emit(cs, mask); /* mask */
211 radeon_emit(cs, 4); /* poll interval */
212 }
213
214 void r600_draw_rectangle(struct blitter_context *blitter,
215 int x1, int y1, int x2, int y2,
216 float depth, unsigned num_instances,
217 enum blitter_attrib_type type,
218 const union blitter_attrib *attrib)
219 {
220 struct r600_common_context *rctx =
221 (struct r600_common_context*)util_blitter_get_pipe(blitter);
222 struct pipe_viewport_state viewport;
223 struct pipe_resource *buf = NULL;
224 unsigned offset = 0;
225 float *vb;
226
227 /* Some operations (like color resolve on r6xx) don't work
228 * with the conventional primitive types.
229 * One that works is PT_RECTLIST, which we use here. */
230
231 /* setup viewport */
232 viewport.scale[0] = 1.0f;
233 viewport.scale[1] = 1.0f;
234 viewport.scale[2] = 1.0f;
235 viewport.translate[0] = 0.0f;
236 viewport.translate[1] = 0.0f;
237 viewport.translate[2] = 0.0f;
238 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
239
240 /* Upload vertices. The hw rectangle has only 3 vertices,
241 * The 4th one is derived from the first 3.
242 * The vertex specification should match u_blitter's vertex element state. */
243 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
244 rctx->screen->info.tcc_cache_line_size,
245 &offset, &buf, (void**)&vb);
246 if (!buf)
247 return;
248
249 vb[0] = x1;
250 vb[1] = y1;
251 vb[2] = depth;
252 vb[3] = 1;
253
254 vb[8] = x1;
255 vb[9] = y2;
256 vb[10] = depth;
257 vb[11] = 1;
258
259 vb[16] = x2;
260 vb[17] = y1;
261 vb[18] = depth;
262 vb[19] = 1;
263
264 switch (type) {
265 case UTIL_BLITTER_ATTRIB_COLOR:
266 memcpy(vb+4, attrib->color, sizeof(float)*4);
267 memcpy(vb+12, attrib->color, sizeof(float)*4);
268 memcpy(vb+20, attrib->color, sizeof(float)*4);
269 break;
270 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
271 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
272 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
273 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
274 /* fall through */
275 vb[4] = attrib->texcoord.x1;
276 vb[5] = attrib->texcoord.y1;
277 vb[12] = attrib->texcoord.x1;
278 vb[13] = attrib->texcoord.y2;
279 vb[20] = attrib->texcoord.x2;
280 vb[21] = attrib->texcoord.y1;
281 break;
282 default:; /* Nothing to do. */
283 }
284
285 /* draw */
286 struct pipe_vertex_buffer vbuffer = {};
287 vbuffer.buffer.resource = buf;
288 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
289 vbuffer.buffer_offset = offset;
290
291 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
292 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
293 0, num_instances);
294 pipe_resource_reference(&buf, NULL);
295 }
296
297 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
298 {
299 struct radeon_winsys_cs *cs = rctx->dma.cs;
300
301 /* NOP waits for idle on Evergreen and later. */
302 if (rctx->chip_class >= CIK)
303 radeon_emit(cs, 0x00000000); /* NOP */
304 else if (rctx->chip_class >= EVERGREEN)
305 radeon_emit(cs, 0xf0000000); /* NOP */
306 else {
307 /* TODO: R600-R700 should use the FENCE packet.
308 * CS checker support is required. */
309 }
310 }
311
312 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
313 struct r600_resource *dst, struct r600_resource *src)
314 {
315 uint64_t vram = ctx->dma.cs->used_vram;
316 uint64_t gtt = ctx->dma.cs->used_gart;
317
318 if (dst) {
319 vram += dst->vram_usage;
320 gtt += dst->gart_usage;
321 }
322 if (src) {
323 vram += src->vram_usage;
324 gtt += src->gart_usage;
325 }
326
327 /* Flush the GFX IB if DMA depends on it. */
328 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
329 ((dst &&
330 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
331 RADEON_USAGE_READWRITE)) ||
332 (src &&
333 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
334 RADEON_USAGE_WRITE))))
335 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
336
337 /* Flush if there's not enough space, or if the memory usage per IB
338 * is too large.
339 *
340 * IBs using too little memory are limited by the IB submission overhead.
341 * IBs using too much memory are limited by the kernel/TTM overhead.
342 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
343 *
344 * This heuristic makes sure that DMA requests are executed
345 * very soon after the call is made and lowers memory usage.
346 * It improves texture upload performance by keeping the DMA
347 * engine busy while uploads are being submitted.
348 */
349 num_dw++; /* for emit_wait_idle below */
350 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
351 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
352 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
353 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
354 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
355 }
356
357 /* Wait for idle if either buffer has been used in the IB before to
358 * prevent read-after-write hazards.
359 */
360 if ((dst &&
361 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
362 RADEON_USAGE_READWRITE)) ||
363 (src &&
364 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
365 RADEON_USAGE_WRITE)))
366 r600_dma_emit_wait_idle(ctx);
367
368 /* If GPUVM is not supported, the CS checker needs 2 entries
369 * in the buffer list per packet, which has to be done manually.
370 */
371 if (ctx->screen->info.has_virtual_memory) {
372 if (dst)
373 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
374 RADEON_USAGE_WRITE,
375 RADEON_PRIO_SDMA_BUFFER);
376 if (src)
377 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
378 RADEON_USAGE_READ,
379 RADEON_PRIO_SDMA_BUFFER);
380 }
381
382 /* this function is called before all DMA calls, so increment this. */
383 ctx->num_dma_calls++;
384 }
385
386 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
387 {
388 }
389
390 void r600_preflush_suspend_features(struct r600_common_context *ctx)
391 {
392 /* suspend queries */
393 if (!LIST_IS_EMPTY(&ctx->active_queries))
394 r600_suspend_queries(ctx);
395
396 ctx->streamout.suspended = false;
397 if (ctx->streamout.begin_emitted) {
398 r600_emit_streamout_end(ctx);
399 ctx->streamout.suspended = true;
400 }
401 }
402
403 void r600_postflush_resume_features(struct r600_common_context *ctx)
404 {
405 if (ctx->streamout.suspended) {
406 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
407 r600_streamout_buffers_dirty(ctx);
408 }
409
410 /* resume queries */
411 if (!LIST_IS_EMPTY(&ctx->active_queries))
412 r600_resume_queries(ctx);
413 }
414
415 static void r600_add_fence_dependency(struct r600_common_context *rctx,
416 struct pipe_fence_handle *fence)
417 {
418 struct radeon_winsys *ws = rctx->ws;
419
420 if (rctx->dma.cs)
421 ws->cs_add_fence_dependency(rctx->dma.cs, fence);
422 ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
423 }
424
425 static void r600_fence_server_sync(struct pipe_context *ctx,
426 struct pipe_fence_handle *fence)
427 {
428 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
429 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
430
431 /* Only amdgpu needs to handle fence dependencies (for fence imports).
432 * radeon synchronizes all rings by default and will not implement
433 * fence imports.
434 */
435 if (rctx->screen->info.drm_major == 2)
436 return;
437
438 /* Only imported fences need to be handled by fence_server_sync,
439 * because the winsys handles synchronizations automatically for BOs
440 * within the process.
441 *
442 * Simply skip unflushed fences here, and the winsys will drop no-op
443 * dependencies (i.e. dependencies within the same ring).
444 */
445 if (rfence->gfx_unflushed.ctx)
446 return;
447
448 /* All unflushed commands will not start execution before
449 * this fence dependency is signalled.
450 *
451 * Should we flush the context to allow more GPU parallelism?
452 */
453 if (rfence->sdma)
454 r600_add_fence_dependency(rctx, rfence->sdma);
455 if (rfence->gfx)
456 r600_add_fence_dependency(rctx, rfence->gfx);
457 }
458
459 static void r600_flush_from_st(struct pipe_context *ctx,
460 struct pipe_fence_handle **fence,
461 unsigned flags)
462 {
463 struct pipe_screen *screen = ctx->screen;
464 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
465 struct radeon_winsys *ws = rctx->ws;
466 struct pipe_fence_handle *gfx_fence = NULL;
467 struct pipe_fence_handle *sdma_fence = NULL;
468 bool deferred_fence = false;
469 unsigned rflags = RADEON_FLUSH_ASYNC;
470
471 if (flags & PIPE_FLUSH_END_OF_FRAME)
472 rflags |= RADEON_FLUSH_END_OF_FRAME;
473
474 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
475 if (rctx->dma.cs)
476 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
477
478 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
479 if (fence)
480 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
481 if (!(flags & PIPE_FLUSH_DEFERRED))
482 ws->cs_sync_flush(rctx->gfx.cs);
483 } else {
484 /* Instead of flushing, create a deferred fence. Constraints:
485 * - The state tracker must allow a deferred flush.
486 * - The state tracker must request a fence.
487 * Thread safety in fence_finish must be ensured by the state tracker.
488 */
489 if (flags & PIPE_FLUSH_DEFERRED && fence) {
490 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
491 deferred_fence = true;
492 } else {
493 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
494 }
495 }
496
497 /* Both engines can signal out of order, so we need to keep both fences. */
498 if (fence) {
499 struct r600_multi_fence *multi_fence =
500 CALLOC_STRUCT(r600_multi_fence);
501 if (!multi_fence) {
502 ws->fence_reference(&sdma_fence, NULL);
503 ws->fence_reference(&gfx_fence, NULL);
504 goto finish;
505 }
506
507 multi_fence->reference.count = 1;
508 /* If both fences are NULL, fence_finish will always return true. */
509 multi_fence->gfx = gfx_fence;
510 multi_fence->sdma = sdma_fence;
511
512 if (deferred_fence) {
513 multi_fence->gfx_unflushed.ctx = rctx;
514 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
515 }
516
517 screen->fence_reference(screen, fence, NULL);
518 *fence = (struct pipe_fence_handle*)multi_fence;
519 }
520 finish:
521 if (!(flags & PIPE_FLUSH_DEFERRED)) {
522 if (rctx->dma.cs)
523 ws->cs_sync_flush(rctx->dma.cs);
524 ws->cs_sync_flush(rctx->gfx.cs);
525 }
526 }
527
528 static void r600_flush_dma_ring(void *ctx, unsigned flags,
529 struct pipe_fence_handle **fence)
530 {
531 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
532 struct radeon_winsys_cs *cs = rctx->dma.cs;
533 struct radeon_saved_cs saved;
534 bool check_vm =
535 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
536 rctx->check_vm_faults;
537
538 if (!radeon_emitted(cs, 0)) {
539 if (fence)
540 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
541 return;
542 }
543
544 if (check_vm)
545 radeon_save_cs(rctx->ws, cs, &saved, true);
546
547 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
548 if (fence)
549 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
550
551 if (check_vm) {
552 /* Use conservative timeout 800ms, after which we won't wait any
553 * longer and assume the GPU is hung.
554 */
555 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
556
557 rctx->check_vm_faults(rctx, &saved, RING_DMA);
558 radeon_clear_saved_cs(&saved);
559 }
560 }
561
562 /**
563 * Store a linearized copy of all chunks of \p cs together with the buffer
564 * list in \p saved.
565 */
566 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
567 struct radeon_saved_cs *saved, bool get_buffer_list)
568 {
569 uint32_t *buf;
570 unsigned i;
571
572 /* Save the IB chunks. */
573 saved->num_dw = cs->prev_dw + cs->current.cdw;
574 saved->ib = MALLOC(4 * saved->num_dw);
575 if (!saved->ib)
576 goto oom;
577
578 buf = saved->ib;
579 for (i = 0; i < cs->num_prev; ++i) {
580 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
581 buf += cs->prev[i].cdw;
582 }
583 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
584
585 if (!get_buffer_list)
586 return;
587
588 /* Save the buffer list. */
589 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
590 saved->bo_list = CALLOC(saved->bo_count,
591 sizeof(saved->bo_list[0]));
592 if (!saved->bo_list) {
593 FREE(saved->ib);
594 goto oom;
595 }
596 ws->cs_get_buffer_list(cs, saved->bo_list);
597
598 return;
599
600 oom:
601 fprintf(stderr, "%s: out of memory\n", __func__);
602 memset(saved, 0, sizeof(*saved));
603 }
604
605 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
606 {
607 FREE(saved->ib);
608 FREE(saved->bo_list);
609
610 memset(saved, 0, sizeof(*saved));
611 }
612
613 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
614 {
615 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
616 unsigned latest = rctx->ws->query_value(rctx->ws,
617 RADEON_GPU_RESET_COUNTER);
618
619 if (rctx->gpu_reset_counter == latest)
620 return PIPE_NO_RESET;
621
622 rctx->gpu_reset_counter = latest;
623 return PIPE_UNKNOWN_CONTEXT_RESET;
624 }
625
626 static void r600_set_debug_callback(struct pipe_context *ctx,
627 const struct pipe_debug_callback *cb)
628 {
629 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
630
631 if (cb)
632 rctx->debug = *cb;
633 else
634 memset(&rctx->debug, 0, sizeof(rctx->debug));
635 }
636
637 static void r600_set_device_reset_callback(struct pipe_context *ctx,
638 const struct pipe_device_reset_callback *cb)
639 {
640 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
641
642 if (cb)
643 rctx->device_reset_callback = *cb;
644 else
645 memset(&rctx->device_reset_callback, 0,
646 sizeof(rctx->device_reset_callback));
647 }
648
649 bool r600_check_device_reset(struct r600_common_context *rctx)
650 {
651 enum pipe_reset_status status;
652
653 if (!rctx->device_reset_callback.reset)
654 return false;
655
656 if (!rctx->b.get_device_reset_status)
657 return false;
658
659 status = rctx->b.get_device_reset_status(&rctx->b);
660 if (status == PIPE_NO_RESET)
661 return false;
662
663 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
664 return true;
665 }
666
667 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
668 struct pipe_resource *dst,
669 uint64_t offset, uint64_t size,
670 unsigned value)
671 {
672 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
673
674 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
675 }
676
677 static bool r600_resource_commit(struct pipe_context *pctx,
678 struct pipe_resource *resource,
679 unsigned level, struct pipe_box *box,
680 bool commit)
681 {
682 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
683 struct r600_resource *res = r600_resource(resource);
684
685 /*
686 * Since buffer commitment changes cannot be pipelined, we need to
687 * (a) flush any pending commands that refer to the buffer we're about
688 * to change, and
689 * (b) wait for threaded submit to finish, including those that were
690 * triggered by some other, earlier operation.
691 */
692 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
693 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
694 res->buf, RADEON_USAGE_READWRITE)) {
695 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
696 }
697 if (radeon_emitted(ctx->dma.cs, 0) &&
698 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
699 res->buf, RADEON_USAGE_READWRITE)) {
700 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
701 }
702
703 ctx->ws->cs_sync_flush(ctx->dma.cs);
704 ctx->ws->cs_sync_flush(ctx->gfx.cs);
705
706 assert(resource->target == PIPE_BUFFER);
707
708 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
709 }
710
711 bool r600_common_context_init(struct r600_common_context *rctx,
712 struct r600_common_screen *rscreen,
713 unsigned context_flags)
714 {
715 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
716 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
717
718 rctx->screen = rscreen;
719 rctx->ws = rscreen->ws;
720 rctx->family = rscreen->family;
721 rctx->chip_class = rscreen->chip_class;
722
723 rctx->b.invalidate_resource = r600_invalidate_resource;
724 rctx->b.resource_commit = r600_resource_commit;
725 rctx->b.transfer_map = u_transfer_map_vtbl;
726 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
727 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
728 rctx->b.texture_subdata = u_default_texture_subdata;
729 rctx->b.memory_barrier = r600_memory_barrier;
730 rctx->b.flush = r600_flush_from_st;
731 rctx->b.set_debug_callback = r600_set_debug_callback;
732 rctx->b.fence_server_sync = r600_fence_server_sync;
733 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
734
735 /* evergreen_compute.c has a special codepath for global buffers.
736 * Everything else can use the direct path.
737 */
738 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
739 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
740 rctx->b.buffer_subdata = u_default_buffer_subdata;
741 else
742 rctx->b.buffer_subdata = r600_buffer_subdata;
743
744 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
745 rctx->b.get_device_reset_status = r600_get_reset_status;
746 rctx->gpu_reset_counter =
747 rctx->ws->query_value(rctx->ws,
748 RADEON_GPU_RESET_COUNTER);
749 }
750
751 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
752
753 r600_init_context_texture_functions(rctx);
754 r600_init_viewport_functions(rctx);
755 r600_streamout_init(rctx);
756 r600_query_init(rctx);
757 cayman_init_msaa(&rctx->b);
758
759 if (rctx->chip_class == CIK ||
760 rctx->chip_class == VI ||
761 rctx->chip_class == GFX9) {
762 rctx->eop_bug_scratch = (struct r600_resource*)
763 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
764 16 * rscreen->info.num_render_backends);
765 if (!rctx->eop_bug_scratch)
766 return false;
767 }
768
769 rctx->allocator_zeroed_memory =
770 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
771 0, PIPE_USAGE_DEFAULT, 0, true);
772 if (!rctx->allocator_zeroed_memory)
773 return false;
774
775 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
776 0, PIPE_USAGE_STREAM);
777 if (!rctx->b.stream_uploader)
778 return false;
779
780 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
781 0, PIPE_USAGE_DEFAULT);
782 if (!rctx->b.const_uploader)
783 return false;
784
785 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
786 if (!rctx->ctx)
787 return false;
788
789 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
790 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
791 r600_flush_dma_ring,
792 rctx);
793 rctx->dma.flush = r600_flush_dma_ring;
794 }
795
796 return true;
797 }
798
799 void r600_common_context_cleanup(struct r600_common_context *rctx)
800 {
801 unsigned i,j;
802
803 /* Release DCC stats. */
804 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
805 assert(!rctx->dcc_stats[i].query_active);
806
807 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
808 if (rctx->dcc_stats[i].ps_stats[j])
809 rctx->b.destroy_query(&rctx->b,
810 rctx->dcc_stats[i].ps_stats[j]);
811
812 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
813 }
814
815 if (rctx->query_result_shader)
816 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
817
818 if (rctx->gfx.cs)
819 rctx->ws->cs_destroy(rctx->gfx.cs);
820 if (rctx->dma.cs)
821 rctx->ws->cs_destroy(rctx->dma.cs);
822 if (rctx->ctx)
823 rctx->ws->ctx_destroy(rctx->ctx);
824
825 if (rctx->b.stream_uploader)
826 u_upload_destroy(rctx->b.stream_uploader);
827 if (rctx->b.const_uploader)
828 u_upload_destroy(rctx->b.const_uploader);
829
830 slab_destroy_child(&rctx->pool_transfers);
831 slab_destroy_child(&rctx->pool_transfers_unsync);
832
833 if (rctx->allocator_zeroed_memory) {
834 u_suballocator_destroy(rctx->allocator_zeroed_memory);
835 }
836 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
837 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
838 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
839 }
840
841 /*
842 * pipe_screen
843 */
844
845 static const struct debug_named_value common_debug_options[] = {
846 /* logging */
847 { "tex", DBG_TEX, "Print texture info" },
848 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
849 { "compute", DBG_COMPUTE, "Print compute info" },
850 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
851 { "info", DBG_INFO, "Print driver information" },
852
853 /* shaders */
854 { "fs", DBG_FS, "Print fetch shaders" },
855 { "vs", DBG_VS, "Print vertex shaders" },
856 { "gs", DBG_GS, "Print geometry shaders" },
857 { "ps", DBG_PS, "Print pixel shaders" },
858 { "cs", DBG_CS, "Print compute shaders" },
859 { "tcs", DBG_TCS, "Print tessellation control shaders" },
860 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
861 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
862 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
863 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
864 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
865 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
866 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
867
868 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
869 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
870 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
871 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
872
873 /* features */
874 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
875 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
876 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
877 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
878 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
879 { "notiling", DBG_NO_TILING, "Disable tiling" },
880 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
881 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
882 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
883 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
884 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
885 { "nodcc", DBG_NO_DCC, "Disable DCC." },
886 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
887 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
888 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
889 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
890 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
891 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
892 { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
893 { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
894 { "nooutoforder", DBG_NO_OUT_OF_ORDER, "Disable out-of-order rasterization" },
895
896 DEBUG_NAMED_VALUE_END /* must be last */
897 };
898
899 static const char* r600_get_vendor(struct pipe_screen* pscreen)
900 {
901 return "X.Org";
902 }
903
904 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
905 {
906 return "AMD";
907 }
908
909 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
910 {
911 if (!ws->get_chip_name)
912 return NULL;
913 return ws->get_chip_name(ws);
914 }
915
916 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
917 {
918 switch (rscreen->info.family) {
919 case CHIP_R600: return "AMD R600";
920 case CHIP_RV610: return "AMD RV610";
921 case CHIP_RV630: return "AMD RV630";
922 case CHIP_RV670: return "AMD RV670";
923 case CHIP_RV620: return "AMD RV620";
924 case CHIP_RV635: return "AMD RV635";
925 case CHIP_RS780: return "AMD RS780";
926 case CHIP_RS880: return "AMD RS880";
927 case CHIP_RV770: return "AMD RV770";
928 case CHIP_RV730: return "AMD RV730";
929 case CHIP_RV710: return "AMD RV710";
930 case CHIP_RV740: return "AMD RV740";
931 case CHIP_CEDAR: return "AMD CEDAR";
932 case CHIP_REDWOOD: return "AMD REDWOOD";
933 case CHIP_JUNIPER: return "AMD JUNIPER";
934 case CHIP_CYPRESS: return "AMD CYPRESS";
935 case CHIP_HEMLOCK: return "AMD HEMLOCK";
936 case CHIP_PALM: return "AMD PALM";
937 case CHIP_SUMO: return "AMD SUMO";
938 case CHIP_SUMO2: return "AMD SUMO2";
939 case CHIP_BARTS: return "AMD BARTS";
940 case CHIP_TURKS: return "AMD TURKS";
941 case CHIP_CAICOS: return "AMD CAICOS";
942 case CHIP_CAYMAN: return "AMD CAYMAN";
943 case CHIP_ARUBA: return "AMD ARUBA";
944 case CHIP_TAHITI: return "AMD TAHITI";
945 case CHIP_PITCAIRN: return "AMD PITCAIRN";
946 case CHIP_VERDE: return "AMD CAPE VERDE";
947 case CHIP_OLAND: return "AMD OLAND";
948 case CHIP_HAINAN: return "AMD HAINAN";
949 case CHIP_BONAIRE: return "AMD BONAIRE";
950 case CHIP_KAVERI: return "AMD KAVERI";
951 case CHIP_KABINI: return "AMD KABINI";
952 case CHIP_HAWAII: return "AMD HAWAII";
953 case CHIP_MULLINS: return "AMD MULLINS";
954 case CHIP_TONGA: return "AMD TONGA";
955 case CHIP_ICELAND: return "AMD ICELAND";
956 case CHIP_CARRIZO: return "AMD CARRIZO";
957 case CHIP_FIJI: return "AMD FIJI";
958 case CHIP_POLARIS10: return "AMD POLARIS10";
959 case CHIP_POLARIS11: return "AMD POLARIS11";
960 case CHIP_POLARIS12: return "AMD POLARIS12";
961 case CHIP_STONEY: return "AMD STONEY";
962 case CHIP_VEGA10: return "AMD VEGA10";
963 case CHIP_RAVEN: return "AMD RAVEN";
964 default: return "AMD unknown";
965 }
966 }
967
968 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
969 {
970 /* Don't use the cache if shader dumping is enabled. */
971 if (rscreen->debug_flags & DBG_ALL_SHADERS)
972 return;
973
974 uint32_t mesa_timestamp;
975 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
976 &mesa_timestamp)) {
977 char *timestamp_str;
978 int res = -1;
979 if (rscreen->chip_class < SI) {
980 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
981 }
982 #if HAVE_LLVM
983 else {
984 uint32_t llvm_timestamp;
985 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
986 &llvm_timestamp)) {
987 res = asprintf(&timestamp_str, "%u_%u",
988 mesa_timestamp, llvm_timestamp);
989 }
990 }
991 #endif
992 if (res != -1) {
993 /* These flags affect shader compilation. */
994 uint64_t shader_debug_flags =
995 rscreen->debug_flags &
996 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
997 DBG_SI_SCHED |
998 DBG_UNSAFE_MATH);
999
1000 rscreen->disk_shader_cache =
1001 disk_cache_create(r600_get_family_name(rscreen),
1002 timestamp_str,
1003 shader_debug_flags);
1004 free(timestamp_str);
1005 }
1006 }
1007 }
1008
1009 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
1010 {
1011 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
1012 return rscreen->disk_shader_cache;
1013 }
1014
1015 static const char* r600_get_name(struct pipe_screen* pscreen)
1016 {
1017 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
1018
1019 return rscreen->renderer_string;
1020 }
1021
1022 static float r600_get_paramf(struct pipe_screen* pscreen,
1023 enum pipe_capf param)
1024 {
1025 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
1026
1027 switch (param) {
1028 case PIPE_CAPF_MAX_LINE_WIDTH:
1029 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
1030 case PIPE_CAPF_MAX_POINT_WIDTH:
1031 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
1032 if (rscreen->family >= CHIP_CEDAR)
1033 return 16384.0f;
1034 else
1035 return 8192.0f;
1036 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
1037 return 16.0f;
1038 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
1039 return 16.0f;
1040 case PIPE_CAPF_GUARD_BAND_LEFT:
1041 case PIPE_CAPF_GUARD_BAND_TOP:
1042 case PIPE_CAPF_GUARD_BAND_RIGHT:
1043 case PIPE_CAPF_GUARD_BAND_BOTTOM:
1044 return 0.0f;
1045 }
1046 return 0.0f;
1047 }
1048
1049 static int r600_get_video_param(struct pipe_screen *screen,
1050 enum pipe_video_profile profile,
1051 enum pipe_video_entrypoint entrypoint,
1052 enum pipe_video_cap param)
1053 {
1054 switch (param) {
1055 case PIPE_VIDEO_CAP_SUPPORTED:
1056 return vl_profile_supported(screen, profile, entrypoint);
1057 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
1058 return 1;
1059 case PIPE_VIDEO_CAP_MAX_WIDTH:
1060 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1061 return vl_video_buffer_max_size(screen);
1062 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1063 return PIPE_FORMAT_NV12;
1064 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1065 return false;
1066 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1067 return false;
1068 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1069 return true;
1070 case PIPE_VIDEO_CAP_MAX_LEVEL:
1071 return vl_level_supported(screen, profile);
1072 default:
1073 return 0;
1074 }
1075 }
1076
1077 const char *r600_get_llvm_processor_name(enum radeon_family family)
1078 {
1079 switch (family) {
1080 case CHIP_R600:
1081 case CHIP_RV630:
1082 case CHIP_RV635:
1083 case CHIP_RV670:
1084 return "r600";
1085 case CHIP_RV610:
1086 case CHIP_RV620:
1087 case CHIP_RS780:
1088 case CHIP_RS880:
1089 return "rs880";
1090 case CHIP_RV710:
1091 return "rv710";
1092 case CHIP_RV730:
1093 return "rv730";
1094 case CHIP_RV740:
1095 case CHIP_RV770:
1096 return "rv770";
1097 case CHIP_PALM:
1098 case CHIP_CEDAR:
1099 return "cedar";
1100 case CHIP_SUMO:
1101 case CHIP_SUMO2:
1102 return "sumo";
1103 case CHIP_REDWOOD:
1104 return "redwood";
1105 case CHIP_JUNIPER:
1106 return "juniper";
1107 case CHIP_HEMLOCK:
1108 case CHIP_CYPRESS:
1109 return "cypress";
1110 case CHIP_BARTS:
1111 return "barts";
1112 case CHIP_TURKS:
1113 return "turks";
1114 case CHIP_CAICOS:
1115 return "caicos";
1116 case CHIP_CAYMAN:
1117 case CHIP_ARUBA:
1118 return "cayman";
1119
1120 case CHIP_TAHITI: return "tahiti";
1121 case CHIP_PITCAIRN: return "pitcairn";
1122 case CHIP_VERDE: return "verde";
1123 case CHIP_OLAND: return "oland";
1124 case CHIP_HAINAN: return "hainan";
1125 case CHIP_BONAIRE: return "bonaire";
1126 case CHIP_KABINI: return "kabini";
1127 case CHIP_KAVERI: return "kaveri";
1128 case CHIP_HAWAII: return "hawaii";
1129 case CHIP_MULLINS:
1130 return "mullins";
1131 case CHIP_TONGA: return "tonga";
1132 case CHIP_ICELAND: return "iceland";
1133 case CHIP_CARRIZO: return "carrizo";
1134 case CHIP_FIJI:
1135 return "fiji";
1136 case CHIP_STONEY:
1137 return "stoney";
1138 case CHIP_POLARIS10:
1139 return "polaris10";
1140 case CHIP_POLARIS11:
1141 case CHIP_POLARIS12: /* same as polaris11 */
1142 return "polaris11";
1143 case CHIP_VEGA10:
1144 case CHIP_RAVEN:
1145 return "gfx900";
1146 default:
1147 return "";
1148 }
1149 }
1150
1151 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1152 enum pipe_shader_ir ir_type)
1153 {
1154 if (ir_type != PIPE_SHADER_IR_TGSI)
1155 return 256;
1156
1157 /* Only 16 waves per thread-group on gfx9. */
1158 if (screen->chip_class >= GFX9)
1159 return 1024;
1160
1161 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1162 * round number.
1163 */
1164 if (screen->chip_class >= SI)
1165 return 2048;
1166
1167 return 256;
1168 }
1169
1170 static int r600_get_compute_param(struct pipe_screen *screen,
1171 enum pipe_shader_ir ir_type,
1172 enum pipe_compute_cap param,
1173 void *ret)
1174 {
1175 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1176
1177 //TODO: select these params by asic
1178 switch (param) {
1179 case PIPE_COMPUTE_CAP_IR_TARGET: {
1180 const char *gpu;
1181 const char *triple;
1182 if (rscreen->family <= CHIP_ARUBA) {
1183 triple = "r600--";
1184 } else {
1185 if (HAVE_LLVM < 0x0400) {
1186 triple = "amdgcn--";
1187 } else {
1188 triple = "amdgcn-mesa-mesa3d";
1189 }
1190 }
1191 switch(rscreen->family) {
1192 /* Clang < 3.6 is missing Hainan in its list of
1193 * GPUs, so we need to use the name of a similar GPU.
1194 */
1195 default:
1196 gpu = r600_get_llvm_processor_name(rscreen->family);
1197 break;
1198 }
1199 if (ret) {
1200 sprintf(ret, "%s-%s", gpu, triple);
1201 }
1202 /* +2 for dash and terminating NIL byte */
1203 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1204 }
1205 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1206 if (ret) {
1207 uint64_t *grid_dimension = ret;
1208 grid_dimension[0] = 3;
1209 }
1210 return 1 * sizeof(uint64_t);
1211
1212 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1213 if (ret) {
1214 uint64_t *grid_size = ret;
1215 grid_size[0] = 65535;
1216 grid_size[1] = 65535;
1217 grid_size[2] = 65535;
1218 }
1219 return 3 * sizeof(uint64_t) ;
1220
1221 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1222 if (ret) {
1223 uint64_t *block_size = ret;
1224 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1225 block_size[0] = threads_per_block;
1226 block_size[1] = threads_per_block;
1227 block_size[2] = threads_per_block;
1228 }
1229 return 3 * sizeof(uint64_t);
1230
1231 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1232 if (ret) {
1233 uint64_t *max_threads_per_block = ret;
1234 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1235 }
1236 return sizeof(uint64_t);
1237 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1238 if (ret) {
1239 uint32_t *address_bits = ret;
1240 address_bits[0] = 32;
1241 if (rscreen->chip_class >= SI)
1242 address_bits[0] = 64;
1243 }
1244 return 1 * sizeof(uint32_t);
1245
1246 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1247 if (ret) {
1248 uint64_t *max_global_size = ret;
1249 uint64_t max_mem_alloc_size;
1250
1251 r600_get_compute_param(screen, ir_type,
1252 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1253 &max_mem_alloc_size);
1254
1255 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1256 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1257 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1258 * make sure we never report more than
1259 * 4 * MAX_MEM_ALLOC_SIZE.
1260 */
1261 *max_global_size = MIN2(4 * max_mem_alloc_size,
1262 MAX2(rscreen->info.gart_size,
1263 rscreen->info.vram_size));
1264 }
1265 return sizeof(uint64_t);
1266
1267 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1268 if (ret) {
1269 uint64_t *max_local_size = ret;
1270 /* Value reported by the closed source driver. */
1271 *max_local_size = 32768;
1272 }
1273 return sizeof(uint64_t);
1274
1275 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1276 if (ret) {
1277 uint64_t *max_input_size = ret;
1278 /* Value reported by the closed source driver. */
1279 *max_input_size = 1024;
1280 }
1281 return sizeof(uint64_t);
1282
1283 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1284 if (ret) {
1285 uint64_t *max_mem_alloc_size = ret;
1286
1287 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1288 }
1289 return sizeof(uint64_t);
1290
1291 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1292 if (ret) {
1293 uint32_t *max_clock_frequency = ret;
1294 *max_clock_frequency = rscreen->info.max_shader_clock;
1295 }
1296 return sizeof(uint32_t);
1297
1298 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1299 if (ret) {
1300 uint32_t *max_compute_units = ret;
1301 *max_compute_units = rscreen->info.num_good_compute_units;
1302 }
1303 return sizeof(uint32_t);
1304
1305 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1306 if (ret) {
1307 uint32_t *images_supported = ret;
1308 *images_supported = 0;
1309 }
1310 return sizeof(uint32_t);
1311 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1312 break; /* unused */
1313 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1314 if (ret) {
1315 uint32_t *subgroup_size = ret;
1316 *subgroup_size = r600_wavefront_size(rscreen->family);
1317 }
1318 return sizeof(uint32_t);
1319 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1320 if (ret) {
1321 uint64_t *max_variable_threads_per_block = ret;
1322 if (rscreen->chip_class >= SI &&
1323 ir_type == PIPE_SHADER_IR_TGSI)
1324 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1325 else
1326 *max_variable_threads_per_block = 0;
1327 }
1328 return sizeof(uint64_t);
1329 }
1330
1331 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1332 return 0;
1333 }
1334
1335 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1336 {
1337 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1338
1339 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1340 rscreen->info.clock_crystal_freq;
1341 }
1342
1343 static void r600_fence_reference(struct pipe_screen *screen,
1344 struct pipe_fence_handle **dst,
1345 struct pipe_fence_handle *src)
1346 {
1347 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1348 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1349 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1350
1351 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1352 ws->fence_reference(&(*rdst)->gfx, NULL);
1353 ws->fence_reference(&(*rdst)->sdma, NULL);
1354 FREE(*rdst);
1355 }
1356 *rdst = rsrc;
1357 }
1358
1359 static boolean r600_fence_finish(struct pipe_screen *screen,
1360 struct pipe_context *ctx,
1361 struct pipe_fence_handle *fence,
1362 uint64_t timeout)
1363 {
1364 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1365 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1366 struct r600_common_context *rctx;
1367 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1368
1369 ctx = threaded_context_unwrap_sync(ctx);
1370 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1371
1372 if (rfence->sdma) {
1373 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1374 return false;
1375
1376 /* Recompute the timeout after waiting. */
1377 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1378 int64_t time = os_time_get_nano();
1379 timeout = abs_timeout > time ? abs_timeout - time : 0;
1380 }
1381 }
1382
1383 if (!rfence->gfx)
1384 return true;
1385
1386 /* Flush the gfx IB if it hasn't been flushed yet. */
1387 if (rctx &&
1388 rfence->gfx_unflushed.ctx == rctx &&
1389 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1390 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1391 rfence->gfx_unflushed.ctx = NULL;
1392
1393 if (!timeout)
1394 return false;
1395
1396 /* Recompute the timeout after all that. */
1397 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1398 int64_t time = os_time_get_nano();
1399 timeout = abs_timeout > time ? abs_timeout - time : 0;
1400 }
1401 }
1402
1403 return rws->fence_wait(rws, rfence->gfx, timeout);
1404 }
1405
1406 static void r600_query_memory_info(struct pipe_screen *screen,
1407 struct pipe_memory_info *info)
1408 {
1409 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1410 struct radeon_winsys *ws = rscreen->ws;
1411 unsigned vram_usage, gtt_usage;
1412
1413 info->total_device_memory = rscreen->info.vram_size / 1024;
1414 info->total_staging_memory = rscreen->info.gart_size / 1024;
1415
1416 /* The real TTM memory usage is somewhat random, because:
1417 *
1418 * 1) TTM delays freeing memory, because it can only free it after
1419 * fences expire.
1420 *
1421 * 2) The memory usage can be really low if big VRAM evictions are
1422 * taking place, but the real usage is well above the size of VRAM.
1423 *
1424 * Instead, return statistics of this process.
1425 */
1426 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1427 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1428
1429 info->avail_device_memory =
1430 vram_usage <= info->total_device_memory ?
1431 info->total_device_memory - vram_usage : 0;
1432 info->avail_staging_memory =
1433 gtt_usage <= info->total_staging_memory ?
1434 info->total_staging_memory - gtt_usage : 0;
1435
1436 info->device_memory_evicted =
1437 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1438
1439 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1440 info->nr_device_memory_evictions =
1441 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1442 else
1443 /* Just return the number of evicted 64KB pages. */
1444 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1445 }
1446
1447 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1448 const struct pipe_resource *templ)
1449 {
1450 if (templ->target == PIPE_BUFFER) {
1451 return r600_buffer_create(screen, templ, 256);
1452 } else {
1453 return r600_texture_create(screen, templ);
1454 }
1455 }
1456
1457 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1458 struct radeon_winsys *ws)
1459 {
1460 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1461 struct utsname uname_data;
1462 const char *chip_name;
1463
1464 ws->query_info(ws, &rscreen->info);
1465 rscreen->ws = ws;
1466
1467 if ((chip_name = r600_get_marketing_name(ws)))
1468 snprintf(family_name, sizeof(family_name), "%s / ",
1469 r600_get_family_name(rscreen) + 4);
1470 else
1471 chip_name = r600_get_family_name(rscreen);
1472
1473 if (uname(&uname_data) == 0)
1474 snprintf(kernel_version, sizeof(kernel_version),
1475 " / %s", uname_data.release);
1476
1477 if (HAVE_LLVM > 0) {
1478 snprintf(llvm_string, sizeof(llvm_string),
1479 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1480 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1481 }
1482
1483 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1484 "%s (%sDRM %i.%i.%i%s%s)",
1485 chip_name, family_name, rscreen->info.drm_major,
1486 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1487 kernel_version, llvm_string);
1488
1489 rscreen->b.get_name = r600_get_name;
1490 rscreen->b.get_vendor = r600_get_vendor;
1491 rscreen->b.get_device_vendor = r600_get_device_vendor;
1492 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1493 rscreen->b.get_compute_param = r600_get_compute_param;
1494 rscreen->b.get_paramf = r600_get_paramf;
1495 rscreen->b.get_timestamp = r600_get_timestamp;
1496 rscreen->b.fence_finish = r600_fence_finish;
1497 rscreen->b.fence_reference = r600_fence_reference;
1498 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1499 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1500 rscreen->b.query_memory_info = r600_query_memory_info;
1501
1502 if (rscreen->info.has_hw_decode) {
1503 rscreen->b.get_video_param = rvid_get_video_param;
1504 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1505 } else {
1506 rscreen->b.get_video_param = r600_get_video_param;
1507 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1508 }
1509
1510 r600_init_screen_texture_functions(rscreen);
1511 r600_init_screen_query_functions(rscreen);
1512
1513 rscreen->family = rscreen->info.family;
1514 rscreen->chip_class = rscreen->info.chip_class;
1515 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1516 rscreen->has_rbplus = false;
1517 rscreen->rbplus_allowed = false;
1518
1519 r600_disk_cache_create(rscreen);
1520
1521 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1522
1523 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1524 if (rscreen->force_aniso >= 0) {
1525 printf("radeon: Forcing anisotropy filter to %ix\n",
1526 /* round down to a power of two */
1527 1 << util_logbase2(rscreen->force_aniso));
1528 }
1529
1530 util_format_s3tc_init();
1531 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1532 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1533
1534 if (rscreen->debug_flags & DBG_INFO) {
1535 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1536 rscreen->info.pci_domain, rscreen->info.pci_bus,
1537 rscreen->info.pci_dev, rscreen->info.pci_func);
1538 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1539 printf("family = %i (%s)\n", rscreen->info.family,
1540 r600_get_family_name(rscreen));
1541 printf("chip_class = %i\n", rscreen->info.chip_class);
1542 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1543 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1544 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1545 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1546 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1547 printf("max_alloc_size = %i MB\n",
1548 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1549 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1550 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1551 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1552 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1553 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1554 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1555 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1556 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1557 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1558 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1559 printf("me_fw_feature = %i\n", rscreen->info.me_fw_feature);
1560 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1561 printf("pfp_fw_feature = %i\n", rscreen->info.pfp_fw_feature);
1562 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1563 printf("ce_fw_feature = %i\n", rscreen->info.ce_fw_feature);
1564 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1565 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1566 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1567 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1568 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1569 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1570 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1571
1572 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1573 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1574 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1575 printf("max_se = %i\n", rscreen->info.max_se);
1576 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1577
1578 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1579 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1580 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1581 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1582 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1583 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1584 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1585 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1586 }
1587 return true;
1588 }
1589
1590 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1591 {
1592 r600_perfcounters_destroy(rscreen);
1593 r600_gpu_load_kill_thread(rscreen);
1594
1595 mtx_destroy(&rscreen->gpu_load_mutex);
1596 mtx_destroy(&rscreen->aux_context_lock);
1597 rscreen->aux_context->destroy(rscreen->aux_context);
1598
1599 slab_destroy_parent(&rscreen->pool_transfers);
1600
1601 disk_cache_destroy(rscreen->disk_shader_cache);
1602 rscreen->ws->destroy(rscreen->ws);
1603 FREE(rscreen);
1604 }
1605
1606 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1607 unsigned processor)
1608 {
1609 return rscreen->debug_flags & (1 << processor);
1610 }
1611
1612 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1613 {
1614 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1615 r600_can_dump_shader(rscreen, processor);
1616 }
1617
1618 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1619 uint64_t offset, uint64_t size, unsigned value)
1620 {
1621 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1622
1623 mtx_lock(&rscreen->aux_context_lock);
1624 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1625 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1626 mtx_unlock(&rscreen->aux_context_lock);
1627 }