src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 bool r600_common_context_init(struct r600_common_context *rctx,
  43                               struct r600_common_screen *rscreen)
  44 {
  45         util_slab_create(&rctx->pool_transfers,
  46                          sizeof(struct r600_transfer), 64,
  47                          UTIL_SLAB_SINGLETHREADED);
  48
  49         rctx->screen = rscreen;
  50         rctx->ws = rscreen->ws;
  51         rctx->family = rscreen->family;
  52         rctx->chip_class = rscreen->chip_class;
  53         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
  54
  55         rctx->b.transfer_map = u_transfer_map_vtbl;
  56         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
  57         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
  58         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
  59
  60         r600_streamout_init(rctx);
  61         r600_query_init(rctx);
  62
  63         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
  64                                                                0, PIPE_USAGE_DEFAULT, TRUE);
  65         if (!rctx->allocator_so_filled_size)
  66                 return false;
  67
  68         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
  69                                         PIPE_BIND_INDEX_BUFFER |
  70                                         PIPE_BIND_CONSTANT_BUFFER);
  71         if (!rctx->uploader)
  72                 return false;
  73
  74         return true;
  75 }
  76
  77 void r600_common_context_cleanup(struct r600_common_context *rctx)
  78 {
  79         if (rctx->rings.gfx.cs) {
  80                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
  81         }
  82         if (rctx->rings.dma.cs) {
  83                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
  84         }
  85
  86         if (rctx->uploader) {
  87                 u_upload_destroy(rctx->uploader);
  88         }
  89
  90         util_slab_destroy(&rctx->pool_transfers);
  91
  92         if (rctx->allocator_so_filled_size) {
  93                 u_suballocator_destroy(rctx->allocator_so_filled_size);
  94         }
  95 }
  96
  97 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
  98 {
  99         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 100         struct r600_resource *rr = (struct r600_resource *)r;
 101
 102         if (r == NULL) {
 103                 return;
 104         }
 105
 106         /*
 107          * The idea is to compute a gross estimate of memory requirement of
 108          * each draw call. After each draw call, memory will be precisely
 109          * accounted. So the uncertainty is only on the current draw call.
 110          * In practice this gave very good estimate (+/- 10% of the target
 111          * memory limit).
 112          */
 113         if (rr->domains & RADEON_DOMAIN_GTT) {
 114                 rctx->gtt += rr->buf->size;
 115         }
 116         if (rr->domains & RADEON_DOMAIN_VRAM) {
 117                 rctx->vram += rr->buf->size;
 118         }
 119 }
 120
 121 /*
 122  * pipe_screen
 123  */
 124
 125 static const struct debug_named_value common_debug_options[] = {
 126         /* logging */
 127         { "tex", DBG_TEX, "Print texture info" },
 128         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 129         { "compute", DBG_COMPUTE, "Print compute info" },
 130         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 131         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 132
 133         /* shaders */
 134         { "fs", DBG_FS, "Print fetch shaders" },
 135         { "vs", DBG_VS, "Print vertex shaders" },
 136         { "gs", DBG_GS, "Print geometry shaders" },
 137         { "ps", DBG_PS, "Print pixel shaders" },
 138         { "cs", DBG_CS, "Print compute shaders" },
 139
 140         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 141         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 142         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 143
 144         DEBUG_NAMED_VALUE_END /* must be last */
 145 };
 146
 147 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 148 {
 149         return "X.Org";
 150 }
 151
 152 static const char* r600_get_name(struct pipe_screen* pscreen)
 153 {
 154         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 155
 156         switch (rscreen->family) {
 157         case CHIP_R600: return "AMD R600";
 158         case CHIP_RV610: return "AMD RV610";
 159         case CHIP_RV630: return "AMD RV630";
 160         case CHIP_RV670: return "AMD RV670";
 161         case CHIP_RV620: return "AMD RV620";
 162         case CHIP_RV635: return "AMD RV635";
 163         case CHIP_RS780: return "AMD RS780";
 164         case CHIP_RS880: return "AMD RS880";
 165         case CHIP_RV770: return "AMD RV770";
 166         case CHIP_RV730: return "AMD RV730";
 167         case CHIP_RV710: return "AMD RV710";
 168         case CHIP_RV740: return "AMD RV740";
 169         case CHIP_CEDAR: return "AMD CEDAR";
 170         case CHIP_REDWOOD: return "AMD REDWOOD";
 171         case CHIP_JUNIPER: return "AMD JUNIPER";
 172         case CHIP_CYPRESS: return "AMD CYPRESS";
 173         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 174         case CHIP_PALM: return "AMD PALM";
 175         case CHIP_SUMO: return "AMD SUMO";
 176         case CHIP_SUMO2: return "AMD SUMO2";
 177         case CHIP_BARTS: return "AMD BARTS";
 178         case CHIP_TURKS: return "AMD TURKS";
 179         case CHIP_CAICOS: return "AMD CAICOS";
 180         case CHIP_CAYMAN: return "AMD CAYMAN";
 181         case CHIP_ARUBA: return "AMD ARUBA";
 182         case CHIP_TAHITI: return "AMD TAHITI";
 183         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 184         case CHIP_VERDE: return "AMD CAPE VERDE";
 185         case CHIP_OLAND: return "AMD OLAND";
 186         case CHIP_HAINAN: return "AMD HAINAN";
 187         case CHIP_BONAIRE: return "AMD BONAIRE";
 188         case CHIP_KAVERI: return "AMD KAVERI";
 189         case CHIP_KABINI: return "AMD KABINI";
 190         case CHIP_HAWAII: return "AMD HAWAII";
 191         default: return "AMD unknown";
 192         }
 193 }
 194
 195 static float r600_get_paramf(struct pipe_screen* pscreen,
 196                              enum pipe_capf param)
 197 {
 198         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 199
 200         switch (param) {
 201         case PIPE_CAPF_MAX_LINE_WIDTH:
 202         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 203         case PIPE_CAPF_MAX_POINT_WIDTH:
 204         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 205                 if (rscreen->family >= CHIP_CEDAR)
 206                         return 16384.0f;
 207                 else
 208                         return 8192.0f;
 209         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 210                 return 16.0f;
 211         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 212                 return 16.0f;
 213         case PIPE_CAPF_GUARD_BAND_LEFT:
 214         case PIPE_CAPF_GUARD_BAND_TOP:
 215         case PIPE_CAPF_GUARD_BAND_RIGHT:
 216         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 217                 return 0.0f;
 218         }
 219         return 0.0f;
 220 }
 221
 222 static int r600_get_video_param(struct pipe_screen *screen,
 223                                 enum pipe_video_profile profile,
 224                                 enum pipe_video_entrypoint entrypoint,
 225                                 enum pipe_video_cap param)
 226 {
 227         switch (param) {
 228         case PIPE_VIDEO_CAP_SUPPORTED:
 229                 return vl_profile_supported(screen, profile, entrypoint);
 230         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 231                 return 1;
 232         case PIPE_VIDEO_CAP_MAX_WIDTH:
 233         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 234                 return vl_video_buffer_max_size(screen);
 235         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 236                 return PIPE_FORMAT_NV12;
 237         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 238                 return false;
 239         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 240                 return false;
 241         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 242                 return true;
 243         case PIPE_VIDEO_CAP_MAX_LEVEL:
 244                 return vl_level_supported(screen, profile);
 245         default:
 246                 return 0;
 247         }
 248 }
 249
 250 const char *r600_get_llvm_processor_name(enum radeon_family family)
 251 {
 252         switch (family) {
 253         case CHIP_R600:
 254         case CHIP_RV630:
 255         case CHIP_RV635:
 256         case CHIP_RV670:
 257                 return "r600";
 258         case CHIP_RV610:
 259         case CHIP_RV620:
 260         case CHIP_RS780:
 261         case CHIP_RS880:
 262                 return "rs880";
 263         case CHIP_RV710:
 264                 return "rv710";
 265         case CHIP_RV730:
 266                 return "rv730";
 267         case CHIP_RV740:
 268         case CHIP_RV770:
 269                 return "rv770";
 270         case CHIP_PALM:
 271         case CHIP_CEDAR:
 272                 return "cedar";
 273         case CHIP_SUMO:
 274         case CHIP_SUMO2:
 275                 return "sumo";
 276         case CHIP_REDWOOD:
 277                 return "redwood";
 278         case CHIP_JUNIPER:
 279                 return "juniper";
 280         case CHIP_HEMLOCK:
 281         case CHIP_CYPRESS:
 282                 return "cypress";
 283         case CHIP_BARTS:
 284                 return "barts";
 285         case CHIP_TURKS:
 286                 return "turks";
 287         case CHIP_CAICOS:
 288                 return "caicos";
 289         case CHIP_CAYMAN:
 290         case CHIP_ARUBA:
 291                 return "cayman";
 292
 293         case CHIP_TAHITI: return "tahiti";
 294         case CHIP_PITCAIRN: return "pitcairn";
 295         case CHIP_VERDE: return "verde";
 296         case CHIP_OLAND: return "oland";
 297 #if HAVE_LLVM <= 0x0303
 298         default:
 299                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 300                         __func__, family);
 301                 return "SI";
 302 #else
 303         case CHIP_HAINAN: return "hainan";
 304         case CHIP_BONAIRE: return "bonaire";
 305         case CHIP_KABINI: return "kabini";
 306         case CHIP_KAVERI: return "kaveri";
 307         case CHIP_HAWAII: return "hawaii";
 308         default: return "";
 309 #endif
 310         }
 311 }
 312
 313 static int r600_get_compute_param(struct pipe_screen *screen,
 314         enum pipe_compute_cap param,
 315         void *ret)
 316 {
 317         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 318
 319         //TODO: select these params by asic
 320         switch (param) {
 321         case PIPE_COMPUTE_CAP_IR_TARGET: {
 322                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 323                 if (ret) {
 324                         sprintf(ret, "%s-r600--", gpu);
 325                 }
 326                 return (8 + strlen(gpu)) * sizeof(char);
 327         }
 328         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 329                 if (ret) {
 330                         uint64_t *grid_dimension = ret;
 331                         grid_dimension[0] = 3;
 332                 }
 333                 return 1 * sizeof(uint64_t);
 334
 335         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 336                 if (ret) {
 337                         uint64_t *grid_size = ret;
 338                         grid_size[0] = 65535;
 339                         grid_size[1] = 65535;
 340                         grid_size[2] = 1;
 341                 }
 342                 return 3 * sizeof(uint64_t) ;
 343
 344         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 345                 if (ret) {
 346                         uint64_t *block_size = ret;
 347                         block_size[0] = 256;
 348                         block_size[1] = 256;
 349                         block_size[2] = 256;
 350                 }
 351                 return 3 * sizeof(uint64_t);
 352
 353         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 354                 if (ret) {
 355                         uint64_t *max_threads_per_block = ret;
 356                         *max_threads_per_block = 256;
 357                 }
 358                 return sizeof(uint64_t);
 359
 360         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 361                 if (ret) {
 362                         uint64_t *max_global_size = ret;
 363                         /* XXX: This is what the proprietary driver reports, we
 364                          * may want to use a different value. */
 365                         /* XXX: Not sure what to put here for SI. */
 366                         if (rscreen->chip_class >= SI)
 367                                 *max_global_size = 2000000000;
 368                         else
 369                                 *max_global_size = 201326592;
 370                 }
 371                 return sizeof(uint64_t);
 372
 373         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 374                 if (ret) {
 375                         uint64_t *max_local_size = ret;
 376                         /* Value reported by the closed source driver. */
 377                         *max_local_size = 32768;
 378                 }
 379                 return sizeof(uint64_t);
 380
 381         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 382                 if (ret) {
 383                         uint64_t *max_input_size = ret;
 384                         /* Value reported by the closed source driver. */
 385                         *max_input_size = 1024;
 386                 }
 387                 return sizeof(uint64_t);
 388
 389         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 390                 if (ret) {
 391                         uint64_t max_global_size;
 392                         uint64_t *max_mem_alloc_size = ret;
 393                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 394                         /* OpenCL requres this value be at least
 395                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 396                          * I'm really not sure what value to report here, but
 397                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 398                          */
 399                         *max_mem_alloc_size = max_global_size / 4;
 400                 }
 401                 return sizeof(uint64_t);
 402
 403         default:
 404                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 405                 return 0;
 406         }
 407 }
 408
 409 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 410 {
 411         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 412
 413         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 414                         rscreen->info.r600_clock_crystal_freq;
 415 }
 416
 417 static int r600_get_driver_query_info(struct pipe_screen *screen,
 418                                       unsigned index,
 419                                       struct pipe_driver_query_info *info)
 420 {
 421         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 422         struct pipe_driver_query_info list[] = {
 423                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 424                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 425                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 426                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 427         };
 428
 429         if (!info)
 430                 return Elements(list);
 431
 432         if (index >= Elements(list))
 433                 return 0;
 434
 435         *info = list[index];
 436         return 1;
 437 }
 438
 439 static void r600_fence_reference(struct pipe_screen *screen,
 440                                  struct pipe_fence_handle **ptr,
 441                                  struct pipe_fence_handle *fence)
 442 {
 443         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 444
 445         rws->fence_reference(ptr, fence);
 446 }
 447
 448 static boolean r600_fence_signalled(struct pipe_screen *screen,
 449                                     struct pipe_fence_handle *fence)
 450 {
 451         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 452
 453         return rws->fence_wait(rws, fence, 0);
 454 }
 455
 456 static boolean r600_fence_finish(struct pipe_screen *screen,
 457                                  struct pipe_fence_handle *fence,
 458                                  uint64_t timeout)
 459 {
 460         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 461
 462         return rws->fence_wait(rws, fence, timeout);
 463 }
 464
 465 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 466                                   uint32_t tiling_config)
 467 {
 468         switch ((tiling_config & 0xe) >> 1) {
 469         case 0:
 470                 rscreen->tiling_info.num_channels = 1;
 471                 break;
 472         case 1:
 473                 rscreen->tiling_info.num_channels = 2;
 474                 break;
 475         case 2:
 476                 rscreen->tiling_info.num_channels = 4;
 477                 break;
 478         case 3:
 479                 rscreen->tiling_info.num_channels = 8;
 480                 break;
 481         default:
 482                 return false;
 483         }
 484
 485         switch ((tiling_config & 0x30) >> 4) {
 486         case 0:
 487                 rscreen->tiling_info.num_banks = 4;
 488                 break;
 489         case 1:
 490                 rscreen->tiling_info.num_banks = 8;
 491                 break;
 492         default:
 493                 return false;
 494
 495         }
 496         switch ((tiling_config & 0xc0) >> 6) {
 497         case 0:
 498                 rscreen->tiling_info.group_bytes = 256;
 499                 break;
 500         case 1:
 501                 rscreen->tiling_info.group_bytes = 512;
 502                 break;
 503         default:
 504                 return false;
 505         }
 506         return true;
 507 }
 508
 509 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 510                                        uint32_t tiling_config)
 511 {
 512         switch (tiling_config & 0xf) {
 513         case 0:
 514                 rscreen->tiling_info.num_channels = 1;
 515                 break;
 516         case 1:
 517                 rscreen->tiling_info.num_channels = 2;
 518                 break;
 519         case 2:
 520                 rscreen->tiling_info.num_channels = 4;
 521                 break;
 522         case 3:
 523                 rscreen->tiling_info.num_channels = 8;
 524                 break;
 525         default:
 526                 return false;
 527         }
 528
 529         switch ((tiling_config & 0xf0) >> 4) {
 530         case 0:
 531                 rscreen->tiling_info.num_banks = 4;
 532                 break;
 533         case 1:
 534                 rscreen->tiling_info.num_banks = 8;
 535                 break;
 536         case 2:
 537                 rscreen->tiling_info.num_banks = 16;
 538                 break;
 539         default:
 540                 return false;
 541         }
 542
 543         switch ((tiling_config & 0xf00) >> 8) {
 544         case 0:
 545                 rscreen->tiling_info.group_bytes = 256;
 546                 break;
 547         case 1:
 548                 rscreen->tiling_info.group_bytes = 512;
 549                 break;
 550         default:
 551                 return false;
 552         }
 553         return true;
 554 }
 555
 556 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 557 {
 558         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 559
 560         /* set default group bytes, overridden by tiling info ioctl */
 561         if (rscreen->chip_class <= R700) {
 562                 rscreen->tiling_info.group_bytes = 256;
 563         } else {
 564                 rscreen->tiling_info.group_bytes = 512;
 565         }
 566
 567         if (!tiling_config)
 568                 return true;
 569
 570         if (rscreen->chip_class <= R700) {
 571                 return r600_interpret_tiling(rscreen, tiling_config);
 572         } else {
 573                 return evergreen_interpret_tiling(rscreen, tiling_config);
 574         }
 575 }
 576
 577 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 578                                                   const struct pipe_resource *templ)
 579 {
 580         if (templ->target == PIPE_BUFFER) {
 581                 return r600_buffer_create(screen, templ, 4096);
 582         } else {
 583                 return r600_texture_create(screen, templ);
 584         }
 585 }
 586
 587 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 588                              struct radeon_winsys *ws)
 589 {
 590         ws->query_info(ws, &rscreen->info);
 591
 592         rscreen->b.get_name = r600_get_name;
 593         rscreen->b.get_vendor = r600_get_vendor;
 594         rscreen->b.get_compute_param = r600_get_compute_param;
 595         rscreen->b.get_paramf = r600_get_paramf;
 596         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 597         rscreen->b.get_timestamp = r600_get_timestamp;
 598         rscreen->b.fence_finish = r600_fence_finish;
 599         rscreen->b.fence_reference = r600_fence_reference;
 600         rscreen->b.fence_signalled = r600_fence_signalled;
 601         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 602
 603         if (rscreen->info.has_uvd) {
 604                 rscreen->b.get_video_param = rvid_get_video_param;
 605                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 606         } else {
 607                 rscreen->b.get_video_param = r600_get_video_param;
 608                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 609         }
 610
 611         r600_init_texture_functions(rscreen);
 612
 613         rscreen->ws = ws;
 614         rscreen->family = rscreen->info.family;
 615         rscreen->chip_class = rscreen->info.chip_class;
 616         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 617
 618         if (!r600_init_tiling(rscreen)) {
 619                 return false;
 620         }
 621         util_format_s3tc_init();
 622         pipe_mutex_init(rscreen->aux_context_lock);
 623
 624         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 625                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 626                                                                                 PIPE_BIND_CUSTOM,
 627                                                                                 PIPE_USAGE_STAGING,
 628                                                                                 4096);
 629                 if (rscreen->trace_bo) {
 630                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 631                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 632                 }
 633         }
 634
 635         return true;
 636 }
 637
 638 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 639 {
 640         pipe_mutex_destroy(rscreen->aux_context_lock);
 641         rscreen->aux_context->destroy(rscreen->aux_context);
 642
 643         if (rscreen->trace_bo) {
 644                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 645                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 646         }
 647
 648         rscreen->ws->destroy(rscreen->ws);
 649         FREE(rscreen);
 650 }
 651
 652 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 653 {
 654         struct tgsi_parse_context parse;
 655
 656         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 657                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 658                 return ~0;
 659         }
 660         return parse.FullHeader.Processor.Processor;
 661 }
 662
 663 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 664                           const struct tgsi_token *tokens)
 665 {
 666         /* Compute shader don't have tgsi_tokens */
 667         if (!tokens)
 668                 return (rscreen->debug_flags & DBG_CS) != 0;
 669
 670         switch (tgsi_get_processor_type(tokens)) {
 671         case TGSI_PROCESSOR_VERTEX:
 672                 return (rscreen->debug_flags & DBG_VS) != 0;
 673         case TGSI_PROCESSOR_GEOMETRY:
 674                 return (rscreen->debug_flags & DBG_GS) != 0;
 675         case TGSI_PROCESSOR_FRAGMENT:
 676                 return (rscreen->debug_flags & DBG_PS) != 0;
 677         case TGSI_PROCESSOR_COMPUTE:
 678                 return (rscreen->debug_flags & DBG_CS) != 0;
 679         default:
 680                 return false;
 681         }
 682 }
 683
 684 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 685                               unsigned offset, unsigned size, unsigned value)
 686 {
 687         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 688
 689         pipe_mutex_lock(rscreen->aux_context_lock);
 690         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 691         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 692         pipe_mutex_unlock(rscreen->aux_context_lock);
 693 }