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gallium/radeon: inline the r600_rings structure
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "os/os_time.h"
35 #include "vl/vl_decoder.h"
36 #include "vl/vl_video_buffer.h"
37 #include "radeon/radeon_video.h"
38 #include <inttypes.h>
39
40 #ifndef HAVE_LLVM
41 #define HAVE_LLVM 0
42 #endif
43
44 struct r600_multi_fence {
45 struct pipe_reference reference;
46 struct pipe_fence_handle *gfx;
47 struct pipe_fence_handle *sdma;
48 };
49
50 /*
51 * pipe_context
52 */
53
54 void r600_draw_rectangle(struct blitter_context *blitter,
55 int x1, int y1, int x2, int y2, float depth,
56 enum blitter_attrib_type type,
57 const union pipe_color_union *attrib)
58 {
59 struct r600_common_context *rctx =
60 (struct r600_common_context*)util_blitter_get_pipe(blitter);
61 struct pipe_viewport_state viewport;
62 struct pipe_resource *buf = NULL;
63 unsigned offset = 0;
64 float *vb;
65
66 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
67 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
68 return;
69 }
70
71 /* Some operations (like color resolve on r6xx) don't work
72 * with the conventional primitive types.
73 * One that works is PT_RECTLIST, which we use here. */
74
75 /* setup viewport */
76 viewport.scale[0] = 1.0f;
77 viewport.scale[1] = 1.0f;
78 viewport.scale[2] = 1.0f;
79 viewport.translate[0] = 0.0f;
80 viewport.translate[1] = 0.0f;
81 viewport.translate[2] = 0.0f;
82 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
83
84 /* Upload vertices. The hw rectangle has only 3 vertices,
85 * I guess the 4th one is derived from the first 3.
86 * The vertex specification should match u_blitter's vertex element state. */
87 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
88 if (!buf)
89 return;
90
91 vb[0] = x1;
92 vb[1] = y1;
93 vb[2] = depth;
94 vb[3] = 1;
95
96 vb[8] = x1;
97 vb[9] = y2;
98 vb[10] = depth;
99 vb[11] = 1;
100
101 vb[16] = x2;
102 vb[17] = y1;
103 vb[18] = depth;
104 vb[19] = 1;
105
106 if (attrib) {
107 memcpy(vb+4, attrib->f, sizeof(float)*4);
108 memcpy(vb+12, attrib->f, sizeof(float)*4);
109 memcpy(vb+20, attrib->f, sizeof(float)*4);
110 }
111
112 /* draw */
113 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
114 R600_PRIM_RECTANGLE_LIST, 3, 2);
115 pipe_resource_reference(&buf, NULL);
116 }
117
118 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
119 {
120 /* Flush the GFX IB if it's not empty. */
121 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
122 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
123
124 /* Flush if there's not enough space. */
125 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
126 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
127 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
128 }
129 }
130
131 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
132 {
133 }
134
135 void r600_preflush_suspend_features(struct r600_common_context *ctx)
136 {
137 /* Disable render condition. */
138 ctx->saved_render_cond = NULL;
139 ctx->saved_render_cond_cond = FALSE;
140 ctx->saved_render_cond_mode = 0;
141 if (ctx->current_render_cond) {
142 ctx->saved_render_cond = ctx->current_render_cond;
143 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
144 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
145 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
146 }
147
148 /* suspend queries */
149 ctx->queries_suspended_for_flush = false;
150 if (ctx->num_cs_dw_nontimer_queries_suspend) {
151 r600_suspend_nontimer_queries(ctx);
152 r600_suspend_timer_queries(ctx);
153 ctx->queries_suspended_for_flush = true;
154 }
155
156 ctx->streamout.suspended = false;
157 if (ctx->streamout.begin_emitted) {
158 r600_emit_streamout_end(ctx);
159 ctx->streamout.suspended = true;
160 }
161 }
162
163 void r600_postflush_resume_features(struct r600_common_context *ctx)
164 {
165 if (ctx->streamout.suspended) {
166 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
167 r600_streamout_buffers_dirty(ctx);
168 }
169
170 /* resume queries */
171 if (ctx->queries_suspended_for_flush) {
172 r600_resume_nontimer_queries(ctx);
173 r600_resume_timer_queries(ctx);
174 }
175
176 /* Re-enable render condition. */
177 if (ctx->saved_render_cond) {
178 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
179 ctx->saved_render_cond_cond,
180 ctx->saved_render_cond_mode);
181 }
182 }
183
184 static void r600_flush_from_st(struct pipe_context *ctx,
185 struct pipe_fence_handle **fence,
186 unsigned flags)
187 {
188 struct pipe_screen *screen = ctx->screen;
189 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
190 unsigned rflags = 0;
191 struct pipe_fence_handle *gfx_fence = NULL;
192 struct pipe_fence_handle *sdma_fence = NULL;
193
194 if (flags & PIPE_FLUSH_END_OF_FRAME)
195 rflags |= RADEON_FLUSH_END_OF_FRAME;
196
197 if (rctx->dma.cs) {
198 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
199 }
200 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
201
202 /* Both engines can signal out of order, so we need to keep both fences. */
203 if (gfx_fence || sdma_fence) {
204 struct r600_multi_fence *multi_fence =
205 CALLOC_STRUCT(r600_multi_fence);
206 if (!multi_fence)
207 return;
208
209 multi_fence->reference.count = 1;
210 multi_fence->gfx = gfx_fence;
211 multi_fence->sdma = sdma_fence;
212
213 screen->fence_reference(screen, fence, NULL);
214 *fence = (struct pipe_fence_handle*)multi_fence;
215 }
216 }
217
218 static void r600_flush_dma_ring(void *ctx, unsigned flags,
219 struct pipe_fence_handle **fence)
220 {
221 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
222 struct radeon_winsys_cs *cs = rctx->dma.cs;
223
224 if (cs->cdw)
225 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
226 if (fence)
227 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
228 }
229
230 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
231 {
232 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
233 unsigned latest = rctx->ws->query_value(rctx->ws,
234 RADEON_GPU_RESET_COUNTER);
235
236 if (rctx->gpu_reset_counter == latest)
237 return PIPE_NO_RESET;
238
239 rctx->gpu_reset_counter = latest;
240 return PIPE_UNKNOWN_CONTEXT_RESET;
241 }
242
243 bool r600_common_context_init(struct r600_common_context *rctx,
244 struct r600_common_screen *rscreen)
245 {
246 util_slab_create(&rctx->pool_transfers,
247 sizeof(struct r600_transfer), 64,
248 UTIL_SLAB_SINGLETHREADED);
249
250 rctx->screen = rscreen;
251 rctx->ws = rscreen->ws;
252 rctx->family = rscreen->family;
253 rctx->chip_class = rscreen->chip_class;
254
255 if (rscreen->family == CHIP_HAWAII)
256 rctx->max_db = 16;
257 else if (rscreen->chip_class >= EVERGREEN)
258 rctx->max_db = 8;
259 else
260 rctx->max_db = 4;
261
262 rctx->b.transfer_map = u_transfer_map_vtbl;
263 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
264 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
265 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
266 rctx->b.memory_barrier = r600_memory_barrier;
267 rctx->b.flush = r600_flush_from_st;
268
269 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
270 rctx->b.get_device_reset_status = r600_get_reset_status;
271 rctx->gpu_reset_counter =
272 rctx->ws->query_value(rctx->ws,
273 RADEON_GPU_RESET_COUNTER);
274 }
275
276 LIST_INITHEAD(&rctx->texture_buffers);
277
278 r600_init_context_texture_functions(rctx);
279 r600_streamout_init(rctx);
280 r600_query_init(rctx);
281 cayman_init_msaa(&rctx->b);
282
283 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
284 0, PIPE_USAGE_DEFAULT, TRUE);
285 if (!rctx->allocator_so_filled_size)
286 return false;
287
288 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
289 PIPE_BIND_INDEX_BUFFER |
290 PIPE_BIND_CONSTANT_BUFFER);
291 if (!rctx->uploader)
292 return false;
293
294 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
295 if (!rctx->ctx)
296 return false;
297
298 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
299 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
300 r600_flush_dma_ring,
301 rctx, NULL);
302 rctx->dma.flush = r600_flush_dma_ring;
303 }
304
305 return true;
306 }
307
308 void r600_common_context_cleanup(struct r600_common_context *rctx)
309 {
310 if (rctx->gfx.cs)
311 rctx->ws->cs_destroy(rctx->gfx.cs);
312 if (rctx->dma.cs)
313 rctx->ws->cs_destroy(rctx->dma.cs);
314 if (rctx->ctx)
315 rctx->ws->ctx_destroy(rctx->ctx);
316
317 if (rctx->uploader) {
318 u_upload_destroy(rctx->uploader);
319 }
320
321 util_slab_destroy(&rctx->pool_transfers);
322
323 if (rctx->allocator_so_filled_size) {
324 u_suballocator_destroy(rctx->allocator_so_filled_size);
325 }
326 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
327 }
328
329 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
330 {
331 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
332 struct r600_resource *rr = (struct r600_resource *)r;
333
334 if (r == NULL) {
335 return;
336 }
337
338 /*
339 * The idea is to compute a gross estimate of memory requirement of
340 * each draw call. After each draw call, memory will be precisely
341 * accounted. So the uncertainty is only on the current draw call.
342 * In practice this gave very good estimate (+/- 10% of the target
343 * memory limit).
344 */
345 if (rr->domains & RADEON_DOMAIN_GTT) {
346 rctx->gtt += rr->buf->size;
347 }
348 if (rr->domains & RADEON_DOMAIN_VRAM) {
349 rctx->vram += rr->buf->size;
350 }
351 }
352
353 /*
354 * pipe_screen
355 */
356
357 static const struct debug_named_value common_debug_options[] = {
358 /* logging */
359 { "tex", DBG_TEX, "Print texture info" },
360 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
361 { "compute", DBG_COMPUTE, "Print compute info" },
362 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
363 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
364 { "info", DBG_INFO, "Print driver information" },
365
366 /* shaders */
367 { "fs", DBG_FS, "Print fetch shaders" },
368 { "vs", DBG_VS, "Print vertex shaders" },
369 { "gs", DBG_GS, "Print geometry shaders" },
370 { "ps", DBG_PS, "Print pixel shaders" },
371 { "cs", DBG_CS, "Print compute shaders" },
372 { "tcs", DBG_TCS, "Print tessellation control shaders" },
373 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
374 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
375 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
376 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
377
378 /* features */
379 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
380 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
381 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
382 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
383 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
384 { "notiling", DBG_NO_TILING, "Disable tiling" },
385 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
386 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
387 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
388 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
389 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
390 { "nodcc", DBG_NO_DCC, "Disable DCC." },
391 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
392
393 DEBUG_NAMED_VALUE_END /* must be last */
394 };
395
396 static const char* r600_get_vendor(struct pipe_screen* pscreen)
397 {
398 return "X.Org";
399 }
400
401 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
402 {
403 return "AMD";
404 }
405
406 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
407 {
408 switch (rscreen->info.family) {
409 case CHIP_R600: return "AMD R600";
410 case CHIP_RV610: return "AMD RV610";
411 case CHIP_RV630: return "AMD RV630";
412 case CHIP_RV670: return "AMD RV670";
413 case CHIP_RV620: return "AMD RV620";
414 case CHIP_RV635: return "AMD RV635";
415 case CHIP_RS780: return "AMD RS780";
416 case CHIP_RS880: return "AMD RS880";
417 case CHIP_RV770: return "AMD RV770";
418 case CHIP_RV730: return "AMD RV730";
419 case CHIP_RV710: return "AMD RV710";
420 case CHIP_RV740: return "AMD RV740";
421 case CHIP_CEDAR: return "AMD CEDAR";
422 case CHIP_REDWOOD: return "AMD REDWOOD";
423 case CHIP_JUNIPER: return "AMD JUNIPER";
424 case CHIP_CYPRESS: return "AMD CYPRESS";
425 case CHIP_HEMLOCK: return "AMD HEMLOCK";
426 case CHIP_PALM: return "AMD PALM";
427 case CHIP_SUMO: return "AMD SUMO";
428 case CHIP_SUMO2: return "AMD SUMO2";
429 case CHIP_BARTS: return "AMD BARTS";
430 case CHIP_TURKS: return "AMD TURKS";
431 case CHIP_CAICOS: return "AMD CAICOS";
432 case CHIP_CAYMAN: return "AMD CAYMAN";
433 case CHIP_ARUBA: return "AMD ARUBA";
434 case CHIP_TAHITI: return "AMD TAHITI";
435 case CHIP_PITCAIRN: return "AMD PITCAIRN";
436 case CHIP_VERDE: return "AMD CAPE VERDE";
437 case CHIP_OLAND: return "AMD OLAND";
438 case CHIP_HAINAN: return "AMD HAINAN";
439 case CHIP_BONAIRE: return "AMD BONAIRE";
440 case CHIP_KAVERI: return "AMD KAVERI";
441 case CHIP_KABINI: return "AMD KABINI";
442 case CHIP_HAWAII: return "AMD HAWAII";
443 case CHIP_MULLINS: return "AMD MULLINS";
444 case CHIP_TONGA: return "AMD TONGA";
445 case CHIP_ICELAND: return "AMD ICELAND";
446 case CHIP_CARRIZO: return "AMD CARRIZO";
447 case CHIP_FIJI: return "AMD FIJI";
448 case CHIP_STONEY: return "AMD STONEY";
449 default: return "AMD unknown";
450 }
451 }
452
453 static const char* r600_get_name(struct pipe_screen* pscreen)
454 {
455 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
456
457 return rscreen->renderer_string;
458 }
459
460 static float r600_get_paramf(struct pipe_screen* pscreen,
461 enum pipe_capf param)
462 {
463 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
464
465 switch (param) {
466 case PIPE_CAPF_MAX_LINE_WIDTH:
467 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
468 case PIPE_CAPF_MAX_POINT_WIDTH:
469 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
470 if (rscreen->family >= CHIP_CEDAR)
471 return 16384.0f;
472 else
473 return 8192.0f;
474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
475 return 16.0f;
476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
477 return 16.0f;
478 case PIPE_CAPF_GUARD_BAND_LEFT:
479 case PIPE_CAPF_GUARD_BAND_TOP:
480 case PIPE_CAPF_GUARD_BAND_RIGHT:
481 case PIPE_CAPF_GUARD_BAND_BOTTOM:
482 return 0.0f;
483 }
484 return 0.0f;
485 }
486
487 static int r600_get_video_param(struct pipe_screen *screen,
488 enum pipe_video_profile profile,
489 enum pipe_video_entrypoint entrypoint,
490 enum pipe_video_cap param)
491 {
492 switch (param) {
493 case PIPE_VIDEO_CAP_SUPPORTED:
494 return vl_profile_supported(screen, profile, entrypoint);
495 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
496 return 1;
497 case PIPE_VIDEO_CAP_MAX_WIDTH:
498 case PIPE_VIDEO_CAP_MAX_HEIGHT:
499 return vl_video_buffer_max_size(screen);
500 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
501 return PIPE_FORMAT_NV12;
502 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
503 return false;
504 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
505 return false;
506 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
507 return true;
508 case PIPE_VIDEO_CAP_MAX_LEVEL:
509 return vl_level_supported(screen, profile);
510 default:
511 return 0;
512 }
513 }
514
515 const char *r600_get_llvm_processor_name(enum radeon_family family)
516 {
517 switch (family) {
518 case CHIP_R600:
519 case CHIP_RV630:
520 case CHIP_RV635:
521 case CHIP_RV670:
522 return "r600";
523 case CHIP_RV610:
524 case CHIP_RV620:
525 case CHIP_RS780:
526 case CHIP_RS880:
527 return "rs880";
528 case CHIP_RV710:
529 return "rv710";
530 case CHIP_RV730:
531 return "rv730";
532 case CHIP_RV740:
533 case CHIP_RV770:
534 return "rv770";
535 case CHIP_PALM:
536 case CHIP_CEDAR:
537 return "cedar";
538 case CHIP_SUMO:
539 case CHIP_SUMO2:
540 return "sumo";
541 case CHIP_REDWOOD:
542 return "redwood";
543 case CHIP_JUNIPER:
544 return "juniper";
545 case CHIP_HEMLOCK:
546 case CHIP_CYPRESS:
547 return "cypress";
548 case CHIP_BARTS:
549 return "barts";
550 case CHIP_TURKS:
551 return "turks";
552 case CHIP_CAICOS:
553 return "caicos";
554 case CHIP_CAYMAN:
555 case CHIP_ARUBA:
556 return "cayman";
557
558 case CHIP_TAHITI: return "tahiti";
559 case CHIP_PITCAIRN: return "pitcairn";
560 case CHIP_VERDE: return "verde";
561 case CHIP_OLAND: return "oland";
562 case CHIP_HAINAN: return "hainan";
563 case CHIP_BONAIRE: return "bonaire";
564 case CHIP_KABINI: return "kabini";
565 case CHIP_KAVERI: return "kaveri";
566 case CHIP_HAWAII: return "hawaii";
567 case CHIP_MULLINS:
568 return "mullins";
569 case CHIP_TONGA: return "tonga";
570 case CHIP_ICELAND: return "iceland";
571 case CHIP_CARRIZO: return "carrizo";
572 case CHIP_FIJI: return "fiji";
573 #if HAVE_LLVM <= 0x0307
574 case CHIP_STONEY: return "carrizo";
575 #else
576 case CHIP_STONEY: return "stoney";
577 #endif
578 default: return "";
579 }
580 }
581
582 static int r600_get_compute_param(struct pipe_screen *screen,
583 enum pipe_compute_cap param,
584 void *ret)
585 {
586 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
587
588 //TODO: select these params by asic
589 switch (param) {
590 case PIPE_COMPUTE_CAP_IR_TARGET: {
591 const char *gpu;
592 const char *triple;
593 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
594 triple = "r600--";
595 } else {
596 triple = "amdgcn--";
597 }
598 switch(rscreen->family) {
599 /* Clang < 3.6 is missing Hainan in its list of
600 * GPUs, so we need to use the name of a similar GPU.
601 */
602 #if HAVE_LLVM < 0x0306
603 case CHIP_HAINAN:
604 gpu = "oland";
605 break;
606 #endif
607 default:
608 gpu = r600_get_llvm_processor_name(rscreen->family);
609 break;
610 }
611 if (ret) {
612 sprintf(ret, "%s-%s", gpu, triple);
613 }
614 /* +2 for dash and terminating NIL byte */
615 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
616 }
617 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
618 if (ret) {
619 uint64_t *grid_dimension = ret;
620 grid_dimension[0] = 3;
621 }
622 return 1 * sizeof(uint64_t);
623
624 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
625 if (ret) {
626 uint64_t *grid_size = ret;
627 grid_size[0] = 65535;
628 grid_size[1] = 65535;
629 grid_size[2] = 1;
630 }
631 return 3 * sizeof(uint64_t) ;
632
633 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
634 if (ret) {
635 uint64_t *block_size = ret;
636 block_size[0] = 256;
637 block_size[1] = 256;
638 block_size[2] = 256;
639 }
640 return 3 * sizeof(uint64_t);
641
642 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
643 if (ret) {
644 uint64_t *max_threads_per_block = ret;
645 *max_threads_per_block = 256;
646 }
647 return sizeof(uint64_t);
648
649 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
650 if (ret) {
651 uint64_t *max_global_size = ret;
652 uint64_t max_mem_alloc_size;
653
654 r600_get_compute_param(screen,
655 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
656 &max_mem_alloc_size);
657
658 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
659 * 1/4 of the MAX_GLOBAL_SIZE. Since the
660 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
661 * make sure we never report more than
662 * 4 * MAX_MEM_ALLOC_SIZE.
663 */
664 *max_global_size = MIN2(4 * max_mem_alloc_size,
665 rscreen->info.gart_size +
666 rscreen->info.vram_size);
667 }
668 return sizeof(uint64_t);
669
670 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
671 if (ret) {
672 uint64_t *max_local_size = ret;
673 /* Value reported by the closed source driver. */
674 *max_local_size = 32768;
675 }
676 return sizeof(uint64_t);
677
678 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
679 if (ret) {
680 uint64_t *max_input_size = ret;
681 /* Value reported by the closed source driver. */
682 *max_input_size = 1024;
683 }
684 return sizeof(uint64_t);
685
686 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
687 if (ret) {
688 uint64_t *max_mem_alloc_size = ret;
689
690 /* XXX: The limit in older kernels is 256 MB. We
691 * should add a query here for newer kernels.
692 */
693 *max_mem_alloc_size = 256 * 1024 * 1024;
694 }
695 return sizeof(uint64_t);
696
697 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
698 if (ret) {
699 uint32_t *max_clock_frequency = ret;
700 *max_clock_frequency = rscreen->info.max_sclk;
701 }
702 return sizeof(uint32_t);
703
704 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
705 if (ret) {
706 uint32_t *max_compute_units = ret;
707 *max_compute_units = rscreen->info.max_compute_units;
708 }
709 return sizeof(uint32_t);
710
711 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
712 if (ret) {
713 uint32_t *images_supported = ret;
714 *images_supported = 0;
715 }
716 return sizeof(uint32_t);
717 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
718 break; /* unused */
719 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
720 if (ret) {
721 uint32_t *subgroup_size = ret;
722 *subgroup_size = r600_wavefront_size(rscreen->family);
723 }
724 return sizeof(uint32_t);
725 }
726
727 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
728 return 0;
729 }
730
731 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
732 {
733 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
734
735 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
736 rscreen->info.r600_clock_crystal_freq;
737 }
738
739 static int r600_get_driver_query_info(struct pipe_screen *screen,
740 unsigned index,
741 struct pipe_driver_query_info *info)
742 {
743 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
744 struct pipe_driver_query_info list[] = {
745 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
746 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
747 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
748 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
749 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
750 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
751 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
752 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
753 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
754 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
755 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
756 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
757 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
758 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
759 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
760 {"temperature", R600_QUERY_GPU_TEMPERATURE, {125}},
761 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
762 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
763 };
764 unsigned num_queries;
765
766 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
767 num_queries = Elements(list);
768 else if (rscreen->info.drm_major == 3)
769 num_queries = Elements(list) - 3;
770 else
771 num_queries = Elements(list) - 4;
772
773 if (!info)
774 return num_queries;
775
776 if (index >= num_queries)
777 return 0;
778
779 *info = list[index];
780 return 1;
781 }
782
783 static void r600_fence_reference(struct pipe_screen *screen,
784 struct pipe_fence_handle **dst,
785 struct pipe_fence_handle *src)
786 {
787 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
788 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
789 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
790
791 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
792 ws->fence_reference(&(*rdst)->gfx, NULL);
793 ws->fence_reference(&(*rdst)->sdma, NULL);
794 FREE(*rdst);
795 }
796 *rdst = rsrc;
797 }
798
799 static boolean r600_fence_finish(struct pipe_screen *screen,
800 struct pipe_fence_handle *fence,
801 uint64_t timeout)
802 {
803 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
804 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
805 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
806
807 if (rfence->sdma) {
808 if (!rws->fence_wait(rws, rfence->sdma, timeout))
809 return false;
810
811 /* Recompute the timeout after waiting. */
812 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
813 int64_t time = os_time_get_nano();
814 timeout = abs_timeout > time ? abs_timeout - time : 0;
815 }
816 }
817
818 if (!rfence->gfx)
819 return true;
820
821 return rws->fence_wait(rws, rfence->gfx, timeout);
822 }
823
824 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
825 uint32_t tiling_config)
826 {
827 switch ((tiling_config & 0xe) >> 1) {
828 case 0:
829 rscreen->tiling_info.num_channels = 1;
830 break;
831 case 1:
832 rscreen->tiling_info.num_channels = 2;
833 break;
834 case 2:
835 rscreen->tiling_info.num_channels = 4;
836 break;
837 case 3:
838 rscreen->tiling_info.num_channels = 8;
839 break;
840 default:
841 return false;
842 }
843
844 switch ((tiling_config & 0x30) >> 4) {
845 case 0:
846 rscreen->tiling_info.num_banks = 4;
847 break;
848 case 1:
849 rscreen->tiling_info.num_banks = 8;
850 break;
851 default:
852 return false;
853
854 }
855 switch ((tiling_config & 0xc0) >> 6) {
856 case 0:
857 rscreen->tiling_info.group_bytes = 256;
858 break;
859 case 1:
860 rscreen->tiling_info.group_bytes = 512;
861 break;
862 default:
863 return false;
864 }
865 return true;
866 }
867
868 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
869 uint32_t tiling_config)
870 {
871 switch (tiling_config & 0xf) {
872 case 0:
873 rscreen->tiling_info.num_channels = 1;
874 break;
875 case 1:
876 rscreen->tiling_info.num_channels = 2;
877 break;
878 case 2:
879 rscreen->tiling_info.num_channels = 4;
880 break;
881 case 3:
882 rscreen->tiling_info.num_channels = 8;
883 break;
884 default:
885 return false;
886 }
887
888 switch ((tiling_config & 0xf0) >> 4) {
889 case 0:
890 rscreen->tiling_info.num_banks = 4;
891 break;
892 case 1:
893 rscreen->tiling_info.num_banks = 8;
894 break;
895 case 2:
896 rscreen->tiling_info.num_banks = 16;
897 break;
898 default:
899 return false;
900 }
901
902 switch ((tiling_config & 0xf00) >> 8) {
903 case 0:
904 rscreen->tiling_info.group_bytes = 256;
905 break;
906 case 1:
907 rscreen->tiling_info.group_bytes = 512;
908 break;
909 default:
910 return false;
911 }
912 return true;
913 }
914
915 static bool r600_init_tiling(struct r600_common_screen *rscreen)
916 {
917 uint32_t tiling_config = rscreen->info.r600_tiling_config;
918
919 /* set default group bytes, overridden by tiling info ioctl */
920 if (rscreen->chip_class <= R700) {
921 rscreen->tiling_info.group_bytes = 256;
922 } else {
923 rscreen->tiling_info.group_bytes = 512;
924 }
925
926 if (!tiling_config)
927 return true;
928
929 if (rscreen->chip_class <= R700) {
930 return r600_interpret_tiling(rscreen, tiling_config);
931 } else {
932 return evergreen_interpret_tiling(rscreen, tiling_config);
933 }
934 }
935
936 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
937 const struct pipe_resource *templ)
938 {
939 if (templ->target == PIPE_BUFFER) {
940 return r600_buffer_create(screen, templ, 4096);
941 } else {
942 return r600_texture_create(screen, templ);
943 }
944 }
945
946 bool r600_common_screen_init(struct r600_common_screen *rscreen,
947 struct radeon_winsys *ws)
948 {
949 char llvm_string[32] = {};
950
951 ws->query_info(ws, &rscreen->info);
952
953 #if HAVE_LLVM
954 snprintf(llvm_string, sizeof(llvm_string),
955 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
956 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
957 #endif
958
959 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
960 "%s (DRM %i.%i.%i%s)",
961 r600_get_chip_name(rscreen), rscreen->info.drm_major,
962 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
963 llvm_string);
964
965 rscreen->b.get_name = r600_get_name;
966 rscreen->b.get_vendor = r600_get_vendor;
967 rscreen->b.get_device_vendor = r600_get_device_vendor;
968 rscreen->b.get_compute_param = r600_get_compute_param;
969 rscreen->b.get_paramf = r600_get_paramf;
970 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
971 rscreen->b.get_timestamp = r600_get_timestamp;
972 rscreen->b.fence_finish = r600_fence_finish;
973 rscreen->b.fence_reference = r600_fence_reference;
974 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
975 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
976
977 if (rscreen->info.has_uvd) {
978 rscreen->b.get_video_param = rvid_get_video_param;
979 rscreen->b.is_video_format_supported = rvid_is_format_supported;
980 } else {
981 rscreen->b.get_video_param = r600_get_video_param;
982 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
983 }
984
985 r600_init_screen_texture_functions(rscreen);
986
987 rscreen->ws = ws;
988 rscreen->family = rscreen->info.family;
989 rscreen->chip_class = rscreen->info.chip_class;
990 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
991
992 if (!r600_init_tiling(rscreen)) {
993 return false;
994 }
995 util_format_s3tc_init();
996 pipe_mutex_init(rscreen->aux_context_lock);
997 pipe_mutex_init(rscreen->gpu_load_mutex);
998
999 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
1000 rscreen->info.drm_major == 3) &&
1001 (rscreen->debug_flags & DBG_TRACE_CS)) {
1002 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
1003 PIPE_BIND_CUSTOM,
1004 PIPE_USAGE_STAGING,
1005 4096);
1006 if (rscreen->trace_bo) {
1007 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1008 PIPE_TRANSFER_UNSYNCHRONIZED);
1009 }
1010 }
1011
1012 if (rscreen->debug_flags & DBG_INFO) {
1013 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1014 printf("family = %i\n", rscreen->info.family);
1015 printf("chip_class = %i\n", rscreen->info.chip_class);
1016 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
1017 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
1018 printf("max_sclk = %i\n", rscreen->info.max_sclk);
1019 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
1020 printf("max_se = %i\n", rscreen->info.max_se);
1021 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1022 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1023 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1024 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1025 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1026 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
1027 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
1028 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
1029 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
1030 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
1031 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
1032 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
1033 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
1034 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
1035 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
1036 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
1037 }
1038 return true;
1039 }
1040
1041 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1042 {
1043 r600_gpu_load_kill_thread(rscreen);
1044
1045 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1046 pipe_mutex_destroy(rscreen->aux_context_lock);
1047 rscreen->aux_context->destroy(rscreen->aux_context);
1048
1049 if (rscreen->trace_bo)
1050 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
1051
1052 rscreen->ws->destroy(rscreen->ws);
1053 FREE(rscreen);
1054 }
1055
1056 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1057 const struct tgsi_token *tokens)
1058 {
1059 /* Compute shader don't have tgsi_tokens */
1060 if (!tokens)
1061 return (rscreen->debug_flags & DBG_CS) != 0;
1062
1063 switch (tgsi_get_processor_type(tokens)) {
1064 case TGSI_PROCESSOR_VERTEX:
1065 return (rscreen->debug_flags & DBG_VS) != 0;
1066 case TGSI_PROCESSOR_TESS_CTRL:
1067 return (rscreen->debug_flags & DBG_TCS) != 0;
1068 case TGSI_PROCESSOR_TESS_EVAL:
1069 return (rscreen->debug_flags & DBG_TES) != 0;
1070 case TGSI_PROCESSOR_GEOMETRY:
1071 return (rscreen->debug_flags & DBG_GS) != 0;
1072 case TGSI_PROCESSOR_FRAGMENT:
1073 return (rscreen->debug_flags & DBG_PS) != 0;
1074 case TGSI_PROCESSOR_COMPUTE:
1075 return (rscreen->debug_flags & DBG_CS) != 0;
1076 default:
1077 return false;
1078 }
1079 }
1080
1081 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1082 unsigned offset, unsigned size, unsigned value,
1083 bool is_framebuffer)
1084 {
1085 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1086
1087 pipe_mutex_lock(rscreen->aux_context_lock);
1088 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1089 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1090 pipe_mutex_unlock(rscreen->aux_context_lock);
1091 }