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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40
41 #ifndef HAVE_LLVM
42 #define HAVE_LLVM 0
43 #endif
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49 };
50
51 /*
52 * shader binary helpers.
53 */
54 void radeon_shader_binary_init(struct radeon_shader_binary *b)
55 {
56 memset(b, 0, sizeof(*b));
57 }
58
59 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
60 {
61 if (!b)
62 return;
63 FREE(b->code);
64 FREE(b->config);
65 FREE(b->rodata);
66 FREE(b->global_symbol_offsets);
67 FREE(b->relocs);
68 FREE(b->disasm_string);
69 }
70
71 /*
72 * pipe_context
73 */
74
75 void r600_draw_rectangle(struct blitter_context *blitter,
76 int x1, int y1, int x2, int y2, float depth,
77 enum blitter_attrib_type type,
78 const union pipe_color_union *attrib)
79 {
80 struct r600_common_context *rctx =
81 (struct r600_common_context*)util_blitter_get_pipe(blitter);
82 struct pipe_viewport_state viewport;
83 struct pipe_resource *buf = NULL;
84 unsigned offset = 0;
85 float *vb;
86
87 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
88 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
89 return;
90 }
91
92 /* Some operations (like color resolve on r6xx) don't work
93 * with the conventional primitive types.
94 * One that works is PT_RECTLIST, which we use here. */
95
96 /* setup viewport */
97 viewport.scale[0] = 1.0f;
98 viewport.scale[1] = 1.0f;
99 viewport.scale[2] = 1.0f;
100 viewport.translate[0] = 0.0f;
101 viewport.translate[1] = 0.0f;
102 viewport.translate[2] = 0.0f;
103 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
104
105 /* Upload vertices. The hw rectangle has only 3 vertices,
106 * I guess the 4th one is derived from the first 3.
107 * The vertex specification should match u_blitter's vertex element state. */
108 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
109 if (!buf)
110 return;
111
112 vb[0] = x1;
113 vb[1] = y1;
114 vb[2] = depth;
115 vb[3] = 1;
116
117 vb[8] = x1;
118 vb[9] = y2;
119 vb[10] = depth;
120 vb[11] = 1;
121
122 vb[16] = x2;
123 vb[17] = y1;
124 vb[18] = depth;
125 vb[19] = 1;
126
127 if (attrib) {
128 memcpy(vb+4, attrib->f, sizeof(float)*4);
129 memcpy(vb+12, attrib->f, sizeof(float)*4);
130 memcpy(vb+20, attrib->f, sizeof(float)*4);
131 }
132
133 /* draw */
134 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
135 R600_PRIM_RECTANGLE_LIST, 3, 2);
136 pipe_resource_reference(&buf, NULL);
137 }
138
139 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
140 struct r600_resource *dst, struct r600_resource *src)
141 {
142 uint64_t vram = 0, gtt = 0;
143
144 if (dst) {
145 if (dst->domains & RADEON_DOMAIN_VRAM)
146 vram += dst->buf->size;
147 else if (dst->domains & RADEON_DOMAIN_GTT)
148 gtt += dst->buf->size;
149 }
150 if (src) {
151 if (src->domains & RADEON_DOMAIN_VRAM)
152 vram += src->buf->size;
153 else if (src->domains & RADEON_DOMAIN_GTT)
154 gtt += src->buf->size;
155 }
156
157 /* Flush the GFX IB if DMA depends on it. */
158 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
159 ((dst &&
160 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
161 RADEON_USAGE_READWRITE)) ||
162 (src &&
163 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
164 RADEON_USAGE_WRITE))))
165 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
166
167 /* Flush if there's not enough space, or if the memory usage per IB
168 * is too large.
169 */
170 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw ||
171 !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
172 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
173 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
174 }
175
176 /* If GPUVM is not supported, the CS checker needs 2 entries
177 * in the buffer list per packet, which has to be done manually.
178 */
179 if (ctx->screen->info.has_virtual_memory) {
180 if (dst)
181 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
182 RADEON_USAGE_WRITE,
183 RADEON_PRIO_SDMA_BUFFER);
184 if (src)
185 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
186 RADEON_USAGE_READ,
187 RADEON_PRIO_SDMA_BUFFER);
188 }
189 }
190
191 /* This is required to prevent read-after-write hazards. */
192 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
193 {
194 struct radeon_winsys_cs *cs = rctx->dma.cs;
195
196 /* done at the end of DMA calls, so increment this. */
197 rctx->num_dma_calls++;
198
199 /* IBs using too little memory are limited by the IB submission overhead.
200 * IBs using too much memory are limited by the kernel/TTM overhead.
201 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
202 *
203 * This heuristic makes sure that DMA requests are executed
204 * very soon after the call is made and lowers memory usage.
205 * It improves texture upload performance by keeping the DMA
206 * engine busy while uploads are being submitted.
207 */
208 if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
209 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
210 return;
211 }
212
213 r600_need_dma_space(rctx, 1, NULL, NULL);
214
215 if (!radeon_emitted(cs, 0)) /* empty queue */
216 return;
217
218 /* NOP waits for idle on Evergreen and later. */
219 if (rctx->chip_class >= CIK)
220 radeon_emit(cs, 0x00000000); /* NOP */
221 else if (rctx->chip_class >= EVERGREEN)
222 radeon_emit(cs, 0xf0000000); /* NOP */
223 else {
224 /* TODO: R600-R700 should use the FENCE packet.
225 * CS checker support is required. */
226 }
227 }
228
229 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
230 {
231 }
232
233 void r600_preflush_suspend_features(struct r600_common_context *ctx)
234 {
235 /* suspend queries */
236 if (!LIST_IS_EMPTY(&ctx->active_queries))
237 r600_suspend_queries(ctx);
238
239 ctx->streamout.suspended = false;
240 if (ctx->streamout.begin_emitted) {
241 r600_emit_streamout_end(ctx);
242 ctx->streamout.suspended = true;
243 }
244 }
245
246 void r600_postflush_resume_features(struct r600_common_context *ctx)
247 {
248 if (ctx->streamout.suspended) {
249 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
250 r600_streamout_buffers_dirty(ctx);
251 }
252
253 /* resume queries */
254 if (!LIST_IS_EMPTY(&ctx->active_queries))
255 r600_resume_queries(ctx);
256 }
257
258 static void r600_flush_from_st(struct pipe_context *ctx,
259 struct pipe_fence_handle **fence,
260 unsigned flags)
261 {
262 struct pipe_screen *screen = ctx->screen;
263 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
264 unsigned rflags = 0;
265 struct pipe_fence_handle *gfx_fence = NULL;
266 struct pipe_fence_handle *sdma_fence = NULL;
267
268 if (flags & PIPE_FLUSH_END_OF_FRAME)
269 rflags |= RADEON_FLUSH_END_OF_FRAME;
270
271 if (rctx->dma.cs) {
272 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
273 }
274 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
275
276 /* Both engines can signal out of order, so we need to keep both fences. */
277 if (gfx_fence || sdma_fence) {
278 struct r600_multi_fence *multi_fence =
279 CALLOC_STRUCT(r600_multi_fence);
280 if (!multi_fence)
281 return;
282
283 multi_fence->reference.count = 1;
284 multi_fence->gfx = gfx_fence;
285 multi_fence->sdma = sdma_fence;
286
287 screen->fence_reference(screen, fence, NULL);
288 *fence = (struct pipe_fence_handle*)multi_fence;
289 }
290 }
291
292 static void r600_flush_dma_ring(void *ctx, unsigned flags,
293 struct pipe_fence_handle **fence)
294 {
295 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
296 struct radeon_winsys_cs *cs = rctx->dma.cs;
297
298 if (radeon_emitted(cs, 0))
299 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
300 if (fence)
301 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
302 }
303
304 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
305 {
306 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
307 unsigned latest = rctx->ws->query_value(rctx->ws,
308 RADEON_GPU_RESET_COUNTER);
309
310 if (rctx->gpu_reset_counter == latest)
311 return PIPE_NO_RESET;
312
313 rctx->gpu_reset_counter = latest;
314 return PIPE_UNKNOWN_CONTEXT_RESET;
315 }
316
317 static void r600_set_debug_callback(struct pipe_context *ctx,
318 const struct pipe_debug_callback *cb)
319 {
320 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
321
322 if (cb)
323 rctx->debug = *cb;
324 else
325 memset(&rctx->debug, 0, sizeof(rctx->debug));
326 }
327
328 bool r600_common_context_init(struct r600_common_context *rctx,
329 struct r600_common_screen *rscreen)
330 {
331 util_slab_create(&rctx->pool_transfers,
332 sizeof(struct r600_transfer), 64,
333 UTIL_SLAB_SINGLETHREADED);
334
335 rctx->screen = rscreen;
336 rctx->ws = rscreen->ws;
337 rctx->family = rscreen->family;
338 rctx->chip_class = rscreen->chip_class;
339
340 if (rscreen->chip_class >= CIK)
341 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
342 else if (rscreen->chip_class >= EVERGREEN)
343 rctx->max_db = 8;
344 else
345 rctx->max_db = 4;
346
347 rctx->b.invalidate_resource = r600_invalidate_resource;
348 rctx->b.transfer_map = u_transfer_map_vtbl;
349 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
350 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
351 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
352 rctx->b.memory_barrier = r600_memory_barrier;
353 rctx->b.flush = r600_flush_from_st;
354 rctx->b.set_debug_callback = r600_set_debug_callback;
355
356 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
357 rctx->b.get_device_reset_status = r600_get_reset_status;
358 rctx->gpu_reset_counter =
359 rctx->ws->query_value(rctx->ws,
360 RADEON_GPU_RESET_COUNTER);
361 }
362
363 LIST_INITHEAD(&rctx->texture_buffers);
364
365 r600_init_context_texture_functions(rctx);
366 r600_init_viewport_functions(rctx);
367 r600_streamout_init(rctx);
368 r600_query_init(rctx);
369 cayman_init_msaa(&rctx->b);
370
371 rctx->allocator_so_filled_size =
372 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
373 4, 0, PIPE_USAGE_DEFAULT, TRUE);
374 if (!rctx->allocator_so_filled_size)
375 return false;
376
377 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
378 PIPE_BIND_INDEX_BUFFER |
379 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
380 if (!rctx->uploader)
381 return false;
382
383 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
384 if (!rctx->ctx)
385 return false;
386
387 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
388 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
389 r600_flush_dma_ring,
390 rctx);
391 rctx->dma.flush = r600_flush_dma_ring;
392 }
393
394 return true;
395 }
396
397 void r600_common_context_cleanup(struct r600_common_context *rctx)
398 {
399 if (rctx->gfx.cs)
400 rctx->ws->cs_destroy(rctx->gfx.cs);
401 if (rctx->dma.cs)
402 rctx->ws->cs_destroy(rctx->dma.cs);
403 if (rctx->ctx)
404 rctx->ws->ctx_destroy(rctx->ctx);
405
406 if (rctx->uploader) {
407 u_upload_destroy(rctx->uploader);
408 }
409
410 util_slab_destroy(&rctx->pool_transfers);
411
412 if (rctx->allocator_so_filled_size) {
413 u_suballocator_destroy(rctx->allocator_so_filled_size);
414 }
415 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
416 }
417
418 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
419 {
420 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
421 struct r600_resource *rr = (struct r600_resource *)r;
422
423 if (!r) {
424 return;
425 }
426
427 /*
428 * The idea is to compute a gross estimate of memory requirement of
429 * each draw call. After each draw call, memory will be precisely
430 * accounted. So the uncertainty is only on the current draw call.
431 * In practice this gave very good estimate (+/- 10% of the target
432 * memory limit).
433 */
434 if (rr->domains & RADEON_DOMAIN_VRAM)
435 rctx->vram += rr->buf->size;
436 else if (rr->domains & RADEON_DOMAIN_GTT)
437 rctx->gtt += rr->buf->size;
438 }
439
440 /*
441 * pipe_screen
442 */
443
444 static const struct debug_named_value common_debug_options[] = {
445 /* logging */
446 { "tex", DBG_TEX, "Print texture info" },
447 { "compute", DBG_COMPUTE, "Print compute info" },
448 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
449 { "info", DBG_INFO, "Print driver information" },
450
451 /* shaders */
452 { "fs", DBG_FS, "Print fetch shaders" },
453 { "vs", DBG_VS, "Print vertex shaders" },
454 { "gs", DBG_GS, "Print geometry shaders" },
455 { "ps", DBG_PS, "Print pixel shaders" },
456 { "cs", DBG_CS, "Print compute shaders" },
457 { "tcs", DBG_TCS, "Print tessellation control shaders" },
458 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
459 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
460 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
461 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
462 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
463
464 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
465
466 /* features */
467 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
468 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
469 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
470 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
471 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
472 { "notiling", DBG_NO_TILING, "Disable tiling" },
473 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
474 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
475 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
476 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
477 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
478 { "nodcc", DBG_NO_DCC, "Disable DCC." },
479 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
480 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
481 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
482 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
483 { "noce", DBG_NO_CE, "Disable the constant engine"},
484
485 DEBUG_NAMED_VALUE_END /* must be last */
486 };
487
488 static const char* r600_get_vendor(struct pipe_screen* pscreen)
489 {
490 return "X.Org";
491 }
492
493 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
494 {
495 return "AMD";
496 }
497
498 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
499 {
500 switch (rscreen->info.family) {
501 case CHIP_R600: return "AMD R600";
502 case CHIP_RV610: return "AMD RV610";
503 case CHIP_RV630: return "AMD RV630";
504 case CHIP_RV670: return "AMD RV670";
505 case CHIP_RV620: return "AMD RV620";
506 case CHIP_RV635: return "AMD RV635";
507 case CHIP_RS780: return "AMD RS780";
508 case CHIP_RS880: return "AMD RS880";
509 case CHIP_RV770: return "AMD RV770";
510 case CHIP_RV730: return "AMD RV730";
511 case CHIP_RV710: return "AMD RV710";
512 case CHIP_RV740: return "AMD RV740";
513 case CHIP_CEDAR: return "AMD CEDAR";
514 case CHIP_REDWOOD: return "AMD REDWOOD";
515 case CHIP_JUNIPER: return "AMD JUNIPER";
516 case CHIP_CYPRESS: return "AMD CYPRESS";
517 case CHIP_HEMLOCK: return "AMD HEMLOCK";
518 case CHIP_PALM: return "AMD PALM";
519 case CHIP_SUMO: return "AMD SUMO";
520 case CHIP_SUMO2: return "AMD SUMO2";
521 case CHIP_BARTS: return "AMD BARTS";
522 case CHIP_TURKS: return "AMD TURKS";
523 case CHIP_CAICOS: return "AMD CAICOS";
524 case CHIP_CAYMAN: return "AMD CAYMAN";
525 case CHIP_ARUBA: return "AMD ARUBA";
526 case CHIP_TAHITI: return "AMD TAHITI";
527 case CHIP_PITCAIRN: return "AMD PITCAIRN";
528 case CHIP_VERDE: return "AMD CAPE VERDE";
529 case CHIP_OLAND: return "AMD OLAND";
530 case CHIP_HAINAN: return "AMD HAINAN";
531 case CHIP_BONAIRE: return "AMD BONAIRE";
532 case CHIP_KAVERI: return "AMD KAVERI";
533 case CHIP_KABINI: return "AMD KABINI";
534 case CHIP_HAWAII: return "AMD HAWAII";
535 case CHIP_MULLINS: return "AMD MULLINS";
536 case CHIP_TONGA: return "AMD TONGA";
537 case CHIP_ICELAND: return "AMD ICELAND";
538 case CHIP_CARRIZO: return "AMD CARRIZO";
539 case CHIP_FIJI: return "AMD FIJI";
540 case CHIP_POLARIS10: return "AMD POLARIS10";
541 case CHIP_POLARIS11: return "AMD POLARIS11";
542 case CHIP_STONEY: return "AMD STONEY";
543 default: return "AMD unknown";
544 }
545 }
546
547 static const char* r600_get_name(struct pipe_screen* pscreen)
548 {
549 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
550
551 return rscreen->renderer_string;
552 }
553
554 static float r600_get_paramf(struct pipe_screen* pscreen,
555 enum pipe_capf param)
556 {
557 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
558
559 switch (param) {
560 case PIPE_CAPF_MAX_LINE_WIDTH:
561 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
562 case PIPE_CAPF_MAX_POINT_WIDTH:
563 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
564 if (rscreen->family >= CHIP_CEDAR)
565 return 16384.0f;
566 else
567 return 8192.0f;
568 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
569 return 16.0f;
570 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
571 return 16.0f;
572 case PIPE_CAPF_GUARD_BAND_LEFT:
573 case PIPE_CAPF_GUARD_BAND_TOP:
574 case PIPE_CAPF_GUARD_BAND_RIGHT:
575 case PIPE_CAPF_GUARD_BAND_BOTTOM:
576 return 0.0f;
577 }
578 return 0.0f;
579 }
580
581 static int r600_get_video_param(struct pipe_screen *screen,
582 enum pipe_video_profile profile,
583 enum pipe_video_entrypoint entrypoint,
584 enum pipe_video_cap param)
585 {
586 switch (param) {
587 case PIPE_VIDEO_CAP_SUPPORTED:
588 return vl_profile_supported(screen, profile, entrypoint);
589 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
590 return 1;
591 case PIPE_VIDEO_CAP_MAX_WIDTH:
592 case PIPE_VIDEO_CAP_MAX_HEIGHT:
593 return vl_video_buffer_max_size(screen);
594 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
595 return PIPE_FORMAT_NV12;
596 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
597 return false;
598 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
599 return false;
600 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
601 return true;
602 case PIPE_VIDEO_CAP_MAX_LEVEL:
603 return vl_level_supported(screen, profile);
604 default:
605 return 0;
606 }
607 }
608
609 const char *r600_get_llvm_processor_name(enum radeon_family family)
610 {
611 switch (family) {
612 case CHIP_R600:
613 case CHIP_RV630:
614 case CHIP_RV635:
615 case CHIP_RV670:
616 return "r600";
617 case CHIP_RV610:
618 case CHIP_RV620:
619 case CHIP_RS780:
620 case CHIP_RS880:
621 return "rs880";
622 case CHIP_RV710:
623 return "rv710";
624 case CHIP_RV730:
625 return "rv730";
626 case CHIP_RV740:
627 case CHIP_RV770:
628 return "rv770";
629 case CHIP_PALM:
630 case CHIP_CEDAR:
631 return "cedar";
632 case CHIP_SUMO:
633 case CHIP_SUMO2:
634 return "sumo";
635 case CHIP_REDWOOD:
636 return "redwood";
637 case CHIP_JUNIPER:
638 return "juniper";
639 case CHIP_HEMLOCK:
640 case CHIP_CYPRESS:
641 return "cypress";
642 case CHIP_BARTS:
643 return "barts";
644 case CHIP_TURKS:
645 return "turks";
646 case CHIP_CAICOS:
647 return "caicos";
648 case CHIP_CAYMAN:
649 case CHIP_ARUBA:
650 return "cayman";
651
652 case CHIP_TAHITI: return "tahiti";
653 case CHIP_PITCAIRN: return "pitcairn";
654 case CHIP_VERDE: return "verde";
655 case CHIP_OLAND: return "oland";
656 case CHIP_HAINAN: return "hainan";
657 case CHIP_BONAIRE: return "bonaire";
658 case CHIP_KABINI: return "kabini";
659 case CHIP_KAVERI: return "kaveri";
660 case CHIP_HAWAII: return "hawaii";
661 case CHIP_MULLINS:
662 return "mullins";
663 case CHIP_TONGA: return "tonga";
664 case CHIP_ICELAND: return "iceland";
665 case CHIP_CARRIZO: return "carrizo";
666 #if HAVE_LLVM <= 0x0307
667 case CHIP_FIJI: return "tonga";
668 case CHIP_STONEY: return "carrizo";
669 #else
670 case CHIP_FIJI: return "fiji";
671 case CHIP_STONEY: return "stoney";
672 #endif
673 #if HAVE_LLVM <= 0x0308
674 case CHIP_POLARIS10: return "tonga";
675 case CHIP_POLARIS11: return "tonga";
676 #else
677 case CHIP_POLARIS10: return "polaris10";
678 case CHIP_POLARIS11: return "polaris11";
679 #endif
680 default: return "";
681 }
682 }
683
684 static int r600_get_compute_param(struct pipe_screen *screen,
685 enum pipe_shader_ir ir_type,
686 enum pipe_compute_cap param,
687 void *ret)
688 {
689 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
690
691 //TODO: select these params by asic
692 switch (param) {
693 case PIPE_COMPUTE_CAP_IR_TARGET: {
694 const char *gpu;
695 const char *triple;
696 if (rscreen->family <= CHIP_ARUBA) {
697 triple = "r600--";
698 } else {
699 triple = "amdgcn--";
700 }
701 switch(rscreen->family) {
702 /* Clang < 3.6 is missing Hainan in its list of
703 * GPUs, so we need to use the name of a similar GPU.
704 */
705 default:
706 gpu = r600_get_llvm_processor_name(rscreen->family);
707 break;
708 }
709 if (ret) {
710 sprintf(ret, "%s-%s", gpu, triple);
711 }
712 /* +2 for dash and terminating NIL byte */
713 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
714 }
715 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
716 if (ret) {
717 uint64_t *grid_dimension = ret;
718 grid_dimension[0] = 3;
719 }
720 return 1 * sizeof(uint64_t);
721
722 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
723 if (ret) {
724 uint64_t *grid_size = ret;
725 grid_size[0] = 65535;
726 grid_size[1] = 65535;
727 grid_size[2] = 65535;
728 }
729 return 3 * sizeof(uint64_t) ;
730
731 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
732 if (ret) {
733 uint64_t *block_size = ret;
734 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
735 ir_type == PIPE_SHADER_IR_TGSI) {
736 block_size[0] = 2048;
737 block_size[1] = 2048;
738 block_size[2] = 2048;
739 } else {
740 block_size[0] = 256;
741 block_size[1] = 256;
742 block_size[2] = 256;
743 }
744 }
745 return 3 * sizeof(uint64_t);
746
747 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
748 if (ret) {
749 uint64_t *max_threads_per_block = ret;
750 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
751 ir_type == PIPE_SHADER_IR_TGSI)
752 *max_threads_per_block = 2048;
753 else
754 *max_threads_per_block = 256;
755 }
756 return sizeof(uint64_t);
757
758 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
759 if (ret) {
760 uint64_t *max_global_size = ret;
761 uint64_t max_mem_alloc_size;
762
763 r600_get_compute_param(screen, ir_type,
764 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
765 &max_mem_alloc_size);
766
767 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
768 * 1/4 of the MAX_GLOBAL_SIZE. Since the
769 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
770 * make sure we never report more than
771 * 4 * MAX_MEM_ALLOC_SIZE.
772 */
773 *max_global_size = MIN2(4 * max_mem_alloc_size,
774 rscreen->info.gart_size +
775 rscreen->info.vram_size);
776 }
777 return sizeof(uint64_t);
778
779 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
780 if (ret) {
781 uint64_t *max_local_size = ret;
782 /* Value reported by the closed source driver. */
783 *max_local_size = 32768;
784 }
785 return sizeof(uint64_t);
786
787 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
788 if (ret) {
789 uint64_t *max_input_size = ret;
790 /* Value reported by the closed source driver. */
791 *max_input_size = 1024;
792 }
793 return sizeof(uint64_t);
794
795 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
796 if (ret) {
797 uint64_t *max_mem_alloc_size = ret;
798
799 /* XXX: The limit in older kernels is 256 MB. We
800 * should add a query here for newer kernels.
801 */
802 *max_mem_alloc_size = 256 * 1024 * 1024;
803 }
804 return sizeof(uint64_t);
805
806 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
807 if (ret) {
808 uint32_t *max_clock_frequency = ret;
809 *max_clock_frequency = rscreen->info.max_shader_clock;
810 }
811 return sizeof(uint32_t);
812
813 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
814 if (ret) {
815 uint32_t *max_compute_units = ret;
816 *max_compute_units = rscreen->info.num_good_compute_units;
817 }
818 return sizeof(uint32_t);
819
820 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
821 if (ret) {
822 uint32_t *images_supported = ret;
823 *images_supported = 0;
824 }
825 return sizeof(uint32_t);
826 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
827 break; /* unused */
828 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
829 if (ret) {
830 uint32_t *subgroup_size = ret;
831 *subgroup_size = r600_wavefront_size(rscreen->family);
832 }
833 return sizeof(uint32_t);
834 }
835
836 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
837 return 0;
838 }
839
840 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
841 {
842 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
843
844 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
845 rscreen->info.clock_crystal_freq;
846 }
847
848 static void r600_fence_reference(struct pipe_screen *screen,
849 struct pipe_fence_handle **dst,
850 struct pipe_fence_handle *src)
851 {
852 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
853 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
854 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
855
856 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
857 ws->fence_reference(&(*rdst)->gfx, NULL);
858 ws->fence_reference(&(*rdst)->sdma, NULL);
859 FREE(*rdst);
860 }
861 *rdst = rsrc;
862 }
863
864 static boolean r600_fence_finish(struct pipe_screen *screen,
865 struct pipe_fence_handle *fence,
866 uint64_t timeout)
867 {
868 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
869 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
870 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
871
872 if (rfence->sdma) {
873 if (!rws->fence_wait(rws, rfence->sdma, timeout))
874 return false;
875
876 /* Recompute the timeout after waiting. */
877 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
878 int64_t time = os_time_get_nano();
879 timeout = abs_timeout > time ? abs_timeout - time : 0;
880 }
881 }
882
883 if (!rfence->gfx)
884 return true;
885
886 return rws->fence_wait(rws, rfence->gfx, timeout);
887 }
888
889 static void r600_query_memory_info(struct pipe_screen *screen,
890 struct pipe_memory_info *info)
891 {
892 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
893 struct radeon_winsys *ws = rscreen->ws;
894 unsigned vram_usage, gtt_usage;
895
896 info->total_device_memory = rscreen->info.vram_size / 1024;
897 info->total_staging_memory = rscreen->info.gart_size / 1024;
898
899 /* The real TTM memory usage is somewhat random, because:
900 *
901 * 1) TTM delays freeing memory, because it can only free it after
902 * fences expire.
903 *
904 * 2) The memory usage can be really low if big VRAM evictions are
905 * taking place, but the real usage is well above the size of VRAM.
906 *
907 * Instead, return statistics of this process.
908 */
909 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
910 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
911
912 info->avail_device_memory =
913 vram_usage <= info->total_device_memory ?
914 info->total_device_memory - vram_usage : 0;
915 info->avail_staging_memory =
916 gtt_usage <= info->total_staging_memory ?
917 info->total_staging_memory - gtt_usage : 0;
918
919 info->device_memory_evicted =
920 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
921 /* Just return the number of evicted 64KB pages. */
922 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
923 }
924
925 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
926 const struct pipe_resource *templ)
927 {
928 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
929
930 if (templ->target == PIPE_BUFFER) {
931 return r600_buffer_create(screen, templ,
932 rscreen->info.gart_page_size);
933 } else {
934 return r600_texture_create(screen, templ);
935 }
936 }
937
938 bool r600_common_screen_init(struct r600_common_screen *rscreen,
939 struct radeon_winsys *ws)
940 {
941 char llvm_string[32] = {};
942
943 ws->query_info(ws, &rscreen->info);
944
945 #if HAVE_LLVM
946 snprintf(llvm_string, sizeof(llvm_string),
947 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
948 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
949 #endif
950
951 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
952 "%s (DRM %i.%i.%i%s)",
953 r600_get_chip_name(rscreen), rscreen->info.drm_major,
954 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
955 llvm_string);
956
957 rscreen->b.get_name = r600_get_name;
958 rscreen->b.get_vendor = r600_get_vendor;
959 rscreen->b.get_device_vendor = r600_get_device_vendor;
960 rscreen->b.get_compute_param = r600_get_compute_param;
961 rscreen->b.get_paramf = r600_get_paramf;
962 rscreen->b.get_timestamp = r600_get_timestamp;
963 rscreen->b.fence_finish = r600_fence_finish;
964 rscreen->b.fence_reference = r600_fence_reference;
965 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
966 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
967 rscreen->b.query_memory_info = r600_query_memory_info;
968
969 if (rscreen->info.has_uvd) {
970 rscreen->b.get_video_param = rvid_get_video_param;
971 rscreen->b.is_video_format_supported = rvid_is_format_supported;
972 } else {
973 rscreen->b.get_video_param = r600_get_video_param;
974 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
975 }
976
977 r600_init_screen_texture_functions(rscreen);
978 r600_init_screen_query_functions(rscreen);
979
980 rscreen->ws = ws;
981 rscreen->family = rscreen->info.family;
982 rscreen->chip_class = rscreen->info.chip_class;
983 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
984
985 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
986 if (rscreen->force_aniso >= 0) {
987 printf("radeon: Forcing anisotropy filter to %ix\n",
988 /* round down to a power of two */
989 1 << util_logbase2(rscreen->force_aniso));
990 }
991
992 util_format_s3tc_init();
993 pipe_mutex_init(rscreen->aux_context_lock);
994 pipe_mutex_init(rscreen->gpu_load_mutex);
995
996 if (rscreen->debug_flags & DBG_INFO) {
997 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
998 printf("family = %i (%s)\n", rscreen->info.family,
999 r600_get_chip_name(rscreen));
1000 printf("chip_class = %i\n", rscreen->info.chip_class);
1001 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1002 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1003 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1004 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1005 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1006 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1007 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1008 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1009 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1010 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1011 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1012 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1013
1014 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1015 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1016 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1017 printf("max_se = %i\n", rscreen->info.max_se);
1018 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1019
1020 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1021 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1022 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1023 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1024 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1025 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1026 }
1027 return true;
1028 }
1029
1030 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1031 {
1032 r600_perfcounters_destroy(rscreen);
1033 r600_gpu_load_kill_thread(rscreen);
1034
1035 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1036 pipe_mutex_destroy(rscreen->aux_context_lock);
1037 rscreen->aux_context->destroy(rscreen->aux_context);
1038
1039 rscreen->ws->destroy(rscreen->ws);
1040 FREE(rscreen);
1041 }
1042
1043 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1044 unsigned processor)
1045 {
1046 switch (processor) {
1047 case PIPE_SHADER_VERTEX:
1048 return (rscreen->debug_flags & DBG_VS) != 0;
1049 case PIPE_SHADER_TESS_CTRL:
1050 return (rscreen->debug_flags & DBG_TCS) != 0;
1051 case PIPE_SHADER_TESS_EVAL:
1052 return (rscreen->debug_flags & DBG_TES) != 0;
1053 case PIPE_SHADER_GEOMETRY:
1054 return (rscreen->debug_flags & DBG_GS) != 0;
1055 case PIPE_SHADER_FRAGMENT:
1056 return (rscreen->debug_flags & DBG_PS) != 0;
1057 case PIPE_SHADER_COMPUTE:
1058 return (rscreen->debug_flags & DBG_CS) != 0;
1059 default:
1060 return false;
1061 }
1062 }
1063
1064 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1065 uint64_t offset, uint64_t size, unsigned value,
1066 enum r600_coherency coher)
1067 {
1068 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1069
1070 pipe_mutex_lock(rscreen->aux_context_lock);
1071 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1072 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1073 pipe_mutex_unlock(rscreen->aux_context_lock);
1074 }