2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
45 struct r600_multi_fence
{
46 struct pipe_reference reference
;
47 struct pipe_fence_handle
*gfx
;
48 struct pipe_fence_handle
*sdma
;
55 void r600_draw_rectangle(struct blitter_context
*blitter
,
56 int x1
, int y1
, int x2
, int y2
, float depth
,
57 enum blitter_attrib_type type
,
58 const union pipe_color_union
*attrib
)
60 struct r600_common_context
*rctx
=
61 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
62 struct pipe_viewport_state viewport
;
63 struct pipe_resource
*buf
= NULL
;
67 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
68 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
72 /* Some operations (like color resolve on r6xx) don't work
73 * with the conventional primitive types.
74 * One that works is PT_RECTLIST, which we use here. */
77 viewport
.scale
[0] = 1.0f
;
78 viewport
.scale
[1] = 1.0f
;
79 viewport
.scale
[2] = 1.0f
;
80 viewport
.translate
[0] = 0.0f
;
81 viewport
.translate
[1] = 0.0f
;
82 viewport
.translate
[2] = 0.0f
;
83 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
85 /* Upload vertices. The hw rectangle has only 3 vertices,
86 * I guess the 4th one is derived from the first 3.
87 * The vertex specification should match u_blitter's vertex element state. */
88 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
108 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
109 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
110 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
114 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
115 R600_PRIM_RECTANGLE_LIST
, 3, 2);
116 pipe_resource_reference(&buf
, NULL
);
119 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
)
121 /* Flush the GFX IB if it's not empty. */
122 if (ctx
->gfx
.cs
->cdw
> ctx
->initial_gfx_cs_size
)
123 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
125 /* Flush if there's not enough space. */
126 if ((num_dw
+ ctx
->dma
.cs
->cdw
) > ctx
->dma
.cs
->max_dw
) {
127 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
128 assert((num_dw
+ ctx
->dma
.cs
->cdw
) <= ctx
->dma
.cs
->max_dw
);
132 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
136 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
138 /* suspend queries */
139 if (ctx
->num_cs_dw_nontimer_queries_suspend
) {
140 /* Since non-timer queries are suspended during blits,
141 * we have to guard against double-suspends. */
142 r600_suspend_nontimer_queries(ctx
);
143 ctx
->nontimer_queries_suspended_by_flush
= true;
145 if (!LIST_IS_EMPTY(&ctx
->active_timer_queries
))
146 r600_suspend_timer_queries(ctx
);
148 ctx
->streamout
.suspended
= false;
149 if (ctx
->streamout
.begin_emitted
) {
150 r600_emit_streamout_end(ctx
);
151 ctx
->streamout
.suspended
= true;
155 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
157 if (ctx
->streamout
.suspended
) {
158 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
159 r600_streamout_buffers_dirty(ctx
);
163 if (!LIST_IS_EMPTY(&ctx
->active_timer_queries
))
164 r600_resume_timer_queries(ctx
);
165 if (ctx
->nontimer_queries_suspended_by_flush
) {
166 ctx
->nontimer_queries_suspended_by_flush
= false;
167 r600_resume_nontimer_queries(ctx
);
171 static void r600_flush_from_st(struct pipe_context
*ctx
,
172 struct pipe_fence_handle
**fence
,
175 struct pipe_screen
*screen
= ctx
->screen
;
176 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
178 struct pipe_fence_handle
*gfx_fence
= NULL
;
179 struct pipe_fence_handle
*sdma_fence
= NULL
;
181 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
182 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
185 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
187 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
189 /* Both engines can signal out of order, so we need to keep both fences. */
190 if (gfx_fence
|| sdma_fence
) {
191 struct r600_multi_fence
*multi_fence
=
192 CALLOC_STRUCT(r600_multi_fence
);
196 multi_fence
->reference
.count
= 1;
197 multi_fence
->gfx
= gfx_fence
;
198 multi_fence
->sdma
= sdma_fence
;
200 screen
->fence_reference(screen
, fence
, NULL
);
201 *fence
= (struct pipe_fence_handle
*)multi_fence
;
205 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
206 struct pipe_fence_handle
**fence
)
208 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
209 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
212 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
, 0);
214 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
217 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
219 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
220 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
221 RADEON_GPU_RESET_COUNTER
);
223 if (rctx
->gpu_reset_counter
== latest
)
224 return PIPE_NO_RESET
;
226 rctx
->gpu_reset_counter
= latest
;
227 return PIPE_UNKNOWN_CONTEXT_RESET
;
230 bool r600_common_context_init(struct r600_common_context
*rctx
,
231 struct r600_common_screen
*rscreen
)
233 util_slab_create(&rctx
->pool_transfers
,
234 sizeof(struct r600_transfer
), 64,
235 UTIL_SLAB_SINGLETHREADED
);
237 rctx
->screen
= rscreen
;
238 rctx
->ws
= rscreen
->ws
;
239 rctx
->family
= rscreen
->family
;
240 rctx
->chip_class
= rscreen
->chip_class
;
242 if (rscreen
->family
== CHIP_HAWAII
)
244 else if (rscreen
->chip_class
>= EVERGREEN
)
249 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
250 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
251 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
252 rctx
->b
.transfer_inline_write
= u_default_transfer_inline_write
;
253 rctx
->b
.memory_barrier
= r600_memory_barrier
;
254 rctx
->b
.flush
= r600_flush_from_st
;
256 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
257 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
258 rctx
->gpu_reset_counter
=
259 rctx
->ws
->query_value(rctx
->ws
,
260 RADEON_GPU_RESET_COUNTER
);
263 LIST_INITHEAD(&rctx
->texture_buffers
);
265 r600_init_context_texture_functions(rctx
);
266 r600_streamout_init(rctx
);
267 r600_query_init(rctx
);
268 cayman_init_msaa(&rctx
->b
);
270 rctx
->allocator_so_filled_size
= u_suballocator_create(&rctx
->b
, 4096, 4,
271 0, PIPE_USAGE_DEFAULT
, TRUE
);
272 if (!rctx
->allocator_so_filled_size
)
275 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024, 256,
276 PIPE_BIND_INDEX_BUFFER
|
277 PIPE_BIND_CONSTANT_BUFFER
);
281 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
285 if (rscreen
->info
.r600_has_dma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
286 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
289 rctx
->dma
.flush
= r600_flush_dma_ring
;
295 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
298 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
300 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
302 rctx
->ws
->ctx_destroy(rctx
->ctx
);
304 if (rctx
->uploader
) {
305 u_upload_destroy(rctx
->uploader
);
308 util_slab_destroy(&rctx
->pool_transfers
);
310 if (rctx
->allocator_so_filled_size
) {
311 u_suballocator_destroy(rctx
->allocator_so_filled_size
);
313 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
316 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
318 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
319 struct r600_resource
*rr
= (struct r600_resource
*)r
;
326 * The idea is to compute a gross estimate of memory requirement of
327 * each draw call. After each draw call, memory will be precisely
328 * accounted. So the uncertainty is only on the current draw call.
329 * In practice this gave very good estimate (+/- 10% of the target
332 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
333 rctx
->gtt
+= rr
->buf
->size
;
335 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
336 rctx
->vram
+= rr
->buf
->size
;
344 static const struct debug_named_value common_debug_options
[] = {
346 { "tex", DBG_TEX
, "Print texture info" },
347 { "texmip", DBG_TEXMIP
, "Print texture info (mipmapped only)" },
348 { "compute", DBG_COMPUTE
, "Print compute info" },
349 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
350 { "trace_cs", DBG_TRACE_CS
, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
351 { "info", DBG_INFO
, "Print driver information" },
354 { "fs", DBG_FS
, "Print fetch shaders" },
355 { "vs", DBG_VS
, "Print vertex shaders" },
356 { "gs", DBG_GS
, "Print geometry shaders" },
357 { "ps", DBG_PS
, "Print pixel shaders" },
358 { "cs", DBG_CS
, "Print compute shaders" },
359 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
360 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
361 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
362 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
363 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
366 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
367 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
368 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
369 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
370 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
371 { "notiling", DBG_NO_TILING
, "Disable tiling" },
372 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
373 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
374 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
375 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
376 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
377 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
378 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
380 DEBUG_NAMED_VALUE_END
/* must be last */
383 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
388 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
393 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
395 switch (rscreen
->info
.family
) {
396 case CHIP_R600
: return "AMD R600";
397 case CHIP_RV610
: return "AMD RV610";
398 case CHIP_RV630
: return "AMD RV630";
399 case CHIP_RV670
: return "AMD RV670";
400 case CHIP_RV620
: return "AMD RV620";
401 case CHIP_RV635
: return "AMD RV635";
402 case CHIP_RS780
: return "AMD RS780";
403 case CHIP_RS880
: return "AMD RS880";
404 case CHIP_RV770
: return "AMD RV770";
405 case CHIP_RV730
: return "AMD RV730";
406 case CHIP_RV710
: return "AMD RV710";
407 case CHIP_RV740
: return "AMD RV740";
408 case CHIP_CEDAR
: return "AMD CEDAR";
409 case CHIP_REDWOOD
: return "AMD REDWOOD";
410 case CHIP_JUNIPER
: return "AMD JUNIPER";
411 case CHIP_CYPRESS
: return "AMD CYPRESS";
412 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
413 case CHIP_PALM
: return "AMD PALM";
414 case CHIP_SUMO
: return "AMD SUMO";
415 case CHIP_SUMO2
: return "AMD SUMO2";
416 case CHIP_BARTS
: return "AMD BARTS";
417 case CHIP_TURKS
: return "AMD TURKS";
418 case CHIP_CAICOS
: return "AMD CAICOS";
419 case CHIP_CAYMAN
: return "AMD CAYMAN";
420 case CHIP_ARUBA
: return "AMD ARUBA";
421 case CHIP_TAHITI
: return "AMD TAHITI";
422 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
423 case CHIP_VERDE
: return "AMD CAPE VERDE";
424 case CHIP_OLAND
: return "AMD OLAND";
425 case CHIP_HAINAN
: return "AMD HAINAN";
426 case CHIP_BONAIRE
: return "AMD BONAIRE";
427 case CHIP_KAVERI
: return "AMD KAVERI";
428 case CHIP_KABINI
: return "AMD KABINI";
429 case CHIP_HAWAII
: return "AMD HAWAII";
430 case CHIP_MULLINS
: return "AMD MULLINS";
431 case CHIP_TONGA
: return "AMD TONGA";
432 case CHIP_ICELAND
: return "AMD ICELAND";
433 case CHIP_CARRIZO
: return "AMD CARRIZO";
434 case CHIP_FIJI
: return "AMD FIJI";
435 case CHIP_STONEY
: return "AMD STONEY";
436 default: return "AMD unknown";
440 static const char* r600_get_name(struct pipe_screen
* pscreen
)
442 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
444 return rscreen
->renderer_string
;
447 static float r600_get_paramf(struct pipe_screen
* pscreen
,
448 enum pipe_capf param
)
450 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
453 case PIPE_CAPF_MAX_LINE_WIDTH
:
454 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
455 case PIPE_CAPF_MAX_POINT_WIDTH
:
456 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
457 if (rscreen
->family
>= CHIP_CEDAR
)
461 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
463 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
465 case PIPE_CAPF_GUARD_BAND_LEFT
:
466 case PIPE_CAPF_GUARD_BAND_TOP
:
467 case PIPE_CAPF_GUARD_BAND_RIGHT
:
468 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
474 static int r600_get_video_param(struct pipe_screen
*screen
,
475 enum pipe_video_profile profile
,
476 enum pipe_video_entrypoint entrypoint
,
477 enum pipe_video_cap param
)
480 case PIPE_VIDEO_CAP_SUPPORTED
:
481 return vl_profile_supported(screen
, profile
, entrypoint
);
482 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
484 case PIPE_VIDEO_CAP_MAX_WIDTH
:
485 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
486 return vl_video_buffer_max_size(screen
);
487 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
488 return PIPE_FORMAT_NV12
;
489 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
491 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
493 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
495 case PIPE_VIDEO_CAP_MAX_LEVEL
:
496 return vl_level_supported(screen
, profile
);
502 const char *r600_get_llvm_processor_name(enum radeon_family family
)
545 case CHIP_TAHITI
: return "tahiti";
546 case CHIP_PITCAIRN
: return "pitcairn";
547 case CHIP_VERDE
: return "verde";
548 case CHIP_OLAND
: return "oland";
549 case CHIP_HAINAN
: return "hainan";
550 case CHIP_BONAIRE
: return "bonaire";
551 case CHIP_KABINI
: return "kabini";
552 case CHIP_KAVERI
: return "kaveri";
553 case CHIP_HAWAII
: return "hawaii";
556 case CHIP_TONGA
: return "tonga";
557 case CHIP_ICELAND
: return "iceland";
558 case CHIP_CARRIZO
: return "carrizo";
559 case CHIP_FIJI
: return "fiji";
560 #if HAVE_LLVM <= 0x0307
561 case CHIP_STONEY
: return "carrizo";
563 case CHIP_STONEY
: return "stoney";
569 static int r600_get_compute_param(struct pipe_screen
*screen
,
570 enum pipe_compute_cap param
,
573 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
575 //TODO: select these params by asic
577 case PIPE_COMPUTE_CAP_IR_TARGET
: {
580 if (rscreen
->family
<= CHIP_ARUBA
|| HAVE_LLVM
< 0x0306) {
585 switch(rscreen
->family
) {
586 /* Clang < 3.6 is missing Hainan in its list of
587 * GPUs, so we need to use the name of a similar GPU.
589 #if HAVE_LLVM < 0x0306
595 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
599 sprintf(ret
, "%s-%s", gpu
, triple
);
601 /* +2 for dash and terminating NIL byte */
602 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
604 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
606 uint64_t *grid_dimension
= ret
;
607 grid_dimension
[0] = 3;
609 return 1 * sizeof(uint64_t);
611 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
613 uint64_t *grid_size
= ret
;
614 grid_size
[0] = 65535;
615 grid_size
[1] = 65535;
618 return 3 * sizeof(uint64_t) ;
620 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
622 uint64_t *block_size
= ret
;
627 return 3 * sizeof(uint64_t);
629 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
631 uint64_t *max_threads_per_block
= ret
;
632 *max_threads_per_block
= 256;
634 return sizeof(uint64_t);
636 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
638 uint64_t *max_global_size
= ret
;
639 uint64_t max_mem_alloc_size
;
641 r600_get_compute_param(screen
,
642 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
643 &max_mem_alloc_size
);
645 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
646 * 1/4 of the MAX_GLOBAL_SIZE. Since the
647 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
648 * make sure we never report more than
649 * 4 * MAX_MEM_ALLOC_SIZE.
651 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
652 rscreen
->info
.gart_size
+
653 rscreen
->info
.vram_size
);
655 return sizeof(uint64_t);
657 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
659 uint64_t *max_local_size
= ret
;
660 /* Value reported by the closed source driver. */
661 *max_local_size
= 32768;
663 return sizeof(uint64_t);
665 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
667 uint64_t *max_input_size
= ret
;
668 /* Value reported by the closed source driver. */
669 *max_input_size
= 1024;
671 return sizeof(uint64_t);
673 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
675 uint64_t *max_mem_alloc_size
= ret
;
677 /* XXX: The limit in older kernels is 256 MB. We
678 * should add a query here for newer kernels.
680 *max_mem_alloc_size
= 256 * 1024 * 1024;
682 return sizeof(uint64_t);
684 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
686 uint32_t *max_clock_frequency
= ret
;
687 *max_clock_frequency
= rscreen
->info
.max_sclk
;
689 return sizeof(uint32_t);
691 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
693 uint32_t *max_compute_units
= ret
;
694 *max_compute_units
= rscreen
->info
.max_compute_units
;
696 return sizeof(uint32_t);
698 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
700 uint32_t *images_supported
= ret
;
701 *images_supported
= 0;
703 return sizeof(uint32_t);
704 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
706 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
708 uint32_t *subgroup_size
= ret
;
709 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
711 return sizeof(uint32_t);
714 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
718 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
720 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
722 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
723 rscreen
->info
.r600_clock_crystal_freq
;
726 static void r600_fence_reference(struct pipe_screen
*screen
,
727 struct pipe_fence_handle
**dst
,
728 struct pipe_fence_handle
*src
)
730 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
731 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
732 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
734 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
735 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
736 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
742 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
743 struct pipe_fence_handle
*fence
,
746 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
747 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
748 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
751 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
754 /* Recompute the timeout after waiting. */
755 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
756 int64_t time
= os_time_get_nano();
757 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
764 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
767 static bool r600_interpret_tiling(struct r600_common_screen
*rscreen
,
768 uint32_t tiling_config
)
770 switch ((tiling_config
& 0xe) >> 1) {
772 rscreen
->tiling_info
.num_channels
= 1;
775 rscreen
->tiling_info
.num_channels
= 2;
778 rscreen
->tiling_info
.num_channels
= 4;
781 rscreen
->tiling_info
.num_channels
= 8;
787 switch ((tiling_config
& 0x30) >> 4) {
789 rscreen
->tiling_info
.num_banks
= 4;
792 rscreen
->tiling_info
.num_banks
= 8;
798 switch ((tiling_config
& 0xc0) >> 6) {
800 rscreen
->tiling_info
.group_bytes
= 256;
803 rscreen
->tiling_info
.group_bytes
= 512;
811 static bool evergreen_interpret_tiling(struct r600_common_screen
*rscreen
,
812 uint32_t tiling_config
)
814 switch (tiling_config
& 0xf) {
816 rscreen
->tiling_info
.num_channels
= 1;
819 rscreen
->tiling_info
.num_channels
= 2;
822 rscreen
->tiling_info
.num_channels
= 4;
825 rscreen
->tiling_info
.num_channels
= 8;
831 switch ((tiling_config
& 0xf0) >> 4) {
833 rscreen
->tiling_info
.num_banks
= 4;
836 rscreen
->tiling_info
.num_banks
= 8;
839 rscreen
->tiling_info
.num_banks
= 16;
845 switch ((tiling_config
& 0xf00) >> 8) {
847 rscreen
->tiling_info
.group_bytes
= 256;
850 rscreen
->tiling_info
.group_bytes
= 512;
858 static bool r600_init_tiling(struct r600_common_screen
*rscreen
)
860 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
862 /* set default group bytes, overridden by tiling info ioctl */
863 if (rscreen
->chip_class
<= R700
) {
864 rscreen
->tiling_info
.group_bytes
= 256;
866 rscreen
->tiling_info
.group_bytes
= 512;
872 if (rscreen
->chip_class
<= R700
) {
873 return r600_interpret_tiling(rscreen
, tiling_config
);
875 return evergreen_interpret_tiling(rscreen
, tiling_config
);
879 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
880 const struct pipe_resource
*templ
)
882 if (templ
->target
== PIPE_BUFFER
) {
883 return r600_buffer_create(screen
, templ
, 4096);
885 return r600_texture_create(screen
, templ
);
889 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
890 struct radeon_winsys
*ws
)
892 char llvm_string
[32] = {};
894 ws
->query_info(ws
, &rscreen
->info
);
897 snprintf(llvm_string
, sizeof(llvm_string
),
898 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
899 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
902 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
903 "%s (DRM %i.%i.%i%s)",
904 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
905 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
908 rscreen
->b
.get_name
= r600_get_name
;
909 rscreen
->b
.get_vendor
= r600_get_vendor
;
910 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
911 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
912 rscreen
->b
.get_paramf
= r600_get_paramf
;
913 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
914 rscreen
->b
.fence_finish
= r600_fence_finish
;
915 rscreen
->b
.fence_reference
= r600_fence_reference
;
916 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
917 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
919 if (rscreen
->info
.has_uvd
) {
920 rscreen
->b
.get_video_param
= rvid_get_video_param
;
921 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
923 rscreen
->b
.get_video_param
= r600_get_video_param
;
924 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
927 r600_init_screen_texture_functions(rscreen
);
928 r600_init_screen_query_functions(rscreen
);
931 rscreen
->family
= rscreen
->info
.family
;
932 rscreen
->chip_class
= rscreen
->info
.chip_class
;
933 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
935 if (!r600_init_tiling(rscreen
)) {
938 util_format_s3tc_init();
939 pipe_mutex_init(rscreen
->aux_context_lock
);
940 pipe_mutex_init(rscreen
->gpu_load_mutex
);
942 if (((rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 28) ||
943 rscreen
->info
.drm_major
== 3) &&
944 (rscreen
->debug_flags
& DBG_TRACE_CS
)) {
945 rscreen
->trace_bo
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
,
949 if (rscreen
->trace_bo
) {
950 rscreen
->trace_ptr
= rscreen
->ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
951 PIPE_TRANSFER_UNSYNCHRONIZED
);
955 if (rscreen
->debug_flags
& DBG_INFO
) {
956 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
957 printf("family = %i\n", rscreen
->info
.family
);
958 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
959 printf("gart_size = %i MB\n", (int)(rscreen
->info
.gart_size
>> 20));
960 printf("vram_size = %i MB\n", (int)(rscreen
->info
.vram_size
>> 20));
961 printf("max_sclk = %i\n", rscreen
->info
.max_sclk
);
962 printf("max_compute_units = %i\n", rscreen
->info
.max_compute_units
);
963 printf("max_se = %i\n", rscreen
->info
.max_se
);
964 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
965 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
966 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
967 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
968 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
969 printf("r600_num_backends = %i\n", rscreen
->info
.r600_num_backends
);
970 printf("r600_clock_crystal_freq = %i\n", rscreen
->info
.r600_clock_crystal_freq
);
971 printf("r600_tiling_config = 0x%x\n", rscreen
->info
.r600_tiling_config
);
972 printf("r600_num_tile_pipes = %i\n", rscreen
->info
.r600_num_tile_pipes
);
973 printf("r600_max_pipes = %i\n", rscreen
->info
.r600_max_pipes
);
974 printf("r600_virtual_address = %i\n", rscreen
->info
.r600_virtual_address
);
975 printf("r600_has_dma = %i\n", rscreen
->info
.r600_has_dma
);
976 printf("r600_backend_map = %i\n", rscreen
->info
.r600_backend_map
);
977 printf("r600_backend_map_valid = %i\n", rscreen
->info
.r600_backend_map_valid
);
978 printf("si_tile_mode_array_valid = %i\n", rscreen
->info
.si_tile_mode_array_valid
);
979 printf("cik_macrotile_mode_array_valid = %i\n", rscreen
->info
.cik_macrotile_mode_array_valid
);
984 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
986 r600_perfcounters_destroy(rscreen
);
987 r600_gpu_load_kill_thread(rscreen
);
989 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
990 pipe_mutex_destroy(rscreen
->aux_context_lock
);
991 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
993 if (rscreen
->trace_bo
)
994 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
996 rscreen
->ws
->destroy(rscreen
->ws
);
1000 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1001 const struct tgsi_token
*tokens
)
1003 /* Compute shader don't have tgsi_tokens */
1005 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1007 switch (tgsi_get_processor_type(tokens
)) {
1008 case TGSI_PROCESSOR_VERTEX
:
1009 return (rscreen
->debug_flags
& DBG_VS
) != 0;
1010 case TGSI_PROCESSOR_TESS_CTRL
:
1011 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
1012 case TGSI_PROCESSOR_TESS_EVAL
:
1013 return (rscreen
->debug_flags
& DBG_TES
) != 0;
1014 case TGSI_PROCESSOR_GEOMETRY
:
1015 return (rscreen
->debug_flags
& DBG_GS
) != 0;
1016 case TGSI_PROCESSOR_FRAGMENT
:
1017 return (rscreen
->debug_flags
& DBG_PS
) != 0;
1018 case TGSI_PROCESSOR_COMPUTE
:
1019 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1025 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1026 unsigned offset
, unsigned size
, unsigned value
,
1027 bool is_framebuffer
)
1029 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1031 pipe_mutex_lock(rscreen
->aux_context_lock
);
1032 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, is_framebuffer
);
1033 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1034 pipe_mutex_unlock(rscreen
->aux_context_lock
);