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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= RADEON_MAX_CMDBUF_DWORDS);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->nontimer_queries_suspended = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 ctx->nontimer_queries_suspended = true;
139 }
140
141 ctx->streamout.suspended = false;
142 if (ctx->streamout.begin_emitted) {
143 r600_emit_streamout_end(ctx);
144 ctx->streamout.suspended = true;
145 }
146 }
147
148 void r600_postflush_resume_features(struct r600_common_context *ctx)
149 {
150 if (ctx->streamout.suspended) {
151 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
152 r600_streamout_buffers_dirty(ctx);
153 }
154
155 /* resume queries */
156 if (ctx->nontimer_queries_suspended) {
157 r600_resume_nontimer_queries(ctx);
158 }
159
160 /* Re-enable render condition. */
161 if (ctx->saved_render_cond) {
162 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
163 ctx->saved_render_cond_cond,
164 ctx->saved_render_cond_mode);
165 }
166 }
167
168 static void r600_flush_from_st(struct pipe_context *ctx,
169 struct pipe_fence_handle **fence,
170 unsigned flags)
171 {
172 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
173 unsigned rflags = 0;
174
175 if (flags & PIPE_FLUSH_END_OF_FRAME)
176 rflags |= RADEON_FLUSH_END_OF_FRAME;
177
178 if (rctx->rings.dma.cs) {
179 rctx->rings.dma.flush(rctx, rflags, NULL);
180 }
181 rctx->rings.gfx.flush(rctx, rflags, fence);
182 }
183
184 static void r600_flush_dma_ring(void *ctx, unsigned flags,
185 struct pipe_fence_handle **fence)
186 {
187 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
188 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
189
190 if (!cs->cdw) {
191 return;
192 }
193
194 rctx->rings.dma.flushing = true;
195 rctx->ws->cs_flush(cs, flags, fence, 0);
196 rctx->rings.dma.flushing = false;
197 }
198
199 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
200 {
201 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
202 unsigned latest = rctx->ws->query_value(rctx->ws,
203 RADEON_GPU_RESET_COUNTER);
204
205 if (rctx->gpu_reset_counter == latest)
206 return PIPE_NO_RESET;
207
208 rctx->gpu_reset_counter = latest;
209 return PIPE_UNKNOWN_CONTEXT_RESET;
210 }
211
212 bool r600_common_context_init(struct r600_common_context *rctx,
213 struct r600_common_screen *rscreen)
214 {
215 util_slab_create(&rctx->pool_transfers,
216 sizeof(struct r600_transfer), 64,
217 UTIL_SLAB_SINGLETHREADED);
218
219 rctx->screen = rscreen;
220 rctx->ws = rscreen->ws;
221 rctx->family = rscreen->family;
222 rctx->chip_class = rscreen->chip_class;
223
224 if (rscreen->family == CHIP_HAWAII)
225 rctx->max_db = 16;
226 else if (rscreen->chip_class >= EVERGREEN)
227 rctx->max_db = 8;
228 else
229 rctx->max_db = 4;
230
231 rctx->b.transfer_map = u_transfer_map_vtbl;
232 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
233 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
234 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
235 rctx->b.memory_barrier = r600_memory_barrier;
236 rctx->b.flush = r600_flush_from_st;
237
238 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
239 rctx->b.get_device_reset_status = r600_get_reset_status;
240 rctx->gpu_reset_counter =
241 rctx->ws->query_value(rctx->ws,
242 RADEON_GPU_RESET_COUNTER);
243 }
244
245 LIST_INITHEAD(&rctx->texture_buffers);
246
247 r600_init_context_texture_functions(rctx);
248 r600_streamout_init(rctx);
249 r600_query_init(rctx);
250 cayman_init_msaa(&rctx->b);
251
252 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
253 0, PIPE_USAGE_DEFAULT, TRUE);
254 if (!rctx->allocator_so_filled_size)
255 return false;
256
257 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
258 PIPE_BIND_INDEX_BUFFER |
259 PIPE_BIND_CONSTANT_BUFFER);
260 if (!rctx->uploader)
261 return false;
262
263 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
264 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
265 r600_flush_dma_ring,
266 rctx, NULL);
267 rctx->rings.dma.flush = r600_flush_dma_ring;
268 }
269
270 return true;
271 }
272
273 void r600_common_context_cleanup(struct r600_common_context *rctx)
274 {
275 if (rctx->rings.gfx.cs) {
276 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
277 }
278 if (rctx->rings.dma.cs) {
279 rctx->ws->cs_destroy(rctx->rings.dma.cs);
280 }
281
282 if (rctx->uploader) {
283 u_upload_destroy(rctx->uploader);
284 }
285
286 util_slab_destroy(&rctx->pool_transfers);
287
288 if (rctx->allocator_so_filled_size) {
289 u_suballocator_destroy(rctx->allocator_so_filled_size);
290 }
291 }
292
293 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
294 {
295 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
296 struct r600_resource *rr = (struct r600_resource *)r;
297
298 if (r == NULL) {
299 return;
300 }
301
302 /*
303 * The idea is to compute a gross estimate of memory requirement of
304 * each draw call. After each draw call, memory will be precisely
305 * accounted. So the uncertainty is only on the current draw call.
306 * In practice this gave very good estimate (+/- 10% of the target
307 * memory limit).
308 */
309 if (rr->domains & RADEON_DOMAIN_GTT) {
310 rctx->gtt += rr->buf->size;
311 }
312 if (rr->domains & RADEON_DOMAIN_VRAM) {
313 rctx->vram += rr->buf->size;
314 }
315 }
316
317 /*
318 * pipe_screen
319 */
320
321 static const struct debug_named_value common_debug_options[] = {
322 /* logging */
323 { "tex", DBG_TEX, "Print texture info" },
324 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
325 { "compute", DBG_COMPUTE, "Print compute info" },
326 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
327 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
328 { "info", DBG_INFO, "Print driver information" },
329
330 /* shaders */
331 { "fs", DBG_FS, "Print fetch shaders" },
332 { "vs", DBG_VS, "Print vertex shaders" },
333 { "gs", DBG_GS, "Print geometry shaders" },
334 { "ps", DBG_PS, "Print pixel shaders" },
335 { "cs", DBG_CS, "Print compute shaders" },
336 { "tcs", DBG_TCS, "Print tessellation control shaders" },
337 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
338 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
339
340 /* features */
341 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
342 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
343 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
344 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
345 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
346 { "notiling", DBG_NO_TILING, "Disable tiling" },
347 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
348 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
349 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
350
351 DEBUG_NAMED_VALUE_END /* must be last */
352 };
353
354 static const char* r600_get_vendor(struct pipe_screen* pscreen)
355 {
356 return "X.Org";
357 }
358
359 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
360 {
361 return "AMD";
362 }
363
364 static const char* r600_get_name(struct pipe_screen* pscreen)
365 {
366 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
367
368 switch (rscreen->family) {
369 case CHIP_R600: return "AMD R600";
370 case CHIP_RV610: return "AMD RV610";
371 case CHIP_RV630: return "AMD RV630";
372 case CHIP_RV670: return "AMD RV670";
373 case CHIP_RV620: return "AMD RV620";
374 case CHIP_RV635: return "AMD RV635";
375 case CHIP_RS780: return "AMD RS780";
376 case CHIP_RS880: return "AMD RS880";
377 case CHIP_RV770: return "AMD RV770";
378 case CHIP_RV730: return "AMD RV730";
379 case CHIP_RV710: return "AMD RV710";
380 case CHIP_RV740: return "AMD RV740";
381 case CHIP_CEDAR: return "AMD CEDAR";
382 case CHIP_REDWOOD: return "AMD REDWOOD";
383 case CHIP_JUNIPER: return "AMD JUNIPER";
384 case CHIP_CYPRESS: return "AMD CYPRESS";
385 case CHIP_HEMLOCK: return "AMD HEMLOCK";
386 case CHIP_PALM: return "AMD PALM";
387 case CHIP_SUMO: return "AMD SUMO";
388 case CHIP_SUMO2: return "AMD SUMO2";
389 case CHIP_BARTS: return "AMD BARTS";
390 case CHIP_TURKS: return "AMD TURKS";
391 case CHIP_CAICOS: return "AMD CAICOS";
392 case CHIP_CAYMAN: return "AMD CAYMAN";
393 case CHIP_ARUBA: return "AMD ARUBA";
394 case CHIP_TAHITI: return "AMD TAHITI";
395 case CHIP_PITCAIRN: return "AMD PITCAIRN";
396 case CHIP_VERDE: return "AMD CAPE VERDE";
397 case CHIP_OLAND: return "AMD OLAND";
398 case CHIP_HAINAN: return "AMD HAINAN";
399 case CHIP_BONAIRE: return "AMD BONAIRE";
400 case CHIP_KAVERI: return "AMD KAVERI";
401 case CHIP_KABINI: return "AMD KABINI";
402 case CHIP_HAWAII: return "AMD HAWAII";
403 case CHIP_MULLINS: return "AMD MULLINS";
404 default: return "AMD unknown";
405 }
406 }
407
408 static float r600_get_paramf(struct pipe_screen* pscreen,
409 enum pipe_capf param)
410 {
411 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
412
413 switch (param) {
414 case PIPE_CAPF_MAX_LINE_WIDTH:
415 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
416 case PIPE_CAPF_MAX_POINT_WIDTH:
417 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
418 if (rscreen->family >= CHIP_CEDAR)
419 return 16384.0f;
420 else
421 return 8192.0f;
422 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
423 return 16.0f;
424 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
425 return 16.0f;
426 case PIPE_CAPF_GUARD_BAND_LEFT:
427 case PIPE_CAPF_GUARD_BAND_TOP:
428 case PIPE_CAPF_GUARD_BAND_RIGHT:
429 case PIPE_CAPF_GUARD_BAND_BOTTOM:
430 return 0.0f;
431 }
432 return 0.0f;
433 }
434
435 static int r600_get_video_param(struct pipe_screen *screen,
436 enum pipe_video_profile profile,
437 enum pipe_video_entrypoint entrypoint,
438 enum pipe_video_cap param)
439 {
440 switch (param) {
441 case PIPE_VIDEO_CAP_SUPPORTED:
442 return vl_profile_supported(screen, profile, entrypoint);
443 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
444 return 1;
445 case PIPE_VIDEO_CAP_MAX_WIDTH:
446 case PIPE_VIDEO_CAP_MAX_HEIGHT:
447 return vl_video_buffer_max_size(screen);
448 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
449 return PIPE_FORMAT_NV12;
450 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
451 return false;
452 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
453 return false;
454 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
455 return true;
456 case PIPE_VIDEO_CAP_MAX_LEVEL:
457 return vl_level_supported(screen, profile);
458 default:
459 return 0;
460 }
461 }
462
463 const char *r600_get_llvm_processor_name(enum radeon_family family)
464 {
465 switch (family) {
466 case CHIP_R600:
467 case CHIP_RV630:
468 case CHIP_RV635:
469 case CHIP_RV670:
470 return "r600";
471 case CHIP_RV610:
472 case CHIP_RV620:
473 case CHIP_RS780:
474 case CHIP_RS880:
475 return "rs880";
476 case CHIP_RV710:
477 return "rv710";
478 case CHIP_RV730:
479 return "rv730";
480 case CHIP_RV740:
481 case CHIP_RV770:
482 return "rv770";
483 case CHIP_PALM:
484 case CHIP_CEDAR:
485 return "cedar";
486 case CHIP_SUMO:
487 case CHIP_SUMO2:
488 return "sumo";
489 case CHIP_REDWOOD:
490 return "redwood";
491 case CHIP_JUNIPER:
492 return "juniper";
493 case CHIP_HEMLOCK:
494 case CHIP_CYPRESS:
495 return "cypress";
496 case CHIP_BARTS:
497 return "barts";
498 case CHIP_TURKS:
499 return "turks";
500 case CHIP_CAICOS:
501 return "caicos";
502 case CHIP_CAYMAN:
503 case CHIP_ARUBA:
504 return "cayman";
505
506 case CHIP_TAHITI: return "tahiti";
507 case CHIP_PITCAIRN: return "pitcairn";
508 case CHIP_VERDE: return "verde";
509 case CHIP_OLAND: return "oland";
510 case CHIP_HAINAN: return "hainan";
511 case CHIP_BONAIRE: return "bonaire";
512 case CHIP_KABINI: return "kabini";
513 case CHIP_KAVERI: return "kaveri";
514 case CHIP_HAWAII: return "hawaii";
515 case CHIP_MULLINS:
516 #if HAVE_LLVM >= 0x0305
517 return "mullins";
518 #else
519 return "kabini";
520 #endif
521 default: return "";
522 }
523 }
524
525 static int r600_get_compute_param(struct pipe_screen *screen,
526 enum pipe_compute_cap param,
527 void *ret)
528 {
529 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
530
531 //TODO: select these params by asic
532 switch (param) {
533 case PIPE_COMPUTE_CAP_IR_TARGET: {
534 const char *gpu;
535 const char *triple;
536 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
537 triple = "r600--";
538 } else {
539 triple = "amdgcn--";
540 }
541 switch(rscreen->family) {
542 /* Clang < 3.6 is missing Hainan in its list of
543 * GPUs, so we need to use the name of a similar GPU.
544 */
545 #if HAVE_LLVM < 0x0306
546 case CHIP_HAINAN:
547 gpu = "oland";
548 break;
549 #endif
550 default:
551 gpu = r600_get_llvm_processor_name(rscreen->family);
552 break;
553 }
554 if (ret) {
555 sprintf(ret, "%s-%s", gpu, triple);
556 }
557 /* +2 for dash and terminating NIL byte */
558 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
559 }
560 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
561 if (ret) {
562 uint64_t *grid_dimension = ret;
563 grid_dimension[0] = 3;
564 }
565 return 1 * sizeof(uint64_t);
566
567 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
568 if (ret) {
569 uint64_t *grid_size = ret;
570 grid_size[0] = 65535;
571 grid_size[1] = 65535;
572 grid_size[2] = 1;
573 }
574 return 3 * sizeof(uint64_t) ;
575
576 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
577 if (ret) {
578 uint64_t *block_size = ret;
579 block_size[0] = 256;
580 block_size[1] = 256;
581 block_size[2] = 256;
582 }
583 return 3 * sizeof(uint64_t);
584
585 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
586 if (ret) {
587 uint64_t *max_threads_per_block = ret;
588 *max_threads_per_block = 256;
589 }
590 return sizeof(uint64_t);
591
592 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
593 if (ret) {
594 uint64_t *max_global_size = ret;
595 uint64_t max_mem_alloc_size;
596
597 r600_get_compute_param(screen,
598 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
599 &max_mem_alloc_size);
600
601 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
602 * 1/4 of the MAX_GLOBAL_SIZE. Since the
603 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
604 * make sure we never report more than
605 * 4 * MAX_MEM_ALLOC_SIZE.
606 */
607 *max_global_size = MIN2(4 * max_mem_alloc_size,
608 rscreen->info.gart_size +
609 rscreen->info.vram_size);
610 }
611 return sizeof(uint64_t);
612
613 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
614 if (ret) {
615 uint64_t *max_local_size = ret;
616 /* Value reported by the closed source driver. */
617 *max_local_size = 32768;
618 }
619 return sizeof(uint64_t);
620
621 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
622 if (ret) {
623 uint64_t *max_input_size = ret;
624 /* Value reported by the closed source driver. */
625 *max_input_size = 1024;
626 }
627 return sizeof(uint64_t);
628
629 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
630 if (ret) {
631 uint64_t *max_mem_alloc_size = ret;
632
633 /* XXX: The limit in older kernels is 256 MB. We
634 * should add a query here for newer kernels.
635 */
636 *max_mem_alloc_size = 256 * 1024 * 1024;
637 }
638 return sizeof(uint64_t);
639
640 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
641 if (ret) {
642 uint32_t *max_clock_frequency = ret;
643 *max_clock_frequency = rscreen->info.max_sclk;
644 }
645 return sizeof(uint32_t);
646
647 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
648 if (ret) {
649 uint32_t *max_compute_units = ret;
650 *max_compute_units = rscreen->info.max_compute_units;
651 }
652 return sizeof(uint32_t);
653
654 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
655 if (ret) {
656 uint32_t *images_supported = ret;
657 *images_supported = 0;
658 }
659 return sizeof(uint32_t);
660 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
661 break; /* unused */
662 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
663 if (ret) {
664 uint32_t *subgroup_size = ret;
665 *subgroup_size = r600_wavefront_size(rscreen->family);
666 }
667 return sizeof(uint32_t);
668 }
669
670 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
671 return 0;
672 }
673
674 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
675 {
676 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
677
678 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
679 rscreen->info.r600_clock_crystal_freq;
680 }
681
682 static int r600_get_driver_query_info(struct pipe_screen *screen,
683 unsigned index,
684 struct pipe_driver_query_info *info)
685 {
686 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
687 struct pipe_driver_query_info list[] = {
688 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
689 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
690 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
691 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}},
692 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
693 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES},
694 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
695 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
696 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
697 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}},
698 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}},
699 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
700 };
701 unsigned num_queries;
702
703 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
704 num_queries = Elements(list);
705 else
706 num_queries = 8;
707
708 if (!info)
709 return num_queries;
710
711 if (index >= num_queries)
712 return 0;
713
714 *info = list[index];
715 return 1;
716 }
717
718 static void r600_fence_reference(struct pipe_screen *screen,
719 struct pipe_fence_handle **ptr,
720 struct pipe_fence_handle *fence)
721 {
722 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
723
724 rws->fence_reference(ptr, fence);
725 }
726
727 static boolean r600_fence_finish(struct pipe_screen *screen,
728 struct pipe_fence_handle *fence,
729 uint64_t timeout)
730 {
731 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
732
733 return rws->fence_wait(rws, fence, timeout);
734 }
735
736 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
737 uint32_t tiling_config)
738 {
739 switch ((tiling_config & 0xe) >> 1) {
740 case 0:
741 rscreen->tiling_info.num_channels = 1;
742 break;
743 case 1:
744 rscreen->tiling_info.num_channels = 2;
745 break;
746 case 2:
747 rscreen->tiling_info.num_channels = 4;
748 break;
749 case 3:
750 rscreen->tiling_info.num_channels = 8;
751 break;
752 default:
753 return false;
754 }
755
756 switch ((tiling_config & 0x30) >> 4) {
757 case 0:
758 rscreen->tiling_info.num_banks = 4;
759 break;
760 case 1:
761 rscreen->tiling_info.num_banks = 8;
762 break;
763 default:
764 return false;
765
766 }
767 switch ((tiling_config & 0xc0) >> 6) {
768 case 0:
769 rscreen->tiling_info.group_bytes = 256;
770 break;
771 case 1:
772 rscreen->tiling_info.group_bytes = 512;
773 break;
774 default:
775 return false;
776 }
777 return true;
778 }
779
780 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
781 uint32_t tiling_config)
782 {
783 switch (tiling_config & 0xf) {
784 case 0:
785 rscreen->tiling_info.num_channels = 1;
786 break;
787 case 1:
788 rscreen->tiling_info.num_channels = 2;
789 break;
790 case 2:
791 rscreen->tiling_info.num_channels = 4;
792 break;
793 case 3:
794 rscreen->tiling_info.num_channels = 8;
795 break;
796 default:
797 return false;
798 }
799
800 switch ((tiling_config & 0xf0) >> 4) {
801 case 0:
802 rscreen->tiling_info.num_banks = 4;
803 break;
804 case 1:
805 rscreen->tiling_info.num_banks = 8;
806 break;
807 case 2:
808 rscreen->tiling_info.num_banks = 16;
809 break;
810 default:
811 return false;
812 }
813
814 switch ((tiling_config & 0xf00) >> 8) {
815 case 0:
816 rscreen->tiling_info.group_bytes = 256;
817 break;
818 case 1:
819 rscreen->tiling_info.group_bytes = 512;
820 break;
821 default:
822 return false;
823 }
824 return true;
825 }
826
827 static bool r600_init_tiling(struct r600_common_screen *rscreen)
828 {
829 uint32_t tiling_config = rscreen->info.r600_tiling_config;
830
831 /* set default group bytes, overridden by tiling info ioctl */
832 if (rscreen->chip_class <= R700) {
833 rscreen->tiling_info.group_bytes = 256;
834 } else {
835 rscreen->tiling_info.group_bytes = 512;
836 }
837
838 if (!tiling_config)
839 return true;
840
841 if (rscreen->chip_class <= R700) {
842 return r600_interpret_tiling(rscreen, tiling_config);
843 } else {
844 return evergreen_interpret_tiling(rscreen, tiling_config);
845 }
846 }
847
848 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
849 const struct pipe_resource *templ)
850 {
851 if (templ->target == PIPE_BUFFER) {
852 return r600_buffer_create(screen, templ, 4096);
853 } else {
854 return r600_texture_create(screen, templ);
855 }
856 }
857
858 bool r600_common_screen_init(struct r600_common_screen *rscreen,
859 struct radeon_winsys *ws)
860 {
861 ws->query_info(ws, &rscreen->info);
862
863 rscreen->b.get_name = r600_get_name;
864 rscreen->b.get_vendor = r600_get_vendor;
865 rscreen->b.get_device_vendor = r600_get_device_vendor;
866 rscreen->b.get_compute_param = r600_get_compute_param;
867 rscreen->b.get_paramf = r600_get_paramf;
868 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
869 rscreen->b.get_timestamp = r600_get_timestamp;
870 rscreen->b.fence_finish = r600_fence_finish;
871 rscreen->b.fence_reference = r600_fence_reference;
872 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
873 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
874
875 if (rscreen->info.has_uvd) {
876 rscreen->b.get_video_param = rvid_get_video_param;
877 rscreen->b.is_video_format_supported = rvid_is_format_supported;
878 } else {
879 rscreen->b.get_video_param = r600_get_video_param;
880 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
881 }
882
883 r600_init_screen_texture_functions(rscreen);
884
885 rscreen->ws = ws;
886 rscreen->family = rscreen->info.family;
887 rscreen->chip_class = rscreen->info.chip_class;
888 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
889
890 if (!r600_init_tiling(rscreen)) {
891 return false;
892 }
893 util_format_s3tc_init();
894 pipe_mutex_init(rscreen->aux_context_lock);
895 pipe_mutex_init(rscreen->gpu_load_mutex);
896
897 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
898 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
899 PIPE_BIND_CUSTOM,
900 PIPE_USAGE_STAGING,
901 4096);
902 if (rscreen->trace_bo) {
903 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
904 PIPE_TRANSFER_UNSYNCHRONIZED);
905 }
906 }
907
908 if (rscreen->debug_flags & DBG_INFO) {
909 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
910 printf("family = %i\n", rscreen->info.family);
911 printf("chip_class = %i\n", rscreen->info.chip_class);
912 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
913 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
914 printf("max_sclk = %i\n", rscreen->info.max_sclk);
915 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
916 printf("max_se = %i\n", rscreen->info.max_se);
917 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
918 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
919 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
920 printf("has_uvd = %i\n", rscreen->info.has_uvd);
921 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
922 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
923 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
924 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
925 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
926 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
927 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
928 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
929 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
930 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
931 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
932 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
933 }
934 return true;
935 }
936
937 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
938 {
939 r600_gpu_load_kill_thread(rscreen);
940
941 pipe_mutex_destroy(rscreen->gpu_load_mutex);
942 pipe_mutex_destroy(rscreen->aux_context_lock);
943 rscreen->aux_context->destroy(rscreen->aux_context);
944
945 if (rscreen->trace_bo)
946 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
947
948 rscreen->ws->destroy(rscreen->ws);
949 FREE(rscreen);
950 }
951
952 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
953 const struct tgsi_token *tokens)
954 {
955 /* Compute shader don't have tgsi_tokens */
956 if (!tokens)
957 return (rscreen->debug_flags & DBG_CS) != 0;
958
959 switch (tgsi_get_processor_type(tokens)) {
960 case TGSI_PROCESSOR_VERTEX:
961 return (rscreen->debug_flags & DBG_VS) != 0;
962 case TGSI_PROCESSOR_TESS_CTRL:
963 return (rscreen->debug_flags & DBG_TCS) != 0;
964 case TGSI_PROCESSOR_TESS_EVAL:
965 return (rscreen->debug_flags & DBG_TES) != 0;
966 case TGSI_PROCESSOR_GEOMETRY:
967 return (rscreen->debug_flags & DBG_GS) != 0;
968 case TGSI_PROCESSOR_FRAGMENT:
969 return (rscreen->debug_flags & DBG_PS) != 0;
970 case TGSI_PROCESSOR_COMPUTE:
971 return (rscreen->debug_flags & DBG_CS) != 0;
972 default:
973 return false;
974 }
975 }
976
977 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
978 unsigned offset, unsigned size, unsigned value,
979 bool is_framebuffer)
980 {
981 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
982
983 pipe_mutex_lock(rscreen->aux_context_lock);
984 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
985 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
986 pipe_mutex_unlock(rscreen->aux_context_lock);
987 }