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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 /*
40 * pipe_context
41 */
42
43 void r600_draw_rectangle(struct blitter_context *blitter,
44 int x1, int y1, int x2, int y2, float depth,
45 enum blitter_attrib_type type,
46 const union pipe_color_union *attrib)
47 {
48 struct r600_common_context *rctx =
49 (struct r600_common_context*)util_blitter_get_pipe(blitter);
50 struct pipe_viewport_state viewport;
51 struct pipe_resource *buf = NULL;
52 unsigned offset = 0;
53 float *vb;
54
55 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
56 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
57 return;
58 }
59
60 /* Some operations (like color resolve on r6xx) don't work
61 * with the conventional primitive types.
62 * One that works is PT_RECTLIST, which we use here. */
63
64 /* setup viewport */
65 viewport.scale[0] = 1.0f;
66 viewport.scale[1] = 1.0f;
67 viewport.scale[2] = 1.0f;
68 viewport.translate[0] = 0.0f;
69 viewport.translate[1] = 0.0f;
70 viewport.translate[2] = 0.0f;
71 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
72
73 /* Upload vertices. The hw rectangle has only 3 vertices,
74 * I guess the 4th one is derived from the first 3.
75 * The vertex specification should match u_blitter's vertex element state. */
76 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
77 vb[0] = x1;
78 vb[1] = y1;
79 vb[2] = depth;
80 vb[3] = 1;
81
82 vb[8] = x1;
83 vb[9] = y2;
84 vb[10] = depth;
85 vb[11] = 1;
86
87 vb[16] = x2;
88 vb[17] = y1;
89 vb[18] = depth;
90 vb[19] = 1;
91
92 if (attrib) {
93 memcpy(vb+4, attrib->f, sizeof(float)*4);
94 memcpy(vb+12, attrib->f, sizeof(float)*4);
95 memcpy(vb+20, attrib->f, sizeof(float)*4);
96 }
97
98 /* draw */
99 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
100 R600_PRIM_RECTANGLE_LIST, 3, 2);
101 pipe_resource_reference(&buf, NULL);
102 }
103
104 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
105 {
106 /* The number of dwords we already used in the DMA so far. */
107 num_dw += ctx->rings.dma.cs->cdw;
108 /* Flush if there's not enough space. */
109 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
110 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
111 }
112 }
113
114 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
115 {
116 }
117
118 void r600_preflush_suspend_features(struct r600_common_context *ctx)
119 {
120 /* Disable render condition. */
121 ctx->saved_render_cond = NULL;
122 ctx->saved_render_cond_cond = FALSE;
123 ctx->saved_render_cond_mode = 0;
124 if (ctx->current_render_cond) {
125 ctx->saved_render_cond = ctx->current_render_cond;
126 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
127 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
128 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
129 }
130
131 /* suspend queries */
132 ctx->nontimer_queries_suspended = false;
133 if (ctx->num_cs_dw_nontimer_queries_suspend) {
134 r600_suspend_nontimer_queries(ctx);
135 ctx->nontimer_queries_suspended = true;
136 }
137
138 ctx->streamout.suspended = false;
139 if (ctx->streamout.begin_emitted) {
140 r600_emit_streamout_end(ctx);
141 ctx->streamout.suspended = true;
142 }
143 }
144
145 void r600_postflush_resume_features(struct r600_common_context *ctx)
146 {
147 if (ctx->streamout.suspended) {
148 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
149 r600_streamout_buffers_dirty(ctx);
150 }
151
152 /* resume queries */
153 if (ctx->nontimer_queries_suspended) {
154 r600_resume_nontimer_queries(ctx);
155 }
156
157 /* Re-enable render condition. */
158 if (ctx->saved_render_cond) {
159 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
160 ctx->saved_render_cond_cond,
161 ctx->saved_render_cond_mode);
162 }
163 }
164
165 static void r600_flush_from_st(struct pipe_context *ctx,
166 struct pipe_fence_handle **fence,
167 unsigned flags)
168 {
169 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
170 unsigned rflags = 0;
171
172 if (flags & PIPE_FLUSH_END_OF_FRAME)
173 rflags |= RADEON_FLUSH_END_OF_FRAME;
174
175 if (rctx->rings.dma.cs) {
176 rctx->rings.dma.flush(rctx, rflags, NULL);
177 }
178 rctx->rings.gfx.flush(rctx, rflags, fence);
179 }
180
181 static void r600_flush_dma_ring(void *ctx, unsigned flags,
182 struct pipe_fence_handle **fence)
183 {
184 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
185 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
186
187 if (!cs->cdw) {
188 return;
189 }
190
191 rctx->rings.dma.flushing = true;
192 rctx->ws->cs_flush(cs, flags, fence, 0);
193 rctx->rings.dma.flushing = false;
194 }
195
196 bool r600_common_context_init(struct r600_common_context *rctx,
197 struct r600_common_screen *rscreen)
198 {
199 util_slab_create(&rctx->pool_transfers,
200 sizeof(struct r600_transfer), 64,
201 UTIL_SLAB_SINGLETHREADED);
202
203 rctx->screen = rscreen;
204 rctx->ws = rscreen->ws;
205 rctx->family = rscreen->family;
206 rctx->chip_class = rscreen->chip_class;
207
208 if (rscreen->family == CHIP_HAWAII)
209 rctx->max_db = 16;
210 else if (rscreen->chip_class >= EVERGREEN)
211 rctx->max_db = 8;
212 else
213 rctx->max_db = 4;
214
215 rctx->b.transfer_map = u_transfer_map_vtbl;
216 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
217 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
218 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
219 rctx->b.memory_barrier = r600_memory_barrier;
220 rctx->b.flush = r600_flush_from_st;
221
222 LIST_INITHEAD(&rctx->texture_buffers);
223
224 r600_init_context_texture_functions(rctx);
225 r600_streamout_init(rctx);
226 r600_query_init(rctx);
227 cayman_init_msaa(&rctx->b);
228
229 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
230 0, PIPE_USAGE_DEFAULT, TRUE);
231 if (!rctx->allocator_so_filled_size)
232 return false;
233
234 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
235 PIPE_BIND_INDEX_BUFFER |
236 PIPE_BIND_CONSTANT_BUFFER);
237 if (!rctx->uploader)
238 return false;
239
240 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
241 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
242 r600_flush_dma_ring,
243 rctx, NULL);
244 rctx->rings.dma.flush = r600_flush_dma_ring;
245 }
246
247 return true;
248 }
249
250 void r600_common_context_cleanup(struct r600_common_context *rctx)
251 {
252 if (rctx->rings.gfx.cs) {
253 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
254 }
255 if (rctx->rings.dma.cs) {
256 rctx->ws->cs_destroy(rctx->rings.dma.cs);
257 }
258
259 if (rctx->uploader) {
260 u_upload_destroy(rctx->uploader);
261 }
262
263 util_slab_destroy(&rctx->pool_transfers);
264
265 if (rctx->allocator_so_filled_size) {
266 u_suballocator_destroy(rctx->allocator_so_filled_size);
267 }
268 }
269
270 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
271 {
272 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
273 struct r600_resource *rr = (struct r600_resource *)r;
274
275 if (r == NULL) {
276 return;
277 }
278
279 /*
280 * The idea is to compute a gross estimate of memory requirement of
281 * each draw call. After each draw call, memory will be precisely
282 * accounted. So the uncertainty is only on the current draw call.
283 * In practice this gave very good estimate (+/- 10% of the target
284 * memory limit).
285 */
286 if (rr->domains & RADEON_DOMAIN_GTT) {
287 rctx->gtt += rr->buf->size;
288 }
289 if (rr->domains & RADEON_DOMAIN_VRAM) {
290 rctx->vram += rr->buf->size;
291 }
292 }
293
294 /*
295 * pipe_screen
296 */
297
298 static const struct debug_named_value common_debug_options[] = {
299 /* logging */
300 { "tex", DBG_TEX, "Print texture info" },
301 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
302 { "compute", DBG_COMPUTE, "Print compute info" },
303 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
304 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
305
306 /* shaders */
307 { "fs", DBG_FS, "Print fetch shaders" },
308 { "vs", DBG_VS, "Print vertex shaders" },
309 { "gs", DBG_GS, "Print geometry shaders" },
310 { "ps", DBG_PS, "Print pixel shaders" },
311 { "cs", DBG_CS, "Print compute shaders" },
312
313 /* features */
314 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
315 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
316 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
317 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
318 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
319 { "notiling", DBG_NO_TILING, "Disable tiling" },
320 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
321 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
322
323 DEBUG_NAMED_VALUE_END /* must be last */
324 };
325
326 static const char* r600_get_vendor(struct pipe_screen* pscreen)
327 {
328 return "X.Org";
329 }
330
331 static const char* r600_get_name(struct pipe_screen* pscreen)
332 {
333 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
334
335 switch (rscreen->family) {
336 case CHIP_R600: return "AMD R600";
337 case CHIP_RV610: return "AMD RV610";
338 case CHIP_RV630: return "AMD RV630";
339 case CHIP_RV670: return "AMD RV670";
340 case CHIP_RV620: return "AMD RV620";
341 case CHIP_RV635: return "AMD RV635";
342 case CHIP_RS780: return "AMD RS780";
343 case CHIP_RS880: return "AMD RS880";
344 case CHIP_RV770: return "AMD RV770";
345 case CHIP_RV730: return "AMD RV730";
346 case CHIP_RV710: return "AMD RV710";
347 case CHIP_RV740: return "AMD RV740";
348 case CHIP_CEDAR: return "AMD CEDAR";
349 case CHIP_REDWOOD: return "AMD REDWOOD";
350 case CHIP_JUNIPER: return "AMD JUNIPER";
351 case CHIP_CYPRESS: return "AMD CYPRESS";
352 case CHIP_HEMLOCK: return "AMD HEMLOCK";
353 case CHIP_PALM: return "AMD PALM";
354 case CHIP_SUMO: return "AMD SUMO";
355 case CHIP_SUMO2: return "AMD SUMO2";
356 case CHIP_BARTS: return "AMD BARTS";
357 case CHIP_TURKS: return "AMD TURKS";
358 case CHIP_CAICOS: return "AMD CAICOS";
359 case CHIP_CAYMAN: return "AMD CAYMAN";
360 case CHIP_ARUBA: return "AMD ARUBA";
361 case CHIP_TAHITI: return "AMD TAHITI";
362 case CHIP_PITCAIRN: return "AMD PITCAIRN";
363 case CHIP_VERDE: return "AMD CAPE VERDE";
364 case CHIP_OLAND: return "AMD OLAND";
365 case CHIP_HAINAN: return "AMD HAINAN";
366 case CHIP_BONAIRE: return "AMD BONAIRE";
367 case CHIP_KAVERI: return "AMD KAVERI";
368 case CHIP_KABINI: return "AMD KABINI";
369 case CHIP_HAWAII: return "AMD HAWAII";
370 case CHIP_MULLINS: return "AMD MULLINS";
371 default: return "AMD unknown";
372 }
373 }
374
375 static float r600_get_paramf(struct pipe_screen* pscreen,
376 enum pipe_capf param)
377 {
378 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
379
380 switch (param) {
381 case PIPE_CAPF_MAX_LINE_WIDTH:
382 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
383 case PIPE_CAPF_MAX_POINT_WIDTH:
384 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
385 if (rscreen->family >= CHIP_CEDAR)
386 return 16384.0f;
387 else
388 return 8192.0f;
389 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
390 return 16.0f;
391 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
392 return 16.0f;
393 case PIPE_CAPF_GUARD_BAND_LEFT:
394 case PIPE_CAPF_GUARD_BAND_TOP:
395 case PIPE_CAPF_GUARD_BAND_RIGHT:
396 case PIPE_CAPF_GUARD_BAND_BOTTOM:
397 return 0.0f;
398 }
399 return 0.0f;
400 }
401
402 static int r600_get_video_param(struct pipe_screen *screen,
403 enum pipe_video_profile profile,
404 enum pipe_video_entrypoint entrypoint,
405 enum pipe_video_cap param)
406 {
407 switch (param) {
408 case PIPE_VIDEO_CAP_SUPPORTED:
409 return vl_profile_supported(screen, profile, entrypoint);
410 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
411 return 1;
412 case PIPE_VIDEO_CAP_MAX_WIDTH:
413 case PIPE_VIDEO_CAP_MAX_HEIGHT:
414 return vl_video_buffer_max_size(screen);
415 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
416 return PIPE_FORMAT_NV12;
417 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
418 return false;
419 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
420 return false;
421 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
422 return true;
423 case PIPE_VIDEO_CAP_MAX_LEVEL:
424 return vl_level_supported(screen, profile);
425 default:
426 return 0;
427 }
428 }
429
430 const char *r600_get_llvm_processor_name(enum radeon_family family)
431 {
432 switch (family) {
433 case CHIP_R600:
434 case CHIP_RV630:
435 case CHIP_RV635:
436 case CHIP_RV670:
437 return "r600";
438 case CHIP_RV610:
439 case CHIP_RV620:
440 case CHIP_RS780:
441 case CHIP_RS880:
442 return "rs880";
443 case CHIP_RV710:
444 return "rv710";
445 case CHIP_RV730:
446 return "rv730";
447 case CHIP_RV740:
448 case CHIP_RV770:
449 return "rv770";
450 case CHIP_PALM:
451 case CHIP_CEDAR:
452 return "cedar";
453 case CHIP_SUMO:
454 case CHIP_SUMO2:
455 return "sumo";
456 case CHIP_REDWOOD:
457 return "redwood";
458 case CHIP_JUNIPER:
459 return "juniper";
460 case CHIP_HEMLOCK:
461 case CHIP_CYPRESS:
462 return "cypress";
463 case CHIP_BARTS:
464 return "barts";
465 case CHIP_TURKS:
466 return "turks";
467 case CHIP_CAICOS:
468 return "caicos";
469 case CHIP_CAYMAN:
470 case CHIP_ARUBA:
471 return "cayman";
472
473 case CHIP_TAHITI: return "tahiti";
474 case CHIP_PITCAIRN: return "pitcairn";
475 case CHIP_VERDE: return "verde";
476 case CHIP_OLAND: return "oland";
477 case CHIP_HAINAN: return "hainan";
478 case CHIP_BONAIRE: return "bonaire";
479 case CHIP_KABINI: return "kabini";
480 case CHIP_KAVERI: return "kaveri";
481 case CHIP_HAWAII: return "hawaii";
482 case CHIP_MULLINS:
483 #if HAVE_LLVM >= 0x0305
484 return "mullins";
485 #else
486 return "kabini";
487 #endif
488 default: return "";
489 }
490 }
491
492 static int r600_get_compute_param(struct pipe_screen *screen,
493 enum pipe_compute_cap param,
494 void *ret)
495 {
496 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
497
498 //TODO: select these params by asic
499 switch (param) {
500 case PIPE_COMPUTE_CAP_IR_TARGET: {
501 const char *gpu;
502 const char *triple;
503 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
504 triple = "r600--";
505 } else {
506 triple = "amdgcn--";
507 }
508 switch(rscreen->family) {
509 /* Clang < 3.6 is missing Hainan in its list of
510 * GPUs, so we need to use the name of a similar GPU.
511 */
512 #if HAVE_LLVM < 0x0306
513 case CHIP_HAINAN:
514 gpu = "oland";
515 break;
516 #endif
517 default:
518 gpu = r600_get_llvm_processor_name(rscreen->family);
519 break;
520 }
521 if (ret) {
522 sprintf(ret, "%s-%s", gpu, triple);
523
524 }
525 return (strlen(triple) + strlen(gpu)) * sizeof(char);
526 }
527 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
528 if (ret) {
529 uint64_t *grid_dimension = ret;
530 grid_dimension[0] = 3;
531 }
532 return 1 * sizeof(uint64_t);
533
534 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
535 if (ret) {
536 uint64_t *grid_size = ret;
537 grid_size[0] = 65535;
538 grid_size[1] = 65535;
539 grid_size[2] = 1;
540 }
541 return 3 * sizeof(uint64_t) ;
542
543 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
544 if (ret) {
545 uint64_t *block_size = ret;
546 block_size[0] = 256;
547 block_size[1] = 256;
548 block_size[2] = 256;
549 }
550 return 3 * sizeof(uint64_t);
551
552 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
553 if (ret) {
554 uint64_t *max_threads_per_block = ret;
555 *max_threads_per_block = 256;
556 }
557 return sizeof(uint64_t);
558
559 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
560 if (ret) {
561 uint64_t *max_global_size = ret;
562 uint64_t max_mem_alloc_size;
563
564 r600_get_compute_param(screen,
565 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
566 &max_mem_alloc_size);
567
568 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
569 * 1/4 of the MAX_GLOBAL_SIZE. Since the
570 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
571 * make sure we never report more than
572 * 4 * MAX_MEM_ALLOC_SIZE.
573 */
574 *max_global_size = MIN2(4 * max_mem_alloc_size,
575 rscreen->info.gart_size +
576 rscreen->info.vram_size);
577 }
578 return sizeof(uint64_t);
579
580 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
581 if (ret) {
582 uint64_t *max_local_size = ret;
583 /* Value reported by the closed source driver. */
584 *max_local_size = 32768;
585 }
586 return sizeof(uint64_t);
587
588 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
589 if (ret) {
590 uint64_t *max_input_size = ret;
591 /* Value reported by the closed source driver. */
592 *max_input_size = 1024;
593 }
594 return sizeof(uint64_t);
595
596 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
597 if (ret) {
598 uint64_t *max_mem_alloc_size = ret;
599
600 /* XXX: The limit in older kernels is 256 MB. We
601 * should add a query here for newer kernels.
602 */
603 *max_mem_alloc_size = 256 * 1024 * 1024;
604 }
605 return sizeof(uint64_t);
606
607 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
608 if (ret) {
609 uint32_t *max_clock_frequency = ret;
610 *max_clock_frequency = rscreen->info.max_sclk;
611 }
612 return sizeof(uint32_t);
613
614 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
615 if (ret) {
616 uint32_t *max_compute_units = ret;
617 *max_compute_units = rscreen->info.max_compute_units;
618 }
619 return sizeof(uint32_t);
620
621 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
622 if (ret) {
623 uint32_t *images_supported = ret;
624 *images_supported = 0;
625 }
626 return sizeof(uint32_t);
627 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
628 break; /* unused */
629 }
630
631 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
632 return 0;
633 }
634
635 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
636 {
637 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
638
639 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
640 rscreen->info.r600_clock_crystal_freq;
641 }
642
643 static int r600_get_driver_query_info(struct pipe_screen *screen,
644 unsigned index,
645 struct pipe_driver_query_info *info)
646 {
647 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
648 struct pipe_driver_query_info list[] = {
649 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
650 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
651 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
652 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
653 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
654 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
655 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
656 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
657 };
658
659 if (!info)
660 return Elements(list);
661
662 if (index >= Elements(list))
663 return 0;
664
665 *info = list[index];
666 return 1;
667 }
668
669 static void r600_fence_reference(struct pipe_screen *screen,
670 struct pipe_fence_handle **ptr,
671 struct pipe_fence_handle *fence)
672 {
673 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
674
675 rws->fence_reference(ptr, fence);
676 }
677
678 static boolean r600_fence_signalled(struct pipe_screen *screen,
679 struct pipe_fence_handle *fence)
680 {
681 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
682
683 return rws->fence_wait(rws, fence, 0);
684 }
685
686 static boolean r600_fence_finish(struct pipe_screen *screen,
687 struct pipe_fence_handle *fence,
688 uint64_t timeout)
689 {
690 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
691
692 return rws->fence_wait(rws, fence, timeout);
693 }
694
695 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
696 uint32_t tiling_config)
697 {
698 switch ((tiling_config & 0xe) >> 1) {
699 case 0:
700 rscreen->tiling_info.num_channels = 1;
701 break;
702 case 1:
703 rscreen->tiling_info.num_channels = 2;
704 break;
705 case 2:
706 rscreen->tiling_info.num_channels = 4;
707 break;
708 case 3:
709 rscreen->tiling_info.num_channels = 8;
710 break;
711 default:
712 return false;
713 }
714
715 switch ((tiling_config & 0x30) >> 4) {
716 case 0:
717 rscreen->tiling_info.num_banks = 4;
718 break;
719 case 1:
720 rscreen->tiling_info.num_banks = 8;
721 break;
722 default:
723 return false;
724
725 }
726 switch ((tiling_config & 0xc0) >> 6) {
727 case 0:
728 rscreen->tiling_info.group_bytes = 256;
729 break;
730 case 1:
731 rscreen->tiling_info.group_bytes = 512;
732 break;
733 default:
734 return false;
735 }
736 return true;
737 }
738
739 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
740 uint32_t tiling_config)
741 {
742 switch (tiling_config & 0xf) {
743 case 0:
744 rscreen->tiling_info.num_channels = 1;
745 break;
746 case 1:
747 rscreen->tiling_info.num_channels = 2;
748 break;
749 case 2:
750 rscreen->tiling_info.num_channels = 4;
751 break;
752 case 3:
753 rscreen->tiling_info.num_channels = 8;
754 break;
755 default:
756 return false;
757 }
758
759 switch ((tiling_config & 0xf0) >> 4) {
760 case 0:
761 rscreen->tiling_info.num_banks = 4;
762 break;
763 case 1:
764 rscreen->tiling_info.num_banks = 8;
765 break;
766 case 2:
767 rscreen->tiling_info.num_banks = 16;
768 break;
769 default:
770 return false;
771 }
772
773 switch ((tiling_config & 0xf00) >> 8) {
774 case 0:
775 rscreen->tiling_info.group_bytes = 256;
776 break;
777 case 1:
778 rscreen->tiling_info.group_bytes = 512;
779 break;
780 default:
781 return false;
782 }
783 return true;
784 }
785
786 static bool r600_init_tiling(struct r600_common_screen *rscreen)
787 {
788 uint32_t tiling_config = rscreen->info.r600_tiling_config;
789
790 /* set default group bytes, overridden by tiling info ioctl */
791 if (rscreen->chip_class <= R700) {
792 rscreen->tiling_info.group_bytes = 256;
793 } else {
794 rscreen->tiling_info.group_bytes = 512;
795 }
796
797 if (!tiling_config)
798 return true;
799
800 if (rscreen->chip_class <= R700) {
801 return r600_interpret_tiling(rscreen, tiling_config);
802 } else {
803 return evergreen_interpret_tiling(rscreen, tiling_config);
804 }
805 }
806
807 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
808 const struct pipe_resource *templ)
809 {
810 if (templ->target == PIPE_BUFFER) {
811 return r600_buffer_create(screen, templ, 4096);
812 } else {
813 return r600_texture_create(screen, templ);
814 }
815 }
816
817 bool r600_common_screen_init(struct r600_common_screen *rscreen,
818 struct radeon_winsys *ws)
819 {
820 ws->query_info(ws, &rscreen->info);
821
822 rscreen->b.get_name = r600_get_name;
823 rscreen->b.get_vendor = r600_get_vendor;
824 rscreen->b.get_compute_param = r600_get_compute_param;
825 rscreen->b.get_paramf = r600_get_paramf;
826 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
827 rscreen->b.get_timestamp = r600_get_timestamp;
828 rscreen->b.fence_finish = r600_fence_finish;
829 rscreen->b.fence_reference = r600_fence_reference;
830 rscreen->b.fence_signalled = r600_fence_signalled;
831 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
832
833 if (rscreen->info.has_uvd) {
834 rscreen->b.get_video_param = rvid_get_video_param;
835 rscreen->b.is_video_format_supported = rvid_is_format_supported;
836 } else {
837 rscreen->b.get_video_param = r600_get_video_param;
838 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
839 }
840
841 r600_init_screen_texture_functions(rscreen);
842
843 rscreen->ws = ws;
844 rscreen->family = rscreen->info.family;
845 rscreen->chip_class = rscreen->info.chip_class;
846 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
847
848 if (!r600_init_tiling(rscreen)) {
849 return false;
850 }
851 util_format_s3tc_init();
852 pipe_mutex_init(rscreen->aux_context_lock);
853
854 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
855 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
856 PIPE_BIND_CUSTOM,
857 PIPE_USAGE_STAGING,
858 4096);
859 if (rscreen->trace_bo) {
860 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
861 PIPE_TRANSFER_UNSYNCHRONIZED);
862 }
863 }
864
865 return true;
866 }
867
868 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
869 {
870 pipe_mutex_destroy(rscreen->aux_context_lock);
871 rscreen->aux_context->destroy(rscreen->aux_context);
872
873 if (rscreen->trace_bo) {
874 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
875 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
876 }
877
878 rscreen->ws->destroy(rscreen->ws);
879 FREE(rscreen);
880 }
881
882 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
883 {
884 struct tgsi_parse_context parse;
885
886 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
887 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
888 return ~0;
889 }
890 return parse.FullHeader.Processor.Processor;
891 }
892
893 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
894 const struct tgsi_token *tokens)
895 {
896 /* Compute shader don't have tgsi_tokens */
897 if (!tokens)
898 return (rscreen->debug_flags & DBG_CS) != 0;
899
900 switch (tgsi_get_processor_type(tokens)) {
901 case TGSI_PROCESSOR_VERTEX:
902 return (rscreen->debug_flags & DBG_VS) != 0;
903 case TGSI_PROCESSOR_GEOMETRY:
904 return (rscreen->debug_flags & DBG_GS) != 0;
905 case TGSI_PROCESSOR_FRAGMENT:
906 return (rscreen->debug_flags & DBG_PS) != 0;
907 case TGSI_PROCESSOR_COMPUTE:
908 return (rscreen->debug_flags & DBG_CS) != 0;
909 default:
910 return false;
911 }
912 }
913
914 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
915 unsigned offset, unsigned size, unsigned value)
916 {
917 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
918
919 pipe_mutex_lock(rscreen->aux_context_lock);
920 rctx->clear_buffer(&rctx->b, dst, offset, size, value);
921 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
922 pipe_mutex_unlock(rscreen->aux_context_lock);
923 }