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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #include <llvm-c/TargetMachine.h>
43
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49
50 /* If the context wasn't flushed at fence creation, this is non-NULL. */
51 struct {
52 struct r600_common_context *ctx;
53 unsigned ib_index;
54 } gfx_unflushed;
55 };
56
57 /*
58 * shader binary helpers.
59 */
60 void si_radeon_shader_binary_init(struct ac_shader_binary *b)
61 {
62 memset(b, 0, sizeof(*b));
63 }
64
65 void si_radeon_shader_binary_clean(struct ac_shader_binary *b)
66 {
67 if (!b)
68 return;
69 FREE(b->code);
70 FREE(b->config);
71 FREE(b->rodata);
72 FREE(b->global_symbol_offsets);
73 FREE(b->relocs);
74 FREE(b->disasm_string);
75 FREE(b->llvm_ir_string);
76 }
77
78 /*
79 * pipe_context
80 */
81
82 /**
83 * Write an EOP event.
84 *
85 * \param event EVENT_TYPE_*
86 * \param event_flags Optional cache flush flags (TC)
87 * \param data_sel 1 = fence, 3 = timestamp
88 * \param buf Buffer
89 * \param va GPU address
90 * \param old_value Previous fence value (for a bug workaround)
91 * \param new_value Fence value to write for this event.
92 */
93 void si_gfx_write_event_eop(struct r600_common_context *ctx,
94 unsigned event, unsigned event_flags,
95 unsigned data_sel,
96 struct r600_resource *buf, uint64_t va,
97 uint32_t new_fence, unsigned query_type)
98 {
99 struct radeon_winsys_cs *cs = ctx->gfx.cs;
100 unsigned op = EVENT_TYPE(event) |
101 EVENT_INDEX(5) |
102 event_flags;
103 unsigned sel = EOP_DATA_SEL(data_sel);
104
105 /* Wait for write confirmation before writing data, but don't send
106 * an interrupt. */
107 if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
108 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
109
110 if (ctx->chip_class >= GFX9) {
111 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
112 * counters) must immediately precede every timestamp event to
113 * prevent a GPU hang on GFX9.
114 *
115 * Occlusion queries don't need to do it here, because they
116 * always do ZPASS_DONE before the timestamp.
117 */
118 if (ctx->chip_class == GFX9 &&
119 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
120 query_type != PIPE_QUERY_OCCLUSION_PREDICATE &&
121 query_type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
122 struct r600_resource *scratch = ctx->eop_bug_scratch;
123
124 assert(16 * ctx->screen->info.num_render_backends <=
125 scratch->b.b.width0);
126 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
127 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
128 radeon_emit(cs, scratch->gpu_address);
129 radeon_emit(cs, scratch->gpu_address >> 32);
130
131 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
132 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
133 }
134
135 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
136 radeon_emit(cs, op);
137 radeon_emit(cs, sel);
138 radeon_emit(cs, va); /* address lo */
139 radeon_emit(cs, va >> 32); /* address hi */
140 radeon_emit(cs, new_fence); /* immediate data lo */
141 radeon_emit(cs, 0); /* immediate data hi */
142 radeon_emit(cs, 0); /* unused */
143 } else {
144 if (ctx->chip_class == CIK ||
145 ctx->chip_class == VI) {
146 struct r600_resource *scratch = ctx->eop_bug_scratch;
147 uint64_t va = scratch->gpu_address;
148
149 /* Two EOP events are required to make all engines go idle
150 * (and optional cache flushes executed) before the timestamp
151 * is written.
152 */
153 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
154 radeon_emit(cs, op);
155 radeon_emit(cs, va);
156 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
157 radeon_emit(cs, 0); /* immediate data */
158 radeon_emit(cs, 0); /* unused */
159
160 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
161 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
162 }
163
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
165 radeon_emit(cs, op);
166 radeon_emit(cs, va);
167 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
168 radeon_emit(cs, new_fence); /* immediate data */
169 radeon_emit(cs, 0); /* unused */
170 }
171
172 if (buf)
173 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
174 RADEON_PRIO_QUERY);
175 }
176
177 unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen)
178 {
179 unsigned dwords = 6;
180
181 if (screen->chip_class == CIK ||
182 screen->chip_class == VI)
183 dwords *= 2;
184
185 if (!screen->info.has_virtual_memory)
186 dwords += 2;
187
188 return dwords;
189 }
190
191 void si_gfx_wait_fence(struct r600_common_context *ctx,
192 uint64_t va, uint32_t ref, uint32_t mask)
193 {
194 struct radeon_winsys_cs *cs = ctx->gfx.cs;
195
196 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
197 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
198 radeon_emit(cs, va);
199 radeon_emit(cs, va >> 32);
200 radeon_emit(cs, ref); /* reference value */
201 radeon_emit(cs, mask); /* mask */
202 radeon_emit(cs, 4); /* poll interval */
203 }
204
205 void si_draw_rectangle(struct blitter_context *blitter,
206 int x1, int y1, int x2, int y2,
207 float depth, unsigned num_instances,
208 enum blitter_attrib_type type,
209 const union blitter_attrib *attrib)
210 {
211 struct r600_common_context *rctx =
212 (struct r600_common_context*)util_blitter_get_pipe(blitter);
213 struct pipe_viewport_state viewport;
214 struct pipe_resource *buf = NULL;
215 unsigned offset = 0;
216 float *vb;
217
218 /* Some operations (like color resolve on r6xx) don't work
219 * with the conventional primitive types.
220 * One that works is PT_RECTLIST, which we use here. */
221
222 /* setup viewport */
223 viewport.scale[0] = 1.0f;
224 viewport.scale[1] = 1.0f;
225 viewport.scale[2] = 1.0f;
226 viewport.translate[0] = 0.0f;
227 viewport.translate[1] = 0.0f;
228 viewport.translate[2] = 0.0f;
229 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
230
231 /* Upload vertices. The hw rectangle has only 3 vertices,
232 * The 4th one is derived from the first 3.
233 * The vertex specification should match u_blitter's vertex element state. */
234 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
235 rctx->screen->info.tcc_cache_line_size,
236 &offset, &buf, (void**)&vb);
237 if (!buf)
238 return;
239
240 vb[0] = x1;
241 vb[1] = y1;
242 vb[2] = depth;
243 vb[3] = 1;
244
245 vb[8] = x1;
246 vb[9] = y2;
247 vb[10] = depth;
248 vb[11] = 1;
249
250 vb[16] = x2;
251 vb[17] = y1;
252 vb[18] = depth;
253 vb[19] = 1;
254
255 switch (type) {
256 case UTIL_BLITTER_ATTRIB_COLOR:
257 memcpy(vb+4, attrib->color, sizeof(float)*4);
258 memcpy(vb+12, attrib->color, sizeof(float)*4);
259 memcpy(vb+20, attrib->color, sizeof(float)*4);
260 break;
261 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
262 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
263 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
264 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
265 /* fall through */
266 vb[4] = attrib->texcoord.x1;
267 vb[5] = attrib->texcoord.y1;
268 vb[12] = attrib->texcoord.x1;
269 vb[13] = attrib->texcoord.y2;
270 vb[20] = attrib->texcoord.x2;
271 vb[21] = attrib->texcoord.y1;
272 break;
273 default:; /* Nothing to do. */
274 }
275
276 /* draw */
277 struct pipe_vertex_buffer vbuffer = {};
278 vbuffer.buffer.resource = buf;
279 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
280 vbuffer.buffer_offset = offset;
281
282 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
283 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
284 0, num_instances);
285 pipe_resource_reference(&buf, NULL);
286 }
287
288 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
289 {
290 struct radeon_winsys_cs *cs = rctx->dma.cs;
291
292 /* NOP waits for idle on Evergreen and later. */
293 if (rctx->chip_class >= CIK)
294 radeon_emit(cs, 0x00000000); /* NOP */
295 else if (rctx->chip_class >= EVERGREEN)
296 radeon_emit(cs, 0xf0000000); /* NOP */
297 else {
298 /* TODO: R600-R700 should use the FENCE packet.
299 * CS checker support is required. */
300 }
301 }
302
303 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
304 struct r600_resource *dst, struct r600_resource *src)
305 {
306 uint64_t vram = ctx->dma.cs->used_vram;
307 uint64_t gtt = ctx->dma.cs->used_gart;
308
309 if (dst) {
310 vram += dst->vram_usage;
311 gtt += dst->gart_usage;
312 }
313 if (src) {
314 vram += src->vram_usage;
315 gtt += src->gart_usage;
316 }
317
318 /* Flush the GFX IB if DMA depends on it. */
319 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
320 ((dst &&
321 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
322 RADEON_USAGE_READWRITE)) ||
323 (src &&
324 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
325 RADEON_USAGE_WRITE))))
326 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
327
328 /* Flush if there's not enough space, or if the memory usage per IB
329 * is too large.
330 *
331 * IBs using too little memory are limited by the IB submission overhead.
332 * IBs using too much memory are limited by the kernel/TTM overhead.
333 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
334 *
335 * This heuristic makes sure that DMA requests are executed
336 * very soon after the call is made and lowers memory usage.
337 * It improves texture upload performance by keeping the DMA
338 * engine busy while uploads are being submitted.
339 */
340 num_dw++; /* for emit_wait_idle below */
341 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
342 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
343 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
344 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
345 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
346 }
347
348 /* Wait for idle if either buffer has been used in the IB before to
349 * prevent read-after-write hazards.
350 */
351 if ((dst &&
352 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
353 RADEON_USAGE_READWRITE)) ||
354 (src &&
355 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
356 RADEON_USAGE_WRITE)))
357 r600_dma_emit_wait_idle(ctx);
358
359 /* If GPUVM is not supported, the CS checker needs 2 entries
360 * in the buffer list per packet, which has to be done manually.
361 */
362 if (ctx->screen->info.has_virtual_memory) {
363 if (dst)
364 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
365 RADEON_USAGE_WRITE,
366 RADEON_PRIO_SDMA_BUFFER);
367 if (src)
368 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
369 RADEON_USAGE_READ,
370 RADEON_PRIO_SDMA_BUFFER);
371 }
372
373 /* this function is called before all DMA calls, so increment this. */
374 ctx->num_dma_calls++;
375 }
376
377 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
378 {
379 }
380
381 void si_preflush_suspend_features(struct r600_common_context *ctx)
382 {
383 /* suspend queries */
384 if (!LIST_IS_EMPTY(&ctx->active_queries))
385 si_suspend_queries(ctx);
386
387 ctx->streamout.suspended = false;
388 if (ctx->streamout.begin_emitted) {
389 si_emit_streamout_end(ctx);
390 ctx->streamout.suspended = true;
391 }
392 }
393
394 void si_postflush_resume_features(struct r600_common_context *ctx)
395 {
396 if (ctx->streamout.suspended) {
397 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
398 si_streamout_buffers_dirty(ctx);
399 }
400
401 /* resume queries */
402 if (!LIST_IS_EMPTY(&ctx->active_queries))
403 si_resume_queries(ctx);
404 }
405
406 static void r600_add_fence_dependency(struct r600_common_context *rctx,
407 struct pipe_fence_handle *fence)
408 {
409 struct radeon_winsys *ws = rctx->ws;
410
411 if (rctx->dma.cs)
412 ws->cs_add_fence_dependency(rctx->dma.cs, fence);
413 ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
414 }
415
416 static void r600_fence_server_sync(struct pipe_context *ctx,
417 struct pipe_fence_handle *fence)
418 {
419 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
420 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
421
422 /* Only amdgpu needs to handle fence dependencies (for fence imports).
423 * radeon synchronizes all rings by default and will not implement
424 * fence imports.
425 */
426 if (rctx->screen->info.drm_major == 2)
427 return;
428
429 /* Only imported fences need to be handled by fence_server_sync,
430 * because the winsys handles synchronizations automatically for BOs
431 * within the process.
432 *
433 * Simply skip unflushed fences here, and the winsys will drop no-op
434 * dependencies (i.e. dependencies within the same ring).
435 */
436 if (rfence->gfx_unflushed.ctx)
437 return;
438
439 /* All unflushed commands will not start execution before
440 * this fence dependency is signalled.
441 *
442 * Should we flush the context to allow more GPU parallelism?
443 */
444 if (rfence->sdma)
445 r600_add_fence_dependency(rctx, rfence->sdma);
446 if (rfence->gfx)
447 r600_add_fence_dependency(rctx, rfence->gfx);
448 }
449
450 static void r600_flush_from_st(struct pipe_context *ctx,
451 struct pipe_fence_handle **fence,
452 unsigned flags)
453 {
454 struct pipe_screen *screen = ctx->screen;
455 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
456 struct radeon_winsys *ws = rctx->ws;
457 struct pipe_fence_handle *gfx_fence = NULL;
458 struct pipe_fence_handle *sdma_fence = NULL;
459 bool deferred_fence = false;
460 unsigned rflags = RADEON_FLUSH_ASYNC;
461
462 if (flags & PIPE_FLUSH_END_OF_FRAME)
463 rflags |= RADEON_FLUSH_END_OF_FRAME;
464
465 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
466 if (rctx->dma.cs)
467 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
468
469 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
470 if (fence)
471 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
472 if (!(flags & PIPE_FLUSH_DEFERRED))
473 ws->cs_sync_flush(rctx->gfx.cs);
474 } else {
475 /* Instead of flushing, create a deferred fence. Constraints:
476 * - The state tracker must allow a deferred flush.
477 * - The state tracker must request a fence.
478 * Thread safety in fence_finish must be ensured by the state tracker.
479 */
480 if (flags & PIPE_FLUSH_DEFERRED && fence) {
481 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
482 deferred_fence = true;
483 } else {
484 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
485 }
486 }
487
488 /* Both engines can signal out of order, so we need to keep both fences. */
489 if (fence) {
490 struct r600_multi_fence *multi_fence =
491 CALLOC_STRUCT(r600_multi_fence);
492 if (!multi_fence) {
493 ws->fence_reference(&sdma_fence, NULL);
494 ws->fence_reference(&gfx_fence, NULL);
495 goto finish;
496 }
497
498 multi_fence->reference.count = 1;
499 /* If both fences are NULL, fence_finish will always return true. */
500 multi_fence->gfx = gfx_fence;
501 multi_fence->sdma = sdma_fence;
502
503 if (deferred_fence) {
504 multi_fence->gfx_unflushed.ctx = rctx;
505 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
506 }
507
508 screen->fence_reference(screen, fence, NULL);
509 *fence = (struct pipe_fence_handle*)multi_fence;
510 }
511 finish:
512 if (!(flags & PIPE_FLUSH_DEFERRED)) {
513 if (rctx->dma.cs)
514 ws->cs_sync_flush(rctx->dma.cs);
515 ws->cs_sync_flush(rctx->gfx.cs);
516 }
517 }
518
519 static void r600_flush_dma_ring(void *ctx, unsigned flags,
520 struct pipe_fence_handle **fence)
521 {
522 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
523 struct radeon_winsys_cs *cs = rctx->dma.cs;
524 struct radeon_saved_cs saved;
525 bool check_vm =
526 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
527 rctx->check_vm_faults;
528
529 if (!radeon_emitted(cs, 0)) {
530 if (fence)
531 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
532 return;
533 }
534
535 if (check_vm)
536 si_save_cs(rctx->ws, cs, &saved, true);
537
538 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
539 if (fence)
540 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
541
542 if (check_vm) {
543 /* Use conservative timeout 800ms, after which we won't wait any
544 * longer and assume the GPU is hung.
545 */
546 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
547
548 rctx->check_vm_faults(rctx, &saved, RING_DMA);
549 si_clear_saved_cs(&saved);
550 }
551 }
552
553 /**
554 * Store a linearized copy of all chunks of \p cs together with the buffer
555 * list in \p saved.
556 */
557 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
558 struct radeon_saved_cs *saved, bool get_buffer_list)
559 {
560 uint32_t *buf;
561 unsigned i;
562
563 /* Save the IB chunks. */
564 saved->num_dw = cs->prev_dw + cs->current.cdw;
565 saved->ib = MALLOC(4 * saved->num_dw);
566 if (!saved->ib)
567 goto oom;
568
569 buf = saved->ib;
570 for (i = 0; i < cs->num_prev; ++i) {
571 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
572 buf += cs->prev[i].cdw;
573 }
574 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
575
576 if (!get_buffer_list)
577 return;
578
579 /* Save the buffer list. */
580 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
581 saved->bo_list = CALLOC(saved->bo_count,
582 sizeof(saved->bo_list[0]));
583 if (!saved->bo_list) {
584 FREE(saved->ib);
585 goto oom;
586 }
587 ws->cs_get_buffer_list(cs, saved->bo_list);
588
589 return;
590
591 oom:
592 fprintf(stderr, "%s: out of memory\n", __func__);
593 memset(saved, 0, sizeof(*saved));
594 }
595
596 void si_clear_saved_cs(struct radeon_saved_cs *saved)
597 {
598 FREE(saved->ib);
599 FREE(saved->bo_list);
600
601 memset(saved, 0, sizeof(*saved));
602 }
603
604 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
605 {
606 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
607 unsigned latest = rctx->ws->query_value(rctx->ws,
608 RADEON_GPU_RESET_COUNTER);
609
610 if (rctx->gpu_reset_counter == latest)
611 return PIPE_NO_RESET;
612
613 rctx->gpu_reset_counter = latest;
614 return PIPE_UNKNOWN_CONTEXT_RESET;
615 }
616
617 static void r600_set_debug_callback(struct pipe_context *ctx,
618 const struct pipe_debug_callback *cb)
619 {
620 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
621
622 if (cb)
623 rctx->debug = *cb;
624 else
625 memset(&rctx->debug, 0, sizeof(rctx->debug));
626 }
627
628 static void r600_set_device_reset_callback(struct pipe_context *ctx,
629 const struct pipe_device_reset_callback *cb)
630 {
631 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
632
633 if (cb)
634 rctx->device_reset_callback = *cb;
635 else
636 memset(&rctx->device_reset_callback, 0,
637 sizeof(rctx->device_reset_callback));
638 }
639
640 bool si_check_device_reset(struct r600_common_context *rctx)
641 {
642 enum pipe_reset_status status;
643
644 if (!rctx->device_reset_callback.reset)
645 return false;
646
647 if (!rctx->b.get_device_reset_status)
648 return false;
649
650 status = rctx->b.get_device_reset_status(&rctx->b);
651 if (status == PIPE_NO_RESET)
652 return false;
653
654 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
655 return true;
656 }
657
658 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
659 struct pipe_resource *dst,
660 uint64_t offset, uint64_t size,
661 unsigned value)
662 {
663 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
664
665 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
666 }
667
668 static bool r600_resource_commit(struct pipe_context *pctx,
669 struct pipe_resource *resource,
670 unsigned level, struct pipe_box *box,
671 bool commit)
672 {
673 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
674 struct r600_resource *res = r600_resource(resource);
675
676 /*
677 * Since buffer commitment changes cannot be pipelined, we need to
678 * (a) flush any pending commands that refer to the buffer we're about
679 * to change, and
680 * (b) wait for threaded submit to finish, including those that were
681 * triggered by some other, earlier operation.
682 */
683 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
684 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
685 res->buf, RADEON_USAGE_READWRITE)) {
686 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
687 }
688 if (radeon_emitted(ctx->dma.cs, 0) &&
689 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
690 res->buf, RADEON_USAGE_READWRITE)) {
691 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
692 }
693
694 ctx->ws->cs_sync_flush(ctx->dma.cs);
695 ctx->ws->cs_sync_flush(ctx->gfx.cs);
696
697 assert(resource->target == PIPE_BUFFER);
698
699 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
700 }
701
702 bool si_common_context_init(struct r600_common_context *rctx,
703 struct r600_common_screen *rscreen,
704 unsigned context_flags)
705 {
706 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
707 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
708
709 rctx->screen = rscreen;
710 rctx->ws = rscreen->ws;
711 rctx->family = rscreen->family;
712 rctx->chip_class = rscreen->chip_class;
713
714 rctx->b.invalidate_resource = si_invalidate_resource;
715 rctx->b.resource_commit = r600_resource_commit;
716 rctx->b.transfer_map = u_transfer_map_vtbl;
717 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
718 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
719 rctx->b.texture_subdata = u_default_texture_subdata;
720 rctx->b.memory_barrier = r600_memory_barrier;
721 rctx->b.flush = r600_flush_from_st;
722 rctx->b.set_debug_callback = r600_set_debug_callback;
723 rctx->b.fence_server_sync = r600_fence_server_sync;
724 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
725 rctx->b.buffer_subdata = si_buffer_subdata;
726
727 /* Set a reasonable default to avoid a performance regression in r600
728 * on stable branches. */
729 rctx->current_rast_prim = PIPE_PRIM_TRIANGLES;
730
731 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
732 rctx->b.get_device_reset_status = r600_get_reset_status;
733 rctx->gpu_reset_counter =
734 rctx->ws->query_value(rctx->ws,
735 RADEON_GPU_RESET_COUNTER);
736 }
737
738 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
739
740 si_init_context_texture_functions(rctx);
741 si_streamout_init(rctx);
742 si_init_query_functions(rctx);
743 si_init_msaa(&rctx->b);
744
745 if (rctx->chip_class == CIK ||
746 rctx->chip_class == VI ||
747 rctx->chip_class == GFX9) {
748 rctx->eop_bug_scratch = (struct r600_resource*)
749 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
750 16 * rscreen->info.num_render_backends);
751 if (!rctx->eop_bug_scratch)
752 return false;
753 }
754
755 rctx->allocator_zeroed_memory =
756 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
757 0, PIPE_USAGE_DEFAULT, 0, true);
758 if (!rctx->allocator_zeroed_memory)
759 return false;
760
761 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
762 0, PIPE_USAGE_STREAM);
763 if (!rctx->b.stream_uploader)
764 return false;
765
766 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
767 0, PIPE_USAGE_DEFAULT);
768 if (!rctx->b.const_uploader)
769 return false;
770
771 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
772 if (!rctx->ctx)
773 return false;
774
775 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
776 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
777 r600_flush_dma_ring,
778 rctx);
779 rctx->dma.flush = r600_flush_dma_ring;
780 }
781
782 return true;
783 }
784
785 void si_common_context_cleanup(struct r600_common_context *rctx)
786 {
787 unsigned i,j;
788
789 /* Release DCC stats. */
790 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
791 assert(!rctx->dcc_stats[i].query_active);
792
793 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
794 if (rctx->dcc_stats[i].ps_stats[j])
795 rctx->b.destroy_query(&rctx->b,
796 rctx->dcc_stats[i].ps_stats[j]);
797
798 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
799 }
800
801 if (rctx->query_result_shader)
802 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
803
804 if (rctx->gfx.cs)
805 rctx->ws->cs_destroy(rctx->gfx.cs);
806 if (rctx->dma.cs)
807 rctx->ws->cs_destroy(rctx->dma.cs);
808 if (rctx->ctx)
809 rctx->ws->ctx_destroy(rctx->ctx);
810
811 if (rctx->b.stream_uploader)
812 u_upload_destroy(rctx->b.stream_uploader);
813 if (rctx->b.const_uploader)
814 u_upload_destroy(rctx->b.const_uploader);
815
816 slab_destroy_child(&rctx->pool_transfers);
817 slab_destroy_child(&rctx->pool_transfers_unsync);
818
819 if (rctx->allocator_zeroed_memory) {
820 u_suballocator_destroy(rctx->allocator_zeroed_memory);
821 }
822 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
823 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
824 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
825 }
826
827 /*
828 * pipe_screen
829 */
830
831 static const struct debug_named_value common_debug_options[] = {
832 /* logging */
833 { "tex", DBG_TEX, "Print texture info" },
834 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
835 { "compute", DBG_COMPUTE, "Print compute info" },
836 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
837 { "info", DBG_INFO, "Print driver information" },
838
839 /* shaders */
840 { "fs", DBG_FS, "Print fetch shaders" },
841 { "vs", DBG_VS, "Print vertex shaders" },
842 { "gs", DBG_GS, "Print geometry shaders" },
843 { "ps", DBG_PS, "Print pixel shaders" },
844 { "cs", DBG_CS, "Print compute shaders" },
845 { "tcs", DBG_TCS, "Print tessellation control shaders" },
846 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
847 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
848 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
849 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
850 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
851 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
852 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
853
854 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
855 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
856 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
857 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
858
859 /* features */
860 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
861 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
862 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
863 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
864 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
865 { "notiling", DBG_NO_TILING, "Disable tiling" },
866 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
867 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
868 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
869 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
870 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
871 { "nodcc", DBG_NO_DCC, "Disable DCC." },
872 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
873 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
874 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
875 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
876 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
877 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
878 { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
879 { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
880 { "nooutoforder", DBG_NO_OUT_OF_ORDER, "Disable out-of-order rasterization" },
881
882 DEBUG_NAMED_VALUE_END /* must be last */
883 };
884
885 static const char* r600_get_vendor(struct pipe_screen* pscreen)
886 {
887 return "X.Org";
888 }
889
890 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
891 {
892 return "AMD";
893 }
894
895 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
896 {
897 if (!ws->get_chip_name)
898 return NULL;
899 return ws->get_chip_name(ws);
900 }
901
902 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
903 {
904 switch (rscreen->info.family) {
905 case CHIP_R600: return "AMD R600";
906 case CHIP_RV610: return "AMD RV610";
907 case CHIP_RV630: return "AMD RV630";
908 case CHIP_RV670: return "AMD RV670";
909 case CHIP_RV620: return "AMD RV620";
910 case CHIP_RV635: return "AMD RV635";
911 case CHIP_RS780: return "AMD RS780";
912 case CHIP_RS880: return "AMD RS880";
913 case CHIP_RV770: return "AMD RV770";
914 case CHIP_RV730: return "AMD RV730";
915 case CHIP_RV710: return "AMD RV710";
916 case CHIP_RV740: return "AMD RV740";
917 case CHIP_CEDAR: return "AMD CEDAR";
918 case CHIP_REDWOOD: return "AMD REDWOOD";
919 case CHIP_JUNIPER: return "AMD JUNIPER";
920 case CHIP_CYPRESS: return "AMD CYPRESS";
921 case CHIP_HEMLOCK: return "AMD HEMLOCK";
922 case CHIP_PALM: return "AMD PALM";
923 case CHIP_SUMO: return "AMD SUMO";
924 case CHIP_SUMO2: return "AMD SUMO2";
925 case CHIP_BARTS: return "AMD BARTS";
926 case CHIP_TURKS: return "AMD TURKS";
927 case CHIP_CAICOS: return "AMD CAICOS";
928 case CHIP_CAYMAN: return "AMD CAYMAN";
929 case CHIP_ARUBA: return "AMD ARUBA";
930 case CHIP_TAHITI: return "AMD TAHITI";
931 case CHIP_PITCAIRN: return "AMD PITCAIRN";
932 case CHIP_VERDE: return "AMD CAPE VERDE";
933 case CHIP_OLAND: return "AMD OLAND";
934 case CHIP_HAINAN: return "AMD HAINAN";
935 case CHIP_BONAIRE: return "AMD BONAIRE";
936 case CHIP_KAVERI: return "AMD KAVERI";
937 case CHIP_KABINI: return "AMD KABINI";
938 case CHIP_HAWAII: return "AMD HAWAII";
939 case CHIP_MULLINS: return "AMD MULLINS";
940 case CHIP_TONGA: return "AMD TONGA";
941 case CHIP_ICELAND: return "AMD ICELAND";
942 case CHIP_CARRIZO: return "AMD CARRIZO";
943 case CHIP_FIJI: return "AMD FIJI";
944 case CHIP_POLARIS10: return "AMD POLARIS10";
945 case CHIP_POLARIS11: return "AMD POLARIS11";
946 case CHIP_POLARIS12: return "AMD POLARIS12";
947 case CHIP_STONEY: return "AMD STONEY";
948 case CHIP_VEGA10: return "AMD VEGA10";
949 case CHIP_RAVEN: return "AMD RAVEN";
950 default: return "AMD unknown";
951 }
952 }
953
954 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
955 {
956 /* Don't use the cache if shader dumping is enabled. */
957 if (rscreen->debug_flags & DBG_ALL_SHADERS)
958 return;
959
960 uint32_t mesa_timestamp;
961 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
962 &mesa_timestamp)) {
963 char *timestamp_str;
964 int res = -1;
965 uint32_t llvm_timestamp;
966
967 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
968 &llvm_timestamp)) {
969 res = asprintf(&timestamp_str, "%u_%u",
970 mesa_timestamp, llvm_timestamp);
971 }
972
973 if (res != -1) {
974 /* These flags affect shader compilation. */
975 uint64_t shader_debug_flags =
976 rscreen->debug_flags &
977 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
978 DBG_SI_SCHED |
979 DBG_UNSAFE_MATH);
980
981 rscreen->disk_shader_cache =
982 disk_cache_create(r600_get_family_name(rscreen),
983 timestamp_str,
984 shader_debug_flags);
985 free(timestamp_str);
986 }
987 }
988 }
989
990 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
991 {
992 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
993 return rscreen->disk_shader_cache;
994 }
995
996 static const char* r600_get_name(struct pipe_screen* pscreen)
997 {
998 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
999
1000 return rscreen->renderer_string;
1001 }
1002
1003 static float r600_get_paramf(struct pipe_screen* pscreen,
1004 enum pipe_capf param)
1005 {
1006 switch (param) {
1007 case PIPE_CAPF_MAX_LINE_WIDTH:
1008 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
1009 case PIPE_CAPF_MAX_POINT_WIDTH:
1010 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
1011 return 8192.0f;
1012 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
1013 return 16.0f;
1014 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
1015 return 16.0f;
1016 case PIPE_CAPF_GUARD_BAND_LEFT:
1017 case PIPE_CAPF_GUARD_BAND_TOP:
1018 case PIPE_CAPF_GUARD_BAND_RIGHT:
1019 case PIPE_CAPF_GUARD_BAND_BOTTOM:
1020 return 0.0f;
1021 }
1022 return 0.0f;
1023 }
1024
1025 static int r600_get_video_param(struct pipe_screen *screen,
1026 enum pipe_video_profile profile,
1027 enum pipe_video_entrypoint entrypoint,
1028 enum pipe_video_cap param)
1029 {
1030 switch (param) {
1031 case PIPE_VIDEO_CAP_SUPPORTED:
1032 return vl_profile_supported(screen, profile, entrypoint);
1033 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
1034 return 1;
1035 case PIPE_VIDEO_CAP_MAX_WIDTH:
1036 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1037 return vl_video_buffer_max_size(screen);
1038 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1039 return PIPE_FORMAT_NV12;
1040 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1041 return false;
1042 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1043 return false;
1044 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1045 return true;
1046 case PIPE_VIDEO_CAP_MAX_LEVEL:
1047 return vl_level_supported(screen, profile);
1048 default:
1049 return 0;
1050 }
1051 }
1052
1053 const char *si_get_llvm_processor_name(enum radeon_family family)
1054 {
1055 switch (family) {
1056 case CHIP_R600:
1057 case CHIP_RV630:
1058 case CHIP_RV635:
1059 case CHIP_RV670:
1060 return "r600";
1061 case CHIP_RV610:
1062 case CHIP_RV620:
1063 case CHIP_RS780:
1064 case CHIP_RS880:
1065 return "rs880";
1066 case CHIP_RV710:
1067 return "rv710";
1068 case CHIP_RV730:
1069 return "rv730";
1070 case CHIP_RV740:
1071 case CHIP_RV770:
1072 return "rv770";
1073 case CHIP_PALM:
1074 case CHIP_CEDAR:
1075 return "cedar";
1076 case CHIP_SUMO:
1077 case CHIP_SUMO2:
1078 return "sumo";
1079 case CHIP_REDWOOD:
1080 return "redwood";
1081 case CHIP_JUNIPER:
1082 return "juniper";
1083 case CHIP_HEMLOCK:
1084 case CHIP_CYPRESS:
1085 return "cypress";
1086 case CHIP_BARTS:
1087 return "barts";
1088 case CHIP_TURKS:
1089 return "turks";
1090 case CHIP_CAICOS:
1091 return "caicos";
1092 case CHIP_CAYMAN:
1093 case CHIP_ARUBA:
1094 return "cayman";
1095
1096 case CHIP_TAHITI: return "tahiti";
1097 case CHIP_PITCAIRN: return "pitcairn";
1098 case CHIP_VERDE: return "verde";
1099 case CHIP_OLAND: return "oland";
1100 case CHIP_HAINAN: return "hainan";
1101 case CHIP_BONAIRE: return "bonaire";
1102 case CHIP_KABINI: return "kabini";
1103 case CHIP_KAVERI: return "kaveri";
1104 case CHIP_HAWAII: return "hawaii";
1105 case CHIP_MULLINS:
1106 return "mullins";
1107 case CHIP_TONGA: return "tonga";
1108 case CHIP_ICELAND: return "iceland";
1109 case CHIP_CARRIZO: return "carrizo";
1110 case CHIP_FIJI:
1111 return "fiji";
1112 case CHIP_STONEY:
1113 return "stoney";
1114 case CHIP_POLARIS10:
1115 return "polaris10";
1116 case CHIP_POLARIS11:
1117 case CHIP_POLARIS12: /* same as polaris11 */
1118 return "polaris11";
1119 case CHIP_VEGA10:
1120 case CHIP_RAVEN:
1121 return "gfx900";
1122 default:
1123 return "";
1124 }
1125 }
1126
1127 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1128 enum pipe_shader_ir ir_type)
1129 {
1130 if (ir_type != PIPE_SHADER_IR_TGSI)
1131 return 256;
1132
1133 /* Only 16 waves per thread-group on gfx9. */
1134 if (screen->chip_class >= GFX9)
1135 return 1024;
1136
1137 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1138 * round number.
1139 */
1140 return 2048;
1141 }
1142
1143 static int r600_get_compute_param(struct pipe_screen *screen,
1144 enum pipe_shader_ir ir_type,
1145 enum pipe_compute_cap param,
1146 void *ret)
1147 {
1148 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1149
1150 //TODO: select these params by asic
1151 switch (param) {
1152 case PIPE_COMPUTE_CAP_IR_TARGET: {
1153 const char *gpu;
1154 const char *triple;
1155 if (rscreen->family <= CHIP_ARUBA) {
1156 triple = "r600--";
1157 } else {
1158 if (HAVE_LLVM < 0x0400) {
1159 triple = "amdgcn--";
1160 } else {
1161 triple = "amdgcn-mesa-mesa3d";
1162 }
1163 }
1164 switch(rscreen->family) {
1165 /* Clang < 3.6 is missing Hainan in its list of
1166 * GPUs, so we need to use the name of a similar GPU.
1167 */
1168 default:
1169 gpu = si_get_llvm_processor_name(rscreen->family);
1170 break;
1171 }
1172 if (ret) {
1173 sprintf(ret, "%s-%s", gpu, triple);
1174 }
1175 /* +2 for dash and terminating NIL byte */
1176 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1177 }
1178 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1179 if (ret) {
1180 uint64_t *grid_dimension = ret;
1181 grid_dimension[0] = 3;
1182 }
1183 return 1 * sizeof(uint64_t);
1184
1185 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1186 if (ret) {
1187 uint64_t *grid_size = ret;
1188 grid_size[0] = 65535;
1189 grid_size[1] = 65535;
1190 grid_size[2] = 65535;
1191 }
1192 return 3 * sizeof(uint64_t) ;
1193
1194 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1195 if (ret) {
1196 uint64_t *block_size = ret;
1197 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1198 block_size[0] = threads_per_block;
1199 block_size[1] = threads_per_block;
1200 block_size[2] = threads_per_block;
1201 }
1202 return 3 * sizeof(uint64_t);
1203
1204 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1205 if (ret) {
1206 uint64_t *max_threads_per_block = ret;
1207 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1208 }
1209 return sizeof(uint64_t);
1210 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1211 if (ret) {
1212 uint32_t *address_bits = ret;
1213 address_bits[0] = 64;
1214 }
1215 return 1 * sizeof(uint32_t);
1216
1217 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1218 if (ret) {
1219 uint64_t *max_global_size = ret;
1220 uint64_t max_mem_alloc_size;
1221
1222 r600_get_compute_param(screen, ir_type,
1223 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1224 &max_mem_alloc_size);
1225
1226 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1227 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1228 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1229 * make sure we never report more than
1230 * 4 * MAX_MEM_ALLOC_SIZE.
1231 */
1232 *max_global_size = MIN2(4 * max_mem_alloc_size,
1233 MAX2(rscreen->info.gart_size,
1234 rscreen->info.vram_size));
1235 }
1236 return sizeof(uint64_t);
1237
1238 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1239 if (ret) {
1240 uint64_t *max_local_size = ret;
1241 /* Value reported by the closed source driver. */
1242 *max_local_size = 32768;
1243 }
1244 return sizeof(uint64_t);
1245
1246 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1247 if (ret) {
1248 uint64_t *max_input_size = ret;
1249 /* Value reported by the closed source driver. */
1250 *max_input_size = 1024;
1251 }
1252 return sizeof(uint64_t);
1253
1254 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1255 if (ret) {
1256 uint64_t *max_mem_alloc_size = ret;
1257
1258 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1259 }
1260 return sizeof(uint64_t);
1261
1262 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1263 if (ret) {
1264 uint32_t *max_clock_frequency = ret;
1265 *max_clock_frequency = rscreen->info.max_shader_clock;
1266 }
1267 return sizeof(uint32_t);
1268
1269 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1270 if (ret) {
1271 uint32_t *max_compute_units = ret;
1272 *max_compute_units = rscreen->info.num_good_compute_units;
1273 }
1274 return sizeof(uint32_t);
1275
1276 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1277 if (ret) {
1278 uint32_t *images_supported = ret;
1279 *images_supported = 0;
1280 }
1281 return sizeof(uint32_t);
1282 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1283 break; /* unused */
1284 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1285 if (ret) {
1286 uint32_t *subgroup_size = ret;
1287 *subgroup_size = r600_wavefront_size(rscreen->family);
1288 }
1289 return sizeof(uint32_t);
1290 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1291 if (ret) {
1292 uint64_t *max_variable_threads_per_block = ret;
1293 if (ir_type == PIPE_SHADER_IR_TGSI)
1294 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1295 else
1296 *max_variable_threads_per_block = 0;
1297 }
1298 return sizeof(uint64_t);
1299 }
1300
1301 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1302 return 0;
1303 }
1304
1305 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1306 {
1307 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1308
1309 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1310 rscreen->info.clock_crystal_freq;
1311 }
1312
1313 static void r600_fence_reference(struct pipe_screen *screen,
1314 struct pipe_fence_handle **dst,
1315 struct pipe_fence_handle *src)
1316 {
1317 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1318 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1319 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1320
1321 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1322 ws->fence_reference(&(*rdst)->gfx, NULL);
1323 ws->fence_reference(&(*rdst)->sdma, NULL);
1324 FREE(*rdst);
1325 }
1326 *rdst = rsrc;
1327 }
1328
1329 static boolean r600_fence_finish(struct pipe_screen *screen,
1330 struct pipe_context *ctx,
1331 struct pipe_fence_handle *fence,
1332 uint64_t timeout)
1333 {
1334 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1335 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1336 struct r600_common_context *rctx;
1337 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1338
1339 ctx = threaded_context_unwrap_sync(ctx);
1340 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1341
1342 if (rfence->sdma) {
1343 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1344 return false;
1345
1346 /* Recompute the timeout after waiting. */
1347 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1348 int64_t time = os_time_get_nano();
1349 timeout = abs_timeout > time ? abs_timeout - time : 0;
1350 }
1351 }
1352
1353 if (!rfence->gfx)
1354 return true;
1355
1356 /* Flush the gfx IB if it hasn't been flushed yet. */
1357 if (rctx &&
1358 rfence->gfx_unflushed.ctx == rctx &&
1359 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1360 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1361 rfence->gfx_unflushed.ctx = NULL;
1362
1363 if (!timeout)
1364 return false;
1365
1366 /* Recompute the timeout after all that. */
1367 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1368 int64_t time = os_time_get_nano();
1369 timeout = abs_timeout > time ? abs_timeout - time : 0;
1370 }
1371 }
1372
1373 return rws->fence_wait(rws, rfence->gfx, timeout);
1374 }
1375
1376 static void r600_query_memory_info(struct pipe_screen *screen,
1377 struct pipe_memory_info *info)
1378 {
1379 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1380 struct radeon_winsys *ws = rscreen->ws;
1381 unsigned vram_usage, gtt_usage;
1382
1383 info->total_device_memory = rscreen->info.vram_size / 1024;
1384 info->total_staging_memory = rscreen->info.gart_size / 1024;
1385
1386 /* The real TTM memory usage is somewhat random, because:
1387 *
1388 * 1) TTM delays freeing memory, because it can only free it after
1389 * fences expire.
1390 *
1391 * 2) The memory usage can be really low if big VRAM evictions are
1392 * taking place, but the real usage is well above the size of VRAM.
1393 *
1394 * Instead, return statistics of this process.
1395 */
1396 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1397 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1398
1399 info->avail_device_memory =
1400 vram_usage <= info->total_device_memory ?
1401 info->total_device_memory - vram_usage : 0;
1402 info->avail_staging_memory =
1403 gtt_usage <= info->total_staging_memory ?
1404 info->total_staging_memory - gtt_usage : 0;
1405
1406 info->device_memory_evicted =
1407 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1408
1409 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1410 info->nr_device_memory_evictions =
1411 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1412 else
1413 /* Just return the number of evicted 64KB pages. */
1414 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1415 }
1416
1417 struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
1418 const struct pipe_resource *templ)
1419 {
1420 if (templ->target == PIPE_BUFFER) {
1421 return si_buffer_create(screen, templ, 256);
1422 } else {
1423 return si_texture_create(screen, templ);
1424 }
1425 }
1426
1427 bool si_common_screen_init(struct r600_common_screen *rscreen,
1428 struct radeon_winsys *ws)
1429 {
1430 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1431 struct utsname uname_data;
1432 const char *chip_name;
1433
1434 ws->query_info(ws, &rscreen->info);
1435 rscreen->ws = ws;
1436
1437 if ((chip_name = r600_get_marketing_name(ws)))
1438 snprintf(family_name, sizeof(family_name), "%s / ",
1439 r600_get_family_name(rscreen) + 4);
1440 else
1441 chip_name = r600_get_family_name(rscreen);
1442
1443 if (uname(&uname_data) == 0)
1444 snprintf(kernel_version, sizeof(kernel_version),
1445 " / %s", uname_data.release);
1446
1447 if (HAVE_LLVM > 0) {
1448 snprintf(llvm_string, sizeof(llvm_string),
1449 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1450 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1451 }
1452
1453 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1454 "%s (%sDRM %i.%i.%i%s%s)",
1455 chip_name, family_name, rscreen->info.drm_major,
1456 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1457 kernel_version, llvm_string);
1458
1459 rscreen->b.get_name = r600_get_name;
1460 rscreen->b.get_vendor = r600_get_vendor;
1461 rscreen->b.get_device_vendor = r600_get_device_vendor;
1462 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1463 rscreen->b.get_compute_param = r600_get_compute_param;
1464 rscreen->b.get_paramf = r600_get_paramf;
1465 rscreen->b.get_timestamp = r600_get_timestamp;
1466 rscreen->b.fence_finish = r600_fence_finish;
1467 rscreen->b.fence_reference = r600_fence_reference;
1468 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1469 rscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
1470 rscreen->b.query_memory_info = r600_query_memory_info;
1471
1472 if (rscreen->info.has_hw_decode) {
1473 rscreen->b.get_video_param = si_vid_get_video_param;
1474 rscreen->b.is_video_format_supported = si_vid_is_format_supported;
1475 } else {
1476 rscreen->b.get_video_param = r600_get_video_param;
1477 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1478 }
1479
1480 si_init_screen_texture_functions(rscreen);
1481 si_init_screen_query_functions(rscreen);
1482
1483 rscreen->family = rscreen->info.family;
1484 rscreen->chip_class = rscreen->info.chip_class;
1485 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1486 rscreen->has_rbplus = false;
1487 rscreen->rbplus_allowed = false;
1488
1489 r600_disk_cache_create(rscreen);
1490
1491 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1492
1493 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1494 if (rscreen->force_aniso >= 0) {
1495 printf("radeon: Forcing anisotropy filter to %ix\n",
1496 /* round down to a power of two */
1497 1 << util_logbase2(rscreen->force_aniso));
1498 }
1499
1500 util_format_s3tc_init();
1501 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1502 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1503
1504 if (rscreen->debug_flags & DBG_INFO) {
1505 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1506 rscreen->info.pci_domain, rscreen->info.pci_bus,
1507 rscreen->info.pci_dev, rscreen->info.pci_func);
1508 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1509 printf("family = %i (%s)\n", rscreen->info.family,
1510 r600_get_family_name(rscreen));
1511 printf("chip_class = %i\n", rscreen->info.chip_class);
1512 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1513 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1514 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1515 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1516 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1517 printf("max_alloc_size = %i MB\n",
1518 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1519 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1520 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1521 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1522 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1523 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1524 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1525 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1526 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1527 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1528 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1529 printf("me_fw_feature = %i\n", rscreen->info.me_fw_feature);
1530 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1531 printf("pfp_fw_feature = %i\n", rscreen->info.pfp_fw_feature);
1532 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1533 printf("ce_fw_feature = %i\n", rscreen->info.ce_fw_feature);
1534 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1535 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1536 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1537 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1538 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1539 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1540 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1541
1542 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1543 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1544 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1545 printf("max_se = %i\n", rscreen->info.max_se);
1546 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1547
1548 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1549 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1550 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1551 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1552 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1553 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1554 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1555 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1556 }
1557 return true;
1558 }
1559
1560 void si_destroy_common_screen(struct r600_common_screen *rscreen)
1561 {
1562 si_perfcounters_destroy(rscreen);
1563 si_gpu_load_kill_thread(rscreen);
1564
1565 mtx_destroy(&rscreen->gpu_load_mutex);
1566 mtx_destroy(&rscreen->aux_context_lock);
1567 rscreen->aux_context->destroy(rscreen->aux_context);
1568
1569 slab_destroy_parent(&rscreen->pool_transfers);
1570
1571 disk_cache_destroy(rscreen->disk_shader_cache);
1572 rscreen->ws->destroy(rscreen->ws);
1573 FREE(rscreen);
1574 }
1575
1576 bool si_can_dump_shader(struct r600_common_screen *rscreen,
1577 unsigned processor)
1578 {
1579 return rscreen->debug_flags & (1 << processor);
1580 }
1581
1582 bool si_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1583 {
1584 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1585 si_can_dump_shader(rscreen, processor);
1586 }
1587
1588 void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1589 uint64_t offset, uint64_t size, unsigned value)
1590 {
1591 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1592
1593 mtx_lock(&rscreen->aux_context_lock);
1594 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1595 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1596 mtx_unlock(&rscreen->aux_context_lock);
1597 }