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gallium/radeon: add and use radeon_info::max_alloc_size (v2)
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50 };
51
52 /*
53 * shader binary helpers.
54 */
55 void radeon_shader_binary_init(struct radeon_shader_binary *b)
56 {
57 memset(b, 0, sizeof(*b));
58 }
59
60 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
61 {
62 if (!b)
63 return;
64 FREE(b->code);
65 FREE(b->config);
66 FREE(b->rodata);
67 FREE(b->global_symbol_offsets);
68 FREE(b->relocs);
69 FREE(b->disasm_string);
70 FREE(b->llvm_ir_string);
71 }
72
73 /*
74 * pipe_context
75 */
76
77 void r600_draw_rectangle(struct blitter_context *blitter,
78 int x1, int y1, int x2, int y2, float depth,
79 enum blitter_attrib_type type,
80 const union pipe_color_union *attrib)
81 {
82 struct r600_common_context *rctx =
83 (struct r600_common_context*)util_blitter_get_pipe(blitter);
84 struct pipe_viewport_state viewport;
85 struct pipe_resource *buf = NULL;
86 unsigned offset = 0;
87 float *vb;
88
89 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
90 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
91 return;
92 }
93
94 /* Some operations (like color resolve on r6xx) don't work
95 * with the conventional primitive types.
96 * One that works is PT_RECTLIST, which we use here. */
97
98 /* setup viewport */
99 viewport.scale[0] = 1.0f;
100 viewport.scale[1] = 1.0f;
101 viewport.scale[2] = 1.0f;
102 viewport.translate[0] = 0.0f;
103 viewport.translate[1] = 0.0f;
104 viewport.translate[2] = 0.0f;
105 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
106
107 /* Upload vertices. The hw rectangle has only 3 vertices,
108 * I guess the 4th one is derived from the first 3.
109 * The vertex specification should match u_blitter's vertex element state. */
110 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
111 if (!buf)
112 return;
113
114 vb[0] = x1;
115 vb[1] = y1;
116 vb[2] = depth;
117 vb[3] = 1;
118
119 vb[8] = x1;
120 vb[9] = y2;
121 vb[10] = depth;
122 vb[11] = 1;
123
124 vb[16] = x2;
125 vb[17] = y1;
126 vb[18] = depth;
127 vb[19] = 1;
128
129 if (attrib) {
130 memcpy(vb+4, attrib->f, sizeof(float)*4);
131 memcpy(vb+12, attrib->f, sizeof(float)*4);
132 memcpy(vb+20, attrib->f, sizeof(float)*4);
133 }
134
135 /* draw */
136 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
137 R600_PRIM_RECTANGLE_LIST, 3, 2);
138 pipe_resource_reference(&buf, NULL);
139 }
140
141 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
142 struct r600_resource *dst, struct r600_resource *src)
143 {
144 uint64_t vram = 0, gtt = 0;
145
146 if (dst) {
147 if (dst->domains & RADEON_DOMAIN_VRAM)
148 vram += dst->buf->size;
149 else if (dst->domains & RADEON_DOMAIN_GTT)
150 gtt += dst->buf->size;
151 }
152 if (src) {
153 if (src->domains & RADEON_DOMAIN_VRAM)
154 vram += src->buf->size;
155 else if (src->domains & RADEON_DOMAIN_GTT)
156 gtt += src->buf->size;
157 }
158
159 /* Flush the GFX IB if DMA depends on it. */
160 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
161 ((dst &&
162 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
163 RADEON_USAGE_READWRITE)) ||
164 (src &&
165 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
166 RADEON_USAGE_WRITE))))
167 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
168
169 /* Flush if there's not enough space, or if the memory usage per IB
170 * is too large.
171 */
172 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
173 !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
174 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
175 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
176 }
177
178 /* If GPUVM is not supported, the CS checker needs 2 entries
179 * in the buffer list per packet, which has to be done manually.
180 */
181 if (ctx->screen->info.has_virtual_memory) {
182 if (dst)
183 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
184 RADEON_USAGE_WRITE,
185 RADEON_PRIO_SDMA_BUFFER);
186 if (src)
187 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
188 RADEON_USAGE_READ,
189 RADEON_PRIO_SDMA_BUFFER);
190 }
191 }
192
193 /* This is required to prevent read-after-write hazards. */
194 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
195 {
196 struct radeon_winsys_cs *cs = rctx->dma.cs;
197
198 /* done at the end of DMA calls, so increment this. */
199 rctx->num_dma_calls++;
200
201 /* IBs using too little memory are limited by the IB submission overhead.
202 * IBs using too much memory are limited by the kernel/TTM overhead.
203 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
204 *
205 * This heuristic makes sure that DMA requests are executed
206 * very soon after the call is made and lowers memory usage.
207 * It improves texture upload performance by keeping the DMA
208 * engine busy while uploads are being submitted.
209 */
210 if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
211 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
212 return;
213 }
214
215 r600_need_dma_space(rctx, 1, NULL, NULL);
216
217 if (!radeon_emitted(cs, 0)) /* empty queue */
218 return;
219
220 /* NOP waits for idle on Evergreen and later. */
221 if (rctx->chip_class >= CIK)
222 radeon_emit(cs, 0x00000000); /* NOP */
223 else if (rctx->chip_class >= EVERGREEN)
224 radeon_emit(cs, 0xf0000000); /* NOP */
225 else {
226 /* TODO: R600-R700 should use the FENCE packet.
227 * CS checker support is required. */
228 }
229 }
230
231 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
232 {
233 }
234
235 void r600_preflush_suspend_features(struct r600_common_context *ctx)
236 {
237 /* suspend queries */
238 if (!LIST_IS_EMPTY(&ctx->active_queries))
239 r600_suspend_queries(ctx);
240
241 ctx->streamout.suspended = false;
242 if (ctx->streamout.begin_emitted) {
243 r600_emit_streamout_end(ctx);
244 ctx->streamout.suspended = true;
245 }
246 }
247
248 void r600_postflush_resume_features(struct r600_common_context *ctx)
249 {
250 if (ctx->streamout.suspended) {
251 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
252 r600_streamout_buffers_dirty(ctx);
253 }
254
255 /* resume queries */
256 if (!LIST_IS_EMPTY(&ctx->active_queries))
257 r600_resume_queries(ctx);
258 }
259
260 static void r600_flush_from_st(struct pipe_context *ctx,
261 struct pipe_fence_handle **fence,
262 unsigned flags)
263 {
264 struct pipe_screen *screen = ctx->screen;
265 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
266 unsigned rflags = 0;
267 struct pipe_fence_handle *gfx_fence = NULL;
268 struct pipe_fence_handle *sdma_fence = NULL;
269
270 if (flags & PIPE_FLUSH_END_OF_FRAME)
271 rflags |= RADEON_FLUSH_END_OF_FRAME;
272
273 if (rctx->dma.cs) {
274 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
275 }
276 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
277
278 /* Both engines can signal out of order, so we need to keep both fences. */
279 if (gfx_fence || sdma_fence) {
280 struct r600_multi_fence *multi_fence =
281 CALLOC_STRUCT(r600_multi_fence);
282 if (!multi_fence)
283 return;
284
285 multi_fence->reference.count = 1;
286 multi_fence->gfx = gfx_fence;
287 multi_fence->sdma = sdma_fence;
288
289 screen->fence_reference(screen, fence, NULL);
290 *fence = (struct pipe_fence_handle*)multi_fence;
291 }
292 }
293
294 static void r600_flush_dma_ring(void *ctx, unsigned flags,
295 struct pipe_fence_handle **fence)
296 {
297 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
298 struct radeon_winsys_cs *cs = rctx->dma.cs;
299 struct radeon_saved_cs saved;
300 bool check_vm =
301 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
302 rctx->check_vm_faults;
303
304 if (!radeon_emitted(cs, 0)) {
305 if (fence)
306 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
307 return;
308 }
309
310 if (check_vm)
311 radeon_save_cs(rctx->ws, cs, &saved);
312
313 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
314 if (fence)
315 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
316
317 if (check_vm) {
318 /* Use conservative timeout 800ms, after which we won't wait any
319 * longer and assume the GPU is hung.
320 */
321 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
322
323 rctx->check_vm_faults(rctx, &saved, RING_DMA);
324 radeon_clear_saved_cs(&saved);
325 }
326 }
327
328 /**
329 * Store a linearized copy of all chunks of \p cs together with the buffer
330 * list in \p saved.
331 */
332 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
333 struct radeon_saved_cs *saved)
334 {
335 void *buf;
336 unsigned i;
337
338 /* Save the IB chunks. */
339 saved->num_dw = cs->prev_dw + cs->current.cdw;
340 saved->ib = MALLOC(4 * saved->num_dw);
341 if (!saved->ib)
342 goto oom;
343
344 buf = saved->ib;
345 for (i = 0; i < cs->num_prev; ++i) {
346 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
347 buf += cs->prev[i].cdw;
348 }
349 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
350
351 /* Save the buffer list. */
352 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
353 saved->bo_list = CALLOC(saved->bo_count,
354 sizeof(saved->bo_list[0]));
355 if (!saved->bo_list) {
356 FREE(saved->ib);
357 goto oom;
358 }
359 ws->cs_get_buffer_list(cs, saved->bo_list);
360
361 return;
362
363 oom:
364 fprintf(stderr, "%s: out of memory\n", __func__);
365 memset(saved, 0, sizeof(*saved));
366 }
367
368 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
369 {
370 unsigned i;
371
372 FREE(saved->ib);
373
374 for (i = 0; i < saved->bo_count; i++)
375 pb_reference(&saved->bo_list[i].buf, NULL);
376 FREE(saved->bo_list);
377
378 memset(saved, 0, sizeof(*saved));
379 }
380
381 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
382 {
383 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
384 unsigned latest = rctx->ws->query_value(rctx->ws,
385 RADEON_GPU_RESET_COUNTER);
386
387 if (rctx->gpu_reset_counter == latest)
388 return PIPE_NO_RESET;
389
390 rctx->gpu_reset_counter = latest;
391 return PIPE_UNKNOWN_CONTEXT_RESET;
392 }
393
394 static void r600_set_debug_callback(struct pipe_context *ctx,
395 const struct pipe_debug_callback *cb)
396 {
397 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
398
399 if (cb)
400 rctx->debug = *cb;
401 else
402 memset(&rctx->debug, 0, sizeof(rctx->debug));
403 }
404
405 bool r600_common_context_init(struct r600_common_context *rctx,
406 struct r600_common_screen *rscreen)
407 {
408 util_slab_create(&rctx->pool_transfers,
409 sizeof(struct r600_transfer), 64,
410 UTIL_SLAB_SINGLETHREADED);
411
412 rctx->screen = rscreen;
413 rctx->ws = rscreen->ws;
414 rctx->family = rscreen->family;
415 rctx->chip_class = rscreen->chip_class;
416
417 if (rscreen->chip_class >= CIK)
418 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
419 else if (rscreen->chip_class >= EVERGREEN)
420 rctx->max_db = 8;
421 else
422 rctx->max_db = 4;
423
424 rctx->b.invalidate_resource = r600_invalidate_resource;
425 rctx->b.transfer_map = u_transfer_map_vtbl;
426 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
427 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
428 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
429 rctx->b.memory_barrier = r600_memory_barrier;
430 rctx->b.flush = r600_flush_from_st;
431 rctx->b.set_debug_callback = r600_set_debug_callback;
432
433 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
434 rctx->b.get_device_reset_status = r600_get_reset_status;
435 rctx->gpu_reset_counter =
436 rctx->ws->query_value(rctx->ws,
437 RADEON_GPU_RESET_COUNTER);
438 }
439
440 LIST_INITHEAD(&rctx->texture_buffers);
441
442 r600_init_context_texture_functions(rctx);
443 r600_init_viewport_functions(rctx);
444 r600_streamout_init(rctx);
445 r600_query_init(rctx);
446 cayman_init_msaa(&rctx->b);
447
448 rctx->allocator_zeroed_memory =
449 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
450 0, PIPE_USAGE_DEFAULT, true);
451 if (!rctx->allocator_zeroed_memory)
452 return false;
453
454 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
455 PIPE_BIND_INDEX_BUFFER |
456 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
457 if (!rctx->uploader)
458 return false;
459
460 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
461 if (!rctx->ctx)
462 return false;
463
464 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
465 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
466 r600_flush_dma_ring,
467 rctx);
468 rctx->dma.flush = r600_flush_dma_ring;
469 }
470
471 return true;
472 }
473
474 void r600_common_context_cleanup(struct r600_common_context *rctx)
475 {
476 unsigned i,j;
477
478 /* Release DCC stats. */
479 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
480 assert(!rctx->dcc_stats[i].query_active);
481
482 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
483 if (rctx->dcc_stats[i].ps_stats[j])
484 rctx->b.destroy_query(&rctx->b,
485 rctx->dcc_stats[i].ps_stats[j]);
486
487 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
488 }
489
490 if (rctx->gfx.cs)
491 rctx->ws->cs_destroy(rctx->gfx.cs);
492 if (rctx->dma.cs)
493 rctx->ws->cs_destroy(rctx->dma.cs);
494 if (rctx->ctx)
495 rctx->ws->ctx_destroy(rctx->ctx);
496
497 if (rctx->uploader) {
498 u_upload_destroy(rctx->uploader);
499 }
500
501 util_slab_destroy(&rctx->pool_transfers);
502
503 if (rctx->allocator_zeroed_memory) {
504 u_suballocator_destroy(rctx->allocator_zeroed_memory);
505 }
506 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
507 }
508
509 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
510 {
511 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
512 struct r600_resource *rr = (struct r600_resource *)r;
513
514 if (!r) {
515 return;
516 }
517
518 /*
519 * The idea is to compute a gross estimate of memory requirement of
520 * each draw call. After each draw call, memory will be precisely
521 * accounted. So the uncertainty is only on the current draw call.
522 * In practice this gave very good estimate (+/- 10% of the target
523 * memory limit).
524 */
525 if (rr->domains & RADEON_DOMAIN_VRAM)
526 rctx->vram += rr->buf->size;
527 else if (rr->domains & RADEON_DOMAIN_GTT)
528 rctx->gtt += rr->buf->size;
529 }
530
531 /*
532 * pipe_screen
533 */
534
535 static const struct debug_named_value common_debug_options[] = {
536 /* logging */
537 { "tex", DBG_TEX, "Print texture info" },
538 { "compute", DBG_COMPUTE, "Print compute info" },
539 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
540 { "info", DBG_INFO, "Print driver information" },
541
542 /* shaders */
543 { "fs", DBG_FS, "Print fetch shaders" },
544 { "vs", DBG_VS, "Print vertex shaders" },
545 { "gs", DBG_GS, "Print geometry shaders" },
546 { "ps", DBG_PS, "Print pixel shaders" },
547 { "cs", DBG_CS, "Print compute shaders" },
548 { "tcs", DBG_TCS, "Print tessellation control shaders" },
549 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
550 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
551 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
552 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
553 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
554
555 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
556
557 /* features */
558 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
559 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
560 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
561 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
562 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
563 { "notiling", DBG_NO_TILING, "Disable tiling" },
564 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
565 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
566 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
567 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
568 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
569 { "nodcc", DBG_NO_DCC, "Disable DCC." },
570 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
571 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
572 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
573 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
574 { "noce", DBG_NO_CE, "Disable the constant engine"},
575 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
576 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
577
578 DEBUG_NAMED_VALUE_END /* must be last */
579 };
580
581 static const char* r600_get_vendor(struct pipe_screen* pscreen)
582 {
583 return "X.Org";
584 }
585
586 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
587 {
588 return "AMD";
589 }
590
591 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
592 {
593 switch (rscreen->info.family) {
594 case CHIP_R600: return "AMD R600";
595 case CHIP_RV610: return "AMD RV610";
596 case CHIP_RV630: return "AMD RV630";
597 case CHIP_RV670: return "AMD RV670";
598 case CHIP_RV620: return "AMD RV620";
599 case CHIP_RV635: return "AMD RV635";
600 case CHIP_RS780: return "AMD RS780";
601 case CHIP_RS880: return "AMD RS880";
602 case CHIP_RV770: return "AMD RV770";
603 case CHIP_RV730: return "AMD RV730";
604 case CHIP_RV710: return "AMD RV710";
605 case CHIP_RV740: return "AMD RV740";
606 case CHIP_CEDAR: return "AMD CEDAR";
607 case CHIP_REDWOOD: return "AMD REDWOOD";
608 case CHIP_JUNIPER: return "AMD JUNIPER";
609 case CHIP_CYPRESS: return "AMD CYPRESS";
610 case CHIP_HEMLOCK: return "AMD HEMLOCK";
611 case CHIP_PALM: return "AMD PALM";
612 case CHIP_SUMO: return "AMD SUMO";
613 case CHIP_SUMO2: return "AMD SUMO2";
614 case CHIP_BARTS: return "AMD BARTS";
615 case CHIP_TURKS: return "AMD TURKS";
616 case CHIP_CAICOS: return "AMD CAICOS";
617 case CHIP_CAYMAN: return "AMD CAYMAN";
618 case CHIP_ARUBA: return "AMD ARUBA";
619 case CHIP_TAHITI: return "AMD TAHITI";
620 case CHIP_PITCAIRN: return "AMD PITCAIRN";
621 case CHIP_VERDE: return "AMD CAPE VERDE";
622 case CHIP_OLAND: return "AMD OLAND";
623 case CHIP_HAINAN: return "AMD HAINAN";
624 case CHIP_BONAIRE: return "AMD BONAIRE";
625 case CHIP_KAVERI: return "AMD KAVERI";
626 case CHIP_KABINI: return "AMD KABINI";
627 case CHIP_HAWAII: return "AMD HAWAII";
628 case CHIP_MULLINS: return "AMD MULLINS";
629 case CHIP_TONGA: return "AMD TONGA";
630 case CHIP_ICELAND: return "AMD ICELAND";
631 case CHIP_CARRIZO: return "AMD CARRIZO";
632 case CHIP_FIJI: return "AMD FIJI";
633 case CHIP_POLARIS10: return "AMD POLARIS10";
634 case CHIP_POLARIS11: return "AMD POLARIS11";
635 case CHIP_STONEY: return "AMD STONEY";
636 default: return "AMD unknown";
637 }
638 }
639
640 static const char* r600_get_name(struct pipe_screen* pscreen)
641 {
642 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
643
644 return rscreen->renderer_string;
645 }
646
647 static float r600_get_paramf(struct pipe_screen* pscreen,
648 enum pipe_capf param)
649 {
650 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
651
652 switch (param) {
653 case PIPE_CAPF_MAX_LINE_WIDTH:
654 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
655 case PIPE_CAPF_MAX_POINT_WIDTH:
656 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
657 if (rscreen->family >= CHIP_CEDAR)
658 return 16384.0f;
659 else
660 return 8192.0f;
661 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
662 return 16.0f;
663 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
664 return 16.0f;
665 case PIPE_CAPF_GUARD_BAND_LEFT:
666 case PIPE_CAPF_GUARD_BAND_TOP:
667 case PIPE_CAPF_GUARD_BAND_RIGHT:
668 case PIPE_CAPF_GUARD_BAND_BOTTOM:
669 return 0.0f;
670 }
671 return 0.0f;
672 }
673
674 static int r600_get_video_param(struct pipe_screen *screen,
675 enum pipe_video_profile profile,
676 enum pipe_video_entrypoint entrypoint,
677 enum pipe_video_cap param)
678 {
679 switch (param) {
680 case PIPE_VIDEO_CAP_SUPPORTED:
681 return vl_profile_supported(screen, profile, entrypoint);
682 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
683 return 1;
684 case PIPE_VIDEO_CAP_MAX_WIDTH:
685 case PIPE_VIDEO_CAP_MAX_HEIGHT:
686 return vl_video_buffer_max_size(screen);
687 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
688 return PIPE_FORMAT_NV12;
689 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
690 return false;
691 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
692 return false;
693 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
694 return true;
695 case PIPE_VIDEO_CAP_MAX_LEVEL:
696 return vl_level_supported(screen, profile);
697 default:
698 return 0;
699 }
700 }
701
702 const char *r600_get_llvm_processor_name(enum radeon_family family)
703 {
704 switch (family) {
705 case CHIP_R600:
706 case CHIP_RV630:
707 case CHIP_RV635:
708 case CHIP_RV670:
709 return "r600";
710 case CHIP_RV610:
711 case CHIP_RV620:
712 case CHIP_RS780:
713 case CHIP_RS880:
714 return "rs880";
715 case CHIP_RV710:
716 return "rv710";
717 case CHIP_RV730:
718 return "rv730";
719 case CHIP_RV740:
720 case CHIP_RV770:
721 return "rv770";
722 case CHIP_PALM:
723 case CHIP_CEDAR:
724 return "cedar";
725 case CHIP_SUMO:
726 case CHIP_SUMO2:
727 return "sumo";
728 case CHIP_REDWOOD:
729 return "redwood";
730 case CHIP_JUNIPER:
731 return "juniper";
732 case CHIP_HEMLOCK:
733 case CHIP_CYPRESS:
734 return "cypress";
735 case CHIP_BARTS:
736 return "barts";
737 case CHIP_TURKS:
738 return "turks";
739 case CHIP_CAICOS:
740 return "caicos";
741 case CHIP_CAYMAN:
742 case CHIP_ARUBA:
743 return "cayman";
744
745 case CHIP_TAHITI: return "tahiti";
746 case CHIP_PITCAIRN: return "pitcairn";
747 case CHIP_VERDE: return "verde";
748 case CHIP_OLAND: return "oland";
749 case CHIP_HAINAN: return "hainan";
750 case CHIP_BONAIRE: return "bonaire";
751 case CHIP_KABINI: return "kabini";
752 case CHIP_KAVERI: return "kaveri";
753 case CHIP_HAWAII: return "hawaii";
754 case CHIP_MULLINS:
755 return "mullins";
756 case CHIP_TONGA: return "tonga";
757 case CHIP_ICELAND: return "iceland";
758 case CHIP_CARRIZO: return "carrizo";
759 #if HAVE_LLVM <= 0x0307
760 case CHIP_FIJI: return "tonga";
761 case CHIP_STONEY: return "carrizo";
762 #else
763 case CHIP_FIJI: return "fiji";
764 case CHIP_STONEY: return "stoney";
765 #endif
766 #if HAVE_LLVM <= 0x0308
767 case CHIP_POLARIS10: return "tonga";
768 case CHIP_POLARIS11: return "tonga";
769 #else
770 case CHIP_POLARIS10: return "polaris10";
771 case CHIP_POLARIS11: return "polaris11";
772 #endif
773 default: return "";
774 }
775 }
776
777 static int r600_get_compute_param(struct pipe_screen *screen,
778 enum pipe_shader_ir ir_type,
779 enum pipe_compute_cap param,
780 void *ret)
781 {
782 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
783
784 //TODO: select these params by asic
785 switch (param) {
786 case PIPE_COMPUTE_CAP_IR_TARGET: {
787 const char *gpu;
788 const char *triple;
789 if (rscreen->family <= CHIP_ARUBA) {
790 triple = "r600--";
791 } else {
792 triple = "amdgcn--";
793 }
794 switch(rscreen->family) {
795 /* Clang < 3.6 is missing Hainan in its list of
796 * GPUs, so we need to use the name of a similar GPU.
797 */
798 default:
799 gpu = r600_get_llvm_processor_name(rscreen->family);
800 break;
801 }
802 if (ret) {
803 sprintf(ret, "%s-%s", gpu, triple);
804 }
805 /* +2 for dash and terminating NIL byte */
806 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
807 }
808 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
809 if (ret) {
810 uint64_t *grid_dimension = ret;
811 grid_dimension[0] = 3;
812 }
813 return 1 * sizeof(uint64_t);
814
815 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
816 if (ret) {
817 uint64_t *grid_size = ret;
818 grid_size[0] = 65535;
819 grid_size[1] = 65535;
820 grid_size[2] = 65535;
821 }
822 return 3 * sizeof(uint64_t) ;
823
824 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
825 if (ret) {
826 uint64_t *block_size = ret;
827 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
828 ir_type == PIPE_SHADER_IR_TGSI) {
829 block_size[0] = 2048;
830 block_size[1] = 2048;
831 block_size[2] = 2048;
832 } else {
833 block_size[0] = 256;
834 block_size[1] = 256;
835 block_size[2] = 256;
836 }
837 }
838 return 3 * sizeof(uint64_t);
839
840 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
841 if (ret) {
842 uint64_t *max_threads_per_block = ret;
843 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
844 ir_type == PIPE_SHADER_IR_TGSI)
845 *max_threads_per_block = 2048;
846 else
847 *max_threads_per_block = 256;
848 }
849 return sizeof(uint64_t);
850
851 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
852 if (ret) {
853 uint64_t *max_global_size = ret;
854 uint64_t max_mem_alloc_size;
855
856 r600_get_compute_param(screen, ir_type,
857 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
858 &max_mem_alloc_size);
859
860 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
861 * 1/4 of the MAX_GLOBAL_SIZE. Since the
862 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
863 * make sure we never report more than
864 * 4 * MAX_MEM_ALLOC_SIZE.
865 */
866 *max_global_size = MIN2(4 * max_mem_alloc_size,
867 MAX2(rscreen->info.gart_size,
868 rscreen->info.vram_size));
869 }
870 return sizeof(uint64_t);
871
872 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
873 if (ret) {
874 uint64_t *max_local_size = ret;
875 /* Value reported by the closed source driver. */
876 *max_local_size = 32768;
877 }
878 return sizeof(uint64_t);
879
880 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
881 if (ret) {
882 uint64_t *max_input_size = ret;
883 /* Value reported by the closed source driver. */
884 *max_input_size = 1024;
885 }
886 return sizeof(uint64_t);
887
888 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
889 if (ret) {
890 uint64_t *max_mem_alloc_size = ret;
891
892 *max_mem_alloc_size = rscreen->info.max_alloc_size;
893 }
894 return sizeof(uint64_t);
895
896 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
897 if (ret) {
898 uint32_t *max_clock_frequency = ret;
899 *max_clock_frequency = rscreen->info.max_shader_clock;
900 }
901 return sizeof(uint32_t);
902
903 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
904 if (ret) {
905 uint32_t *max_compute_units = ret;
906 *max_compute_units = rscreen->info.num_good_compute_units;
907 }
908 return sizeof(uint32_t);
909
910 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
911 if (ret) {
912 uint32_t *images_supported = ret;
913 *images_supported = 0;
914 }
915 return sizeof(uint32_t);
916 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
917 break; /* unused */
918 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
919 if (ret) {
920 uint32_t *subgroup_size = ret;
921 *subgroup_size = r600_wavefront_size(rscreen->family);
922 }
923 return sizeof(uint32_t);
924 }
925
926 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
927 return 0;
928 }
929
930 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
931 {
932 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
933
934 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
935 rscreen->info.clock_crystal_freq;
936 }
937
938 static void r600_fence_reference(struct pipe_screen *screen,
939 struct pipe_fence_handle **dst,
940 struct pipe_fence_handle *src)
941 {
942 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
943 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
944 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
945
946 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
947 ws->fence_reference(&(*rdst)->gfx, NULL);
948 ws->fence_reference(&(*rdst)->sdma, NULL);
949 FREE(*rdst);
950 }
951 *rdst = rsrc;
952 }
953
954 static boolean r600_fence_finish(struct pipe_screen *screen,
955 struct pipe_fence_handle *fence,
956 uint64_t timeout)
957 {
958 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
959 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
960 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
961
962 if (rfence->sdma) {
963 if (!rws->fence_wait(rws, rfence->sdma, timeout))
964 return false;
965
966 /* Recompute the timeout after waiting. */
967 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
968 int64_t time = os_time_get_nano();
969 timeout = abs_timeout > time ? abs_timeout - time : 0;
970 }
971 }
972
973 if (!rfence->gfx)
974 return true;
975
976 return rws->fence_wait(rws, rfence->gfx, timeout);
977 }
978
979 static void r600_query_memory_info(struct pipe_screen *screen,
980 struct pipe_memory_info *info)
981 {
982 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
983 struct radeon_winsys *ws = rscreen->ws;
984 unsigned vram_usage, gtt_usage;
985
986 info->total_device_memory = rscreen->info.vram_size / 1024;
987 info->total_staging_memory = rscreen->info.gart_size / 1024;
988
989 /* The real TTM memory usage is somewhat random, because:
990 *
991 * 1) TTM delays freeing memory, because it can only free it after
992 * fences expire.
993 *
994 * 2) The memory usage can be really low if big VRAM evictions are
995 * taking place, but the real usage is well above the size of VRAM.
996 *
997 * Instead, return statistics of this process.
998 */
999 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1000 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1001
1002 info->avail_device_memory =
1003 vram_usage <= info->total_device_memory ?
1004 info->total_device_memory - vram_usage : 0;
1005 info->avail_staging_memory =
1006 gtt_usage <= info->total_staging_memory ?
1007 info->total_staging_memory - gtt_usage : 0;
1008
1009 info->device_memory_evicted =
1010 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1011 /* Just return the number of evicted 64KB pages. */
1012 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1013 }
1014
1015 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1016 const struct pipe_resource *templ)
1017 {
1018 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1019
1020 if (templ->target == PIPE_BUFFER) {
1021 return r600_buffer_create(screen, templ,
1022 rscreen->info.gart_page_size);
1023 } else {
1024 return r600_texture_create(screen, templ);
1025 }
1026 }
1027
1028 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1029 struct radeon_winsys *ws)
1030 {
1031 char llvm_string[32] = {}, kernel_version[128] = {};
1032 struct utsname uname_data;
1033
1034 ws->query_info(ws, &rscreen->info);
1035
1036 if (uname(&uname_data) == 0)
1037 snprintf(kernel_version, sizeof(kernel_version),
1038 " / %s", uname_data.release);
1039
1040 #if HAVE_LLVM
1041 snprintf(llvm_string, sizeof(llvm_string),
1042 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1043 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1044 #endif
1045
1046 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1047 "%s (DRM %i.%i.%i%s%s)",
1048 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1049 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1050 kernel_version, llvm_string);
1051
1052 rscreen->b.get_name = r600_get_name;
1053 rscreen->b.get_vendor = r600_get_vendor;
1054 rscreen->b.get_device_vendor = r600_get_device_vendor;
1055 rscreen->b.get_compute_param = r600_get_compute_param;
1056 rscreen->b.get_paramf = r600_get_paramf;
1057 rscreen->b.get_timestamp = r600_get_timestamp;
1058 rscreen->b.fence_finish = r600_fence_finish;
1059 rscreen->b.fence_reference = r600_fence_reference;
1060 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1061 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1062 rscreen->b.query_memory_info = r600_query_memory_info;
1063
1064 if (rscreen->info.has_uvd) {
1065 rscreen->b.get_video_param = rvid_get_video_param;
1066 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1067 } else {
1068 rscreen->b.get_video_param = r600_get_video_param;
1069 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1070 }
1071
1072 r600_init_screen_texture_functions(rscreen);
1073 r600_init_screen_query_functions(rscreen);
1074
1075 rscreen->ws = ws;
1076 rscreen->family = rscreen->info.family;
1077 rscreen->chip_class = rscreen->info.chip_class;
1078 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1079
1080 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1081 if (rscreen->force_aniso >= 0) {
1082 printf("radeon: Forcing anisotropy filter to %ix\n",
1083 /* round down to a power of two */
1084 1 << util_logbase2(rscreen->force_aniso));
1085 }
1086
1087 util_format_s3tc_init();
1088 pipe_mutex_init(rscreen->aux_context_lock);
1089 pipe_mutex_init(rscreen->gpu_load_mutex);
1090
1091 if (rscreen->debug_flags & DBG_INFO) {
1092 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1093 printf("family = %i (%s)\n", rscreen->info.family,
1094 r600_get_chip_name(rscreen));
1095 printf("chip_class = %i\n", rscreen->info.chip_class);
1096 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1097 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1098 printf("max_alloc_size = %i MB\n",
1099 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1100 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1101 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1102 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1103 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1104 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1105 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1106 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1107 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1108 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1109 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1110
1111 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1112 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1113 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1114 printf("max_se = %i\n", rscreen->info.max_se);
1115 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1116
1117 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1118 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1119 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1120 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1121 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1122 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1123 }
1124 return true;
1125 }
1126
1127 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1128 {
1129 r600_perfcounters_destroy(rscreen);
1130 r600_gpu_load_kill_thread(rscreen);
1131
1132 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1133 pipe_mutex_destroy(rscreen->aux_context_lock);
1134 rscreen->aux_context->destroy(rscreen->aux_context);
1135
1136 rscreen->ws->destroy(rscreen->ws);
1137 FREE(rscreen);
1138 }
1139
1140 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1141 unsigned processor)
1142 {
1143 switch (processor) {
1144 case PIPE_SHADER_VERTEX:
1145 return (rscreen->debug_flags & DBG_VS) != 0;
1146 case PIPE_SHADER_TESS_CTRL:
1147 return (rscreen->debug_flags & DBG_TCS) != 0;
1148 case PIPE_SHADER_TESS_EVAL:
1149 return (rscreen->debug_flags & DBG_TES) != 0;
1150 case PIPE_SHADER_GEOMETRY:
1151 return (rscreen->debug_flags & DBG_GS) != 0;
1152 case PIPE_SHADER_FRAGMENT:
1153 return (rscreen->debug_flags & DBG_PS) != 0;
1154 case PIPE_SHADER_COMPUTE:
1155 return (rscreen->debug_flags & DBG_CS) != 0;
1156 default:
1157 return false;
1158 }
1159 }
1160
1161 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1162 uint64_t offset, uint64_t size, unsigned value,
1163 enum r600_coherency coher)
1164 {
1165 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1166
1167 pipe_mutex_lock(rscreen->aux_context_lock);
1168 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1169 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1170 pipe_mutex_unlock(rscreen->aux_context_lock);
1171 }