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[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* The number of dwords we already used in the DMA so far. */
111 num_dw += ctx->rings.dma.cs->cdw;
112 /* Flush if there's not enough space. */
113 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
114 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
115 }
116 }
117
118 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
119 {
120 }
121
122 void r600_preflush_suspend_features(struct r600_common_context *ctx)
123 {
124 /* Disable render condition. */
125 ctx->saved_render_cond = NULL;
126 ctx->saved_render_cond_cond = FALSE;
127 ctx->saved_render_cond_mode = 0;
128 if (ctx->current_render_cond) {
129 ctx->saved_render_cond = ctx->current_render_cond;
130 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
131 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
132 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
133 }
134
135 /* suspend queries */
136 ctx->nontimer_queries_suspended = false;
137 if (ctx->num_cs_dw_nontimer_queries_suspend) {
138 r600_suspend_nontimer_queries(ctx);
139 ctx->nontimer_queries_suspended = true;
140 }
141
142 ctx->streamout.suspended = false;
143 if (ctx->streamout.begin_emitted) {
144 r600_emit_streamout_end(ctx);
145 ctx->streamout.suspended = true;
146 }
147 }
148
149 void r600_postflush_resume_features(struct r600_common_context *ctx)
150 {
151 if (ctx->streamout.suspended) {
152 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
153 r600_streamout_buffers_dirty(ctx);
154 }
155
156 /* resume queries */
157 if (ctx->nontimer_queries_suspended) {
158 r600_resume_nontimer_queries(ctx);
159 }
160
161 /* Re-enable render condition. */
162 if (ctx->saved_render_cond) {
163 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
164 ctx->saved_render_cond_cond,
165 ctx->saved_render_cond_mode);
166 }
167 }
168
169 static void r600_flush_from_st(struct pipe_context *ctx,
170 struct pipe_fence_handle **fence,
171 unsigned flags)
172 {
173 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
174 unsigned rflags = 0;
175
176 if (flags & PIPE_FLUSH_END_OF_FRAME)
177 rflags |= RADEON_FLUSH_END_OF_FRAME;
178
179 if (rctx->rings.dma.cs) {
180 rctx->rings.dma.flush(rctx, rflags, NULL);
181 }
182 rctx->rings.gfx.flush(rctx, rflags, fence);
183 }
184
185 static void r600_flush_dma_ring(void *ctx, unsigned flags,
186 struct pipe_fence_handle **fence)
187 {
188 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
189 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
190
191 if (!cs->cdw) {
192 return;
193 }
194
195 rctx->rings.dma.flushing = true;
196 rctx->ws->cs_flush(cs, flags, fence, 0);
197 rctx->rings.dma.flushing = false;
198 }
199
200 bool r600_common_context_init(struct r600_common_context *rctx,
201 struct r600_common_screen *rscreen)
202 {
203 util_slab_create(&rctx->pool_transfers,
204 sizeof(struct r600_transfer), 64,
205 UTIL_SLAB_SINGLETHREADED);
206
207 rctx->screen = rscreen;
208 rctx->ws = rscreen->ws;
209 rctx->family = rscreen->family;
210 rctx->chip_class = rscreen->chip_class;
211
212 if (rscreen->family == CHIP_HAWAII)
213 rctx->max_db = 16;
214 else if (rscreen->chip_class >= EVERGREEN)
215 rctx->max_db = 8;
216 else
217 rctx->max_db = 4;
218
219 rctx->b.transfer_map = u_transfer_map_vtbl;
220 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
221 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
222 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
223 rctx->b.memory_barrier = r600_memory_barrier;
224 rctx->b.flush = r600_flush_from_st;
225
226 LIST_INITHEAD(&rctx->texture_buffers);
227
228 r600_init_context_texture_functions(rctx);
229 r600_streamout_init(rctx);
230 r600_query_init(rctx);
231 cayman_init_msaa(&rctx->b);
232
233 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
234 0, PIPE_USAGE_DEFAULT, TRUE);
235 if (!rctx->allocator_so_filled_size)
236 return false;
237
238 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
239 PIPE_BIND_INDEX_BUFFER |
240 PIPE_BIND_CONSTANT_BUFFER);
241 if (!rctx->uploader)
242 return false;
243
244 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
245 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
246 r600_flush_dma_ring,
247 rctx, NULL);
248 rctx->rings.dma.flush = r600_flush_dma_ring;
249 }
250
251 return true;
252 }
253
254 void r600_common_context_cleanup(struct r600_common_context *rctx)
255 {
256 if (rctx->rings.gfx.cs) {
257 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
258 }
259 if (rctx->rings.dma.cs) {
260 rctx->ws->cs_destroy(rctx->rings.dma.cs);
261 }
262
263 if (rctx->uploader) {
264 u_upload_destroy(rctx->uploader);
265 }
266
267 util_slab_destroy(&rctx->pool_transfers);
268
269 if (rctx->allocator_so_filled_size) {
270 u_suballocator_destroy(rctx->allocator_so_filled_size);
271 }
272 }
273
274 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
275 {
276 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
277 struct r600_resource *rr = (struct r600_resource *)r;
278
279 if (r == NULL) {
280 return;
281 }
282
283 /*
284 * The idea is to compute a gross estimate of memory requirement of
285 * each draw call. After each draw call, memory will be precisely
286 * accounted. So the uncertainty is only on the current draw call.
287 * In practice this gave very good estimate (+/- 10% of the target
288 * memory limit).
289 */
290 if (rr->domains & RADEON_DOMAIN_GTT) {
291 rctx->gtt += rr->buf->size;
292 }
293 if (rr->domains & RADEON_DOMAIN_VRAM) {
294 rctx->vram += rr->buf->size;
295 }
296 }
297
298 /*
299 * pipe_screen
300 */
301
302 static const struct debug_named_value common_debug_options[] = {
303 /* logging */
304 { "tex", DBG_TEX, "Print texture info" },
305 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
306 { "compute", DBG_COMPUTE, "Print compute info" },
307 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
308 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
309
310 /* shaders */
311 { "fs", DBG_FS, "Print fetch shaders" },
312 { "vs", DBG_VS, "Print vertex shaders" },
313 { "gs", DBG_GS, "Print geometry shaders" },
314 { "ps", DBG_PS, "Print pixel shaders" },
315 { "cs", DBG_CS, "Print compute shaders" },
316
317 /* features */
318 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
319 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
320 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
321 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
322 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
323 { "notiling", DBG_NO_TILING, "Disable tiling" },
324 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
325 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
326
327 DEBUG_NAMED_VALUE_END /* must be last */
328 };
329
330 static const char* r600_get_vendor(struct pipe_screen* pscreen)
331 {
332 return "X.Org";
333 }
334
335 static const char* r600_get_name(struct pipe_screen* pscreen)
336 {
337 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
338
339 switch (rscreen->family) {
340 case CHIP_R600: return "AMD R600";
341 case CHIP_RV610: return "AMD RV610";
342 case CHIP_RV630: return "AMD RV630";
343 case CHIP_RV670: return "AMD RV670";
344 case CHIP_RV620: return "AMD RV620";
345 case CHIP_RV635: return "AMD RV635";
346 case CHIP_RS780: return "AMD RS780";
347 case CHIP_RS880: return "AMD RS880";
348 case CHIP_RV770: return "AMD RV770";
349 case CHIP_RV730: return "AMD RV730";
350 case CHIP_RV710: return "AMD RV710";
351 case CHIP_RV740: return "AMD RV740";
352 case CHIP_CEDAR: return "AMD CEDAR";
353 case CHIP_REDWOOD: return "AMD REDWOOD";
354 case CHIP_JUNIPER: return "AMD JUNIPER";
355 case CHIP_CYPRESS: return "AMD CYPRESS";
356 case CHIP_HEMLOCK: return "AMD HEMLOCK";
357 case CHIP_PALM: return "AMD PALM";
358 case CHIP_SUMO: return "AMD SUMO";
359 case CHIP_SUMO2: return "AMD SUMO2";
360 case CHIP_BARTS: return "AMD BARTS";
361 case CHIP_TURKS: return "AMD TURKS";
362 case CHIP_CAICOS: return "AMD CAICOS";
363 case CHIP_CAYMAN: return "AMD CAYMAN";
364 case CHIP_ARUBA: return "AMD ARUBA";
365 case CHIP_TAHITI: return "AMD TAHITI";
366 case CHIP_PITCAIRN: return "AMD PITCAIRN";
367 case CHIP_VERDE: return "AMD CAPE VERDE";
368 case CHIP_OLAND: return "AMD OLAND";
369 case CHIP_HAINAN: return "AMD HAINAN";
370 case CHIP_BONAIRE: return "AMD BONAIRE";
371 case CHIP_KAVERI: return "AMD KAVERI";
372 case CHIP_KABINI: return "AMD KABINI";
373 case CHIP_HAWAII: return "AMD HAWAII";
374 case CHIP_MULLINS: return "AMD MULLINS";
375 default: return "AMD unknown";
376 }
377 }
378
379 static float r600_get_paramf(struct pipe_screen* pscreen,
380 enum pipe_capf param)
381 {
382 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
383
384 switch (param) {
385 case PIPE_CAPF_MAX_LINE_WIDTH:
386 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
387 case PIPE_CAPF_MAX_POINT_WIDTH:
388 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
389 if (rscreen->family >= CHIP_CEDAR)
390 return 16384.0f;
391 else
392 return 8192.0f;
393 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
394 return 16.0f;
395 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
396 return 16.0f;
397 case PIPE_CAPF_GUARD_BAND_LEFT:
398 case PIPE_CAPF_GUARD_BAND_TOP:
399 case PIPE_CAPF_GUARD_BAND_RIGHT:
400 case PIPE_CAPF_GUARD_BAND_BOTTOM:
401 return 0.0f;
402 }
403 return 0.0f;
404 }
405
406 static int r600_get_video_param(struct pipe_screen *screen,
407 enum pipe_video_profile profile,
408 enum pipe_video_entrypoint entrypoint,
409 enum pipe_video_cap param)
410 {
411 switch (param) {
412 case PIPE_VIDEO_CAP_SUPPORTED:
413 return vl_profile_supported(screen, profile, entrypoint);
414 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
415 return 1;
416 case PIPE_VIDEO_CAP_MAX_WIDTH:
417 case PIPE_VIDEO_CAP_MAX_HEIGHT:
418 return vl_video_buffer_max_size(screen);
419 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
420 return PIPE_FORMAT_NV12;
421 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
422 return false;
423 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
424 return false;
425 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
426 return true;
427 case PIPE_VIDEO_CAP_MAX_LEVEL:
428 return vl_level_supported(screen, profile);
429 default:
430 return 0;
431 }
432 }
433
434 const char *r600_get_llvm_processor_name(enum radeon_family family)
435 {
436 switch (family) {
437 case CHIP_R600:
438 case CHIP_RV630:
439 case CHIP_RV635:
440 case CHIP_RV670:
441 return "r600";
442 case CHIP_RV610:
443 case CHIP_RV620:
444 case CHIP_RS780:
445 case CHIP_RS880:
446 return "rs880";
447 case CHIP_RV710:
448 return "rv710";
449 case CHIP_RV730:
450 return "rv730";
451 case CHIP_RV740:
452 case CHIP_RV770:
453 return "rv770";
454 case CHIP_PALM:
455 case CHIP_CEDAR:
456 return "cedar";
457 case CHIP_SUMO:
458 case CHIP_SUMO2:
459 return "sumo";
460 case CHIP_REDWOOD:
461 return "redwood";
462 case CHIP_JUNIPER:
463 return "juniper";
464 case CHIP_HEMLOCK:
465 case CHIP_CYPRESS:
466 return "cypress";
467 case CHIP_BARTS:
468 return "barts";
469 case CHIP_TURKS:
470 return "turks";
471 case CHIP_CAICOS:
472 return "caicos";
473 case CHIP_CAYMAN:
474 case CHIP_ARUBA:
475 return "cayman";
476
477 case CHIP_TAHITI: return "tahiti";
478 case CHIP_PITCAIRN: return "pitcairn";
479 case CHIP_VERDE: return "verde";
480 case CHIP_OLAND: return "oland";
481 case CHIP_HAINAN: return "hainan";
482 case CHIP_BONAIRE: return "bonaire";
483 case CHIP_KABINI: return "kabini";
484 case CHIP_KAVERI: return "kaveri";
485 case CHIP_HAWAII: return "hawaii";
486 case CHIP_MULLINS:
487 #if HAVE_LLVM >= 0x0305
488 return "mullins";
489 #else
490 return "kabini";
491 #endif
492 default: return "";
493 }
494 }
495
496 static int r600_get_compute_param(struct pipe_screen *screen,
497 enum pipe_compute_cap param,
498 void *ret)
499 {
500 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
501
502 //TODO: select these params by asic
503 switch (param) {
504 case PIPE_COMPUTE_CAP_IR_TARGET: {
505 const char *gpu;
506 const char *triple;
507 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
508 triple = "r600--";
509 } else {
510 triple = "amdgcn--";
511 }
512 switch(rscreen->family) {
513 /* Clang < 3.6 is missing Hainan in its list of
514 * GPUs, so we need to use the name of a similar GPU.
515 */
516 #if HAVE_LLVM < 0x0306
517 case CHIP_HAINAN:
518 gpu = "oland";
519 break;
520 #endif
521 default:
522 gpu = r600_get_llvm_processor_name(rscreen->family);
523 break;
524 }
525 if (ret) {
526 sprintf(ret, "%s-%s", gpu, triple);
527
528 }
529 return (strlen(triple) + strlen(gpu)) * sizeof(char);
530 }
531 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
532 if (ret) {
533 uint64_t *grid_dimension = ret;
534 grid_dimension[0] = 3;
535 }
536 return 1 * sizeof(uint64_t);
537
538 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
539 if (ret) {
540 uint64_t *grid_size = ret;
541 grid_size[0] = 65535;
542 grid_size[1] = 65535;
543 grid_size[2] = 1;
544 }
545 return 3 * sizeof(uint64_t) ;
546
547 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
548 if (ret) {
549 uint64_t *block_size = ret;
550 block_size[0] = 256;
551 block_size[1] = 256;
552 block_size[2] = 256;
553 }
554 return 3 * sizeof(uint64_t);
555
556 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
557 if (ret) {
558 uint64_t *max_threads_per_block = ret;
559 *max_threads_per_block = 256;
560 }
561 return sizeof(uint64_t);
562
563 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
564 if (ret) {
565 uint64_t *max_global_size = ret;
566 uint64_t max_mem_alloc_size;
567
568 r600_get_compute_param(screen,
569 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
570 &max_mem_alloc_size);
571
572 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
573 * 1/4 of the MAX_GLOBAL_SIZE. Since the
574 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
575 * make sure we never report more than
576 * 4 * MAX_MEM_ALLOC_SIZE.
577 */
578 *max_global_size = MIN2(4 * max_mem_alloc_size,
579 rscreen->info.gart_size +
580 rscreen->info.vram_size);
581 }
582 return sizeof(uint64_t);
583
584 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
585 if (ret) {
586 uint64_t *max_local_size = ret;
587 /* Value reported by the closed source driver. */
588 *max_local_size = 32768;
589 }
590 return sizeof(uint64_t);
591
592 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
593 if (ret) {
594 uint64_t *max_input_size = ret;
595 /* Value reported by the closed source driver. */
596 *max_input_size = 1024;
597 }
598 return sizeof(uint64_t);
599
600 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
601 if (ret) {
602 uint64_t *max_mem_alloc_size = ret;
603
604 /* XXX: The limit in older kernels is 256 MB. We
605 * should add a query here for newer kernels.
606 */
607 *max_mem_alloc_size = 256 * 1024 * 1024;
608 }
609 return sizeof(uint64_t);
610
611 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
612 if (ret) {
613 uint32_t *max_clock_frequency = ret;
614 *max_clock_frequency = rscreen->info.max_sclk;
615 }
616 return sizeof(uint32_t);
617
618 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
619 if (ret) {
620 uint32_t *max_compute_units = ret;
621 *max_compute_units = rscreen->info.max_compute_units;
622 }
623 return sizeof(uint32_t);
624
625 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
626 if (ret) {
627 uint32_t *images_supported = ret;
628 *images_supported = 0;
629 }
630 return sizeof(uint32_t);
631 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
632 break; /* unused */
633 }
634
635 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
636 return 0;
637 }
638
639 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
640 {
641 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
642
643 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
644 rscreen->info.r600_clock_crystal_freq;
645 }
646
647 static int r600_get_driver_query_info(struct pipe_screen *screen,
648 unsigned index,
649 struct pipe_driver_query_info *info)
650 {
651 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
652 struct pipe_driver_query_info list[] = {
653 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
654 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
655 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
656 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
657 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
658 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
659 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
660 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
661 };
662
663 if (!info)
664 return Elements(list);
665
666 if (index >= Elements(list))
667 return 0;
668
669 *info = list[index];
670 return 1;
671 }
672
673 static void r600_fence_reference(struct pipe_screen *screen,
674 struct pipe_fence_handle **ptr,
675 struct pipe_fence_handle *fence)
676 {
677 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
678
679 rws->fence_reference(ptr, fence);
680 }
681
682 static boolean r600_fence_signalled(struct pipe_screen *screen,
683 struct pipe_fence_handle *fence)
684 {
685 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
686
687 return rws->fence_wait(rws, fence, 0);
688 }
689
690 static boolean r600_fence_finish(struct pipe_screen *screen,
691 struct pipe_fence_handle *fence,
692 uint64_t timeout)
693 {
694 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
695
696 return rws->fence_wait(rws, fence, timeout);
697 }
698
699 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
700 uint32_t tiling_config)
701 {
702 switch ((tiling_config & 0xe) >> 1) {
703 case 0:
704 rscreen->tiling_info.num_channels = 1;
705 break;
706 case 1:
707 rscreen->tiling_info.num_channels = 2;
708 break;
709 case 2:
710 rscreen->tiling_info.num_channels = 4;
711 break;
712 case 3:
713 rscreen->tiling_info.num_channels = 8;
714 break;
715 default:
716 return false;
717 }
718
719 switch ((tiling_config & 0x30) >> 4) {
720 case 0:
721 rscreen->tiling_info.num_banks = 4;
722 break;
723 case 1:
724 rscreen->tiling_info.num_banks = 8;
725 break;
726 default:
727 return false;
728
729 }
730 switch ((tiling_config & 0xc0) >> 6) {
731 case 0:
732 rscreen->tiling_info.group_bytes = 256;
733 break;
734 case 1:
735 rscreen->tiling_info.group_bytes = 512;
736 break;
737 default:
738 return false;
739 }
740 return true;
741 }
742
743 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
744 uint32_t tiling_config)
745 {
746 switch (tiling_config & 0xf) {
747 case 0:
748 rscreen->tiling_info.num_channels = 1;
749 break;
750 case 1:
751 rscreen->tiling_info.num_channels = 2;
752 break;
753 case 2:
754 rscreen->tiling_info.num_channels = 4;
755 break;
756 case 3:
757 rscreen->tiling_info.num_channels = 8;
758 break;
759 default:
760 return false;
761 }
762
763 switch ((tiling_config & 0xf0) >> 4) {
764 case 0:
765 rscreen->tiling_info.num_banks = 4;
766 break;
767 case 1:
768 rscreen->tiling_info.num_banks = 8;
769 break;
770 case 2:
771 rscreen->tiling_info.num_banks = 16;
772 break;
773 default:
774 return false;
775 }
776
777 switch ((tiling_config & 0xf00) >> 8) {
778 case 0:
779 rscreen->tiling_info.group_bytes = 256;
780 break;
781 case 1:
782 rscreen->tiling_info.group_bytes = 512;
783 break;
784 default:
785 return false;
786 }
787 return true;
788 }
789
790 static bool r600_init_tiling(struct r600_common_screen *rscreen)
791 {
792 uint32_t tiling_config = rscreen->info.r600_tiling_config;
793
794 /* set default group bytes, overridden by tiling info ioctl */
795 if (rscreen->chip_class <= R700) {
796 rscreen->tiling_info.group_bytes = 256;
797 } else {
798 rscreen->tiling_info.group_bytes = 512;
799 }
800
801 if (!tiling_config)
802 return true;
803
804 if (rscreen->chip_class <= R700) {
805 return r600_interpret_tiling(rscreen, tiling_config);
806 } else {
807 return evergreen_interpret_tiling(rscreen, tiling_config);
808 }
809 }
810
811 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
812 const struct pipe_resource *templ)
813 {
814 if (templ->target == PIPE_BUFFER) {
815 return r600_buffer_create(screen, templ, 4096);
816 } else {
817 return r600_texture_create(screen, templ);
818 }
819 }
820
821 bool r600_common_screen_init(struct r600_common_screen *rscreen,
822 struct radeon_winsys *ws)
823 {
824 ws->query_info(ws, &rscreen->info);
825
826 rscreen->b.get_name = r600_get_name;
827 rscreen->b.get_vendor = r600_get_vendor;
828 rscreen->b.get_compute_param = r600_get_compute_param;
829 rscreen->b.get_paramf = r600_get_paramf;
830 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
831 rscreen->b.get_timestamp = r600_get_timestamp;
832 rscreen->b.fence_finish = r600_fence_finish;
833 rscreen->b.fence_reference = r600_fence_reference;
834 rscreen->b.fence_signalled = r600_fence_signalled;
835 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
836
837 if (rscreen->info.has_uvd) {
838 rscreen->b.get_video_param = rvid_get_video_param;
839 rscreen->b.is_video_format_supported = rvid_is_format_supported;
840 } else {
841 rscreen->b.get_video_param = r600_get_video_param;
842 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
843 }
844
845 r600_init_screen_texture_functions(rscreen);
846
847 rscreen->ws = ws;
848 rscreen->family = rscreen->info.family;
849 rscreen->chip_class = rscreen->info.chip_class;
850 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
851
852 if (!r600_init_tiling(rscreen)) {
853 return false;
854 }
855 util_format_s3tc_init();
856 pipe_mutex_init(rscreen->aux_context_lock);
857
858 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
859 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
860 PIPE_BIND_CUSTOM,
861 PIPE_USAGE_STAGING,
862 4096);
863 if (rscreen->trace_bo) {
864 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
865 PIPE_TRANSFER_UNSYNCHRONIZED);
866 }
867 }
868
869 return true;
870 }
871
872 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
873 {
874 pipe_mutex_destroy(rscreen->aux_context_lock);
875 rscreen->aux_context->destroy(rscreen->aux_context);
876
877 if (rscreen->trace_bo) {
878 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
879 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
880 }
881
882 rscreen->ws->destroy(rscreen->ws);
883 FREE(rscreen);
884 }
885
886 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
887 {
888 struct tgsi_parse_context parse;
889
890 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
891 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
892 return ~0;
893 }
894 return parse.FullHeader.Processor.Processor;
895 }
896
897 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
898 const struct tgsi_token *tokens)
899 {
900 /* Compute shader don't have tgsi_tokens */
901 if (!tokens)
902 return (rscreen->debug_flags & DBG_CS) != 0;
903
904 switch (tgsi_get_processor_type(tokens)) {
905 case TGSI_PROCESSOR_VERTEX:
906 return (rscreen->debug_flags & DBG_VS) != 0;
907 case TGSI_PROCESSOR_GEOMETRY:
908 return (rscreen->debug_flags & DBG_GS) != 0;
909 case TGSI_PROCESSOR_FRAGMENT:
910 return (rscreen->debug_flags & DBG_PS) != 0;
911 case TGSI_PROCESSOR_COMPUTE:
912 return (rscreen->debug_flags & DBG_CS) != 0;
913 default:
914 return false;
915 }
916 }
917
918 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
919 unsigned offset, unsigned size, unsigned value,
920 bool is_framebuffer)
921 {
922 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
923
924 pipe_mutex_lock(rscreen->aux_context_lock);
925 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
926 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
927 pipe_mutex_unlock(rscreen->aux_context_lock);
928 }