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radeonsi: don't use llvm.AMDIL.fraction for FRC and DFRAC
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= RADEON_MAX_CMDBUF_DWORDS);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->nontimer_queries_suspended = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 ctx->nontimer_queries_suspended = true;
139 }
140
141 ctx->streamout.suspended = false;
142 if (ctx->streamout.begin_emitted) {
143 r600_emit_streamout_end(ctx);
144 ctx->streamout.suspended = true;
145 }
146 }
147
148 void r600_postflush_resume_features(struct r600_common_context *ctx)
149 {
150 if (ctx->streamout.suspended) {
151 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
152 r600_streamout_buffers_dirty(ctx);
153 }
154
155 /* resume queries */
156 if (ctx->nontimer_queries_suspended) {
157 r600_resume_nontimer_queries(ctx);
158 }
159
160 /* Re-enable render condition. */
161 if (ctx->saved_render_cond) {
162 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
163 ctx->saved_render_cond_cond,
164 ctx->saved_render_cond_mode);
165 }
166 }
167
168 static void r600_flush_from_st(struct pipe_context *ctx,
169 struct pipe_fence_handle **fence,
170 unsigned flags)
171 {
172 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
173 unsigned rflags = 0;
174
175 if (flags & PIPE_FLUSH_END_OF_FRAME)
176 rflags |= RADEON_FLUSH_END_OF_FRAME;
177
178 if (rctx->rings.dma.cs) {
179 rctx->rings.dma.flush(rctx, rflags, NULL);
180 }
181 rctx->rings.gfx.flush(rctx, rflags, fence);
182 }
183
184 static void r600_flush_dma_ring(void *ctx, unsigned flags,
185 struct pipe_fence_handle **fence)
186 {
187 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
188 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
189
190 if (!cs->cdw) {
191 return;
192 }
193
194 rctx->rings.dma.flushing = true;
195 rctx->ws->cs_flush(cs, flags, fence, 0);
196 rctx->rings.dma.flushing = false;
197 }
198
199 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
200 {
201 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
202 unsigned latest = rctx->ws->query_value(rctx->ws,
203 RADEON_GPU_RESET_COUNTER);
204
205 if (rctx->gpu_reset_counter == latest)
206 return PIPE_NO_RESET;
207
208 rctx->gpu_reset_counter = latest;
209 return PIPE_UNKNOWN_CONTEXT_RESET;
210 }
211
212 bool r600_common_context_init(struct r600_common_context *rctx,
213 struct r600_common_screen *rscreen)
214 {
215 util_slab_create(&rctx->pool_transfers,
216 sizeof(struct r600_transfer), 64,
217 UTIL_SLAB_SINGLETHREADED);
218
219 rctx->screen = rscreen;
220 rctx->ws = rscreen->ws;
221 rctx->family = rscreen->family;
222 rctx->chip_class = rscreen->chip_class;
223
224 if (rscreen->family == CHIP_HAWAII)
225 rctx->max_db = 16;
226 else if (rscreen->chip_class >= EVERGREEN)
227 rctx->max_db = 8;
228 else
229 rctx->max_db = 4;
230
231 rctx->b.transfer_map = u_transfer_map_vtbl;
232 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
233 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
234 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
235 rctx->b.memory_barrier = r600_memory_barrier;
236 rctx->b.flush = r600_flush_from_st;
237
238 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
239 rctx->b.get_device_reset_status = r600_get_reset_status;
240 rctx->gpu_reset_counter =
241 rctx->ws->query_value(rctx->ws,
242 RADEON_GPU_RESET_COUNTER);
243 }
244
245 LIST_INITHEAD(&rctx->texture_buffers);
246
247 r600_init_context_texture_functions(rctx);
248 r600_streamout_init(rctx);
249 r600_query_init(rctx);
250 cayman_init_msaa(&rctx->b);
251
252 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
253 0, PIPE_USAGE_DEFAULT, TRUE);
254 if (!rctx->allocator_so_filled_size)
255 return false;
256
257 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
258 PIPE_BIND_INDEX_BUFFER |
259 PIPE_BIND_CONSTANT_BUFFER);
260 if (!rctx->uploader)
261 return false;
262
263 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
264 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
265 r600_flush_dma_ring,
266 rctx, NULL);
267 rctx->rings.dma.flush = r600_flush_dma_ring;
268 }
269
270 return true;
271 }
272
273 void r600_common_context_cleanup(struct r600_common_context *rctx)
274 {
275 if (rctx->rings.gfx.cs) {
276 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
277 }
278 if (rctx->rings.dma.cs) {
279 rctx->ws->cs_destroy(rctx->rings.dma.cs);
280 }
281
282 if (rctx->uploader) {
283 u_upload_destroy(rctx->uploader);
284 }
285
286 util_slab_destroy(&rctx->pool_transfers);
287
288 if (rctx->allocator_so_filled_size) {
289 u_suballocator_destroy(rctx->allocator_so_filled_size);
290 }
291 }
292
293 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
294 {
295 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
296 struct r600_resource *rr = (struct r600_resource *)r;
297
298 if (r == NULL) {
299 return;
300 }
301
302 /*
303 * The idea is to compute a gross estimate of memory requirement of
304 * each draw call. After each draw call, memory will be precisely
305 * accounted. So the uncertainty is only on the current draw call.
306 * In practice this gave very good estimate (+/- 10% of the target
307 * memory limit).
308 */
309 if (rr->domains & RADEON_DOMAIN_GTT) {
310 rctx->gtt += rr->buf->size;
311 }
312 if (rr->domains & RADEON_DOMAIN_VRAM) {
313 rctx->vram += rr->buf->size;
314 }
315 }
316
317 /*
318 * pipe_screen
319 */
320
321 static const struct debug_named_value common_debug_options[] = {
322 /* logging */
323 { "tex", DBG_TEX, "Print texture info" },
324 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
325 { "compute", DBG_COMPUTE, "Print compute info" },
326 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
327 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
328 { "info", DBG_INFO, "Print driver information" },
329
330 /* shaders */
331 { "fs", DBG_FS, "Print fetch shaders" },
332 { "vs", DBG_VS, "Print vertex shaders" },
333 { "gs", DBG_GS, "Print geometry shaders" },
334 { "ps", DBG_PS, "Print pixel shaders" },
335 { "cs", DBG_CS, "Print compute shaders" },
336 { "tcs", DBG_TCS, "Print tessellation control shaders" },
337 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
338
339 /* features */
340 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
341 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
342 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
343 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
344 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
345 { "notiling", DBG_NO_TILING, "Disable tiling" },
346 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
347 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
348 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
349
350 DEBUG_NAMED_VALUE_END /* must be last */
351 };
352
353 static const char* r600_get_vendor(struct pipe_screen* pscreen)
354 {
355 return "X.Org";
356 }
357
358 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
359 {
360 return "AMD";
361 }
362
363 static const char* r600_get_name(struct pipe_screen* pscreen)
364 {
365 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
366
367 switch (rscreen->family) {
368 case CHIP_R600: return "AMD R600";
369 case CHIP_RV610: return "AMD RV610";
370 case CHIP_RV630: return "AMD RV630";
371 case CHIP_RV670: return "AMD RV670";
372 case CHIP_RV620: return "AMD RV620";
373 case CHIP_RV635: return "AMD RV635";
374 case CHIP_RS780: return "AMD RS780";
375 case CHIP_RS880: return "AMD RS880";
376 case CHIP_RV770: return "AMD RV770";
377 case CHIP_RV730: return "AMD RV730";
378 case CHIP_RV710: return "AMD RV710";
379 case CHIP_RV740: return "AMD RV740";
380 case CHIP_CEDAR: return "AMD CEDAR";
381 case CHIP_REDWOOD: return "AMD REDWOOD";
382 case CHIP_JUNIPER: return "AMD JUNIPER";
383 case CHIP_CYPRESS: return "AMD CYPRESS";
384 case CHIP_HEMLOCK: return "AMD HEMLOCK";
385 case CHIP_PALM: return "AMD PALM";
386 case CHIP_SUMO: return "AMD SUMO";
387 case CHIP_SUMO2: return "AMD SUMO2";
388 case CHIP_BARTS: return "AMD BARTS";
389 case CHIP_TURKS: return "AMD TURKS";
390 case CHIP_CAICOS: return "AMD CAICOS";
391 case CHIP_CAYMAN: return "AMD CAYMAN";
392 case CHIP_ARUBA: return "AMD ARUBA";
393 case CHIP_TAHITI: return "AMD TAHITI";
394 case CHIP_PITCAIRN: return "AMD PITCAIRN";
395 case CHIP_VERDE: return "AMD CAPE VERDE";
396 case CHIP_OLAND: return "AMD OLAND";
397 case CHIP_HAINAN: return "AMD HAINAN";
398 case CHIP_BONAIRE: return "AMD BONAIRE";
399 case CHIP_KAVERI: return "AMD KAVERI";
400 case CHIP_KABINI: return "AMD KABINI";
401 case CHIP_HAWAII: return "AMD HAWAII";
402 case CHIP_MULLINS: return "AMD MULLINS";
403 default: return "AMD unknown";
404 }
405 }
406
407 static float r600_get_paramf(struct pipe_screen* pscreen,
408 enum pipe_capf param)
409 {
410 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
411
412 switch (param) {
413 case PIPE_CAPF_MAX_LINE_WIDTH:
414 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
415 case PIPE_CAPF_MAX_POINT_WIDTH:
416 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
417 if (rscreen->family >= CHIP_CEDAR)
418 return 16384.0f;
419 else
420 return 8192.0f;
421 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
422 return 16.0f;
423 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
424 return 16.0f;
425 case PIPE_CAPF_GUARD_BAND_LEFT:
426 case PIPE_CAPF_GUARD_BAND_TOP:
427 case PIPE_CAPF_GUARD_BAND_RIGHT:
428 case PIPE_CAPF_GUARD_BAND_BOTTOM:
429 return 0.0f;
430 }
431 return 0.0f;
432 }
433
434 static int r600_get_video_param(struct pipe_screen *screen,
435 enum pipe_video_profile profile,
436 enum pipe_video_entrypoint entrypoint,
437 enum pipe_video_cap param)
438 {
439 switch (param) {
440 case PIPE_VIDEO_CAP_SUPPORTED:
441 return vl_profile_supported(screen, profile, entrypoint);
442 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
443 return 1;
444 case PIPE_VIDEO_CAP_MAX_WIDTH:
445 case PIPE_VIDEO_CAP_MAX_HEIGHT:
446 return vl_video_buffer_max_size(screen);
447 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
448 return PIPE_FORMAT_NV12;
449 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
450 return false;
451 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
452 return false;
453 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
454 return true;
455 case PIPE_VIDEO_CAP_MAX_LEVEL:
456 return vl_level_supported(screen, profile);
457 default:
458 return 0;
459 }
460 }
461
462 const char *r600_get_llvm_processor_name(enum radeon_family family)
463 {
464 switch (family) {
465 case CHIP_R600:
466 case CHIP_RV630:
467 case CHIP_RV635:
468 case CHIP_RV670:
469 return "r600";
470 case CHIP_RV610:
471 case CHIP_RV620:
472 case CHIP_RS780:
473 case CHIP_RS880:
474 return "rs880";
475 case CHIP_RV710:
476 return "rv710";
477 case CHIP_RV730:
478 return "rv730";
479 case CHIP_RV740:
480 case CHIP_RV770:
481 return "rv770";
482 case CHIP_PALM:
483 case CHIP_CEDAR:
484 return "cedar";
485 case CHIP_SUMO:
486 case CHIP_SUMO2:
487 return "sumo";
488 case CHIP_REDWOOD:
489 return "redwood";
490 case CHIP_JUNIPER:
491 return "juniper";
492 case CHIP_HEMLOCK:
493 case CHIP_CYPRESS:
494 return "cypress";
495 case CHIP_BARTS:
496 return "barts";
497 case CHIP_TURKS:
498 return "turks";
499 case CHIP_CAICOS:
500 return "caicos";
501 case CHIP_CAYMAN:
502 case CHIP_ARUBA:
503 return "cayman";
504
505 case CHIP_TAHITI: return "tahiti";
506 case CHIP_PITCAIRN: return "pitcairn";
507 case CHIP_VERDE: return "verde";
508 case CHIP_OLAND: return "oland";
509 case CHIP_HAINAN: return "hainan";
510 case CHIP_BONAIRE: return "bonaire";
511 case CHIP_KABINI: return "kabini";
512 case CHIP_KAVERI: return "kaveri";
513 case CHIP_HAWAII: return "hawaii";
514 case CHIP_MULLINS:
515 #if HAVE_LLVM >= 0x0305
516 return "mullins";
517 #else
518 return "kabini";
519 #endif
520 default: return "";
521 }
522 }
523
524 static int r600_get_compute_param(struct pipe_screen *screen,
525 enum pipe_compute_cap param,
526 void *ret)
527 {
528 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
529
530 //TODO: select these params by asic
531 switch (param) {
532 case PIPE_COMPUTE_CAP_IR_TARGET: {
533 const char *gpu;
534 const char *triple;
535 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
536 triple = "r600--";
537 } else {
538 triple = "amdgcn--";
539 }
540 switch(rscreen->family) {
541 /* Clang < 3.6 is missing Hainan in its list of
542 * GPUs, so we need to use the name of a similar GPU.
543 */
544 #if HAVE_LLVM < 0x0306
545 case CHIP_HAINAN:
546 gpu = "oland";
547 break;
548 #endif
549 default:
550 gpu = r600_get_llvm_processor_name(rscreen->family);
551 break;
552 }
553 if (ret) {
554 sprintf(ret, "%s-%s", gpu, triple);
555 }
556 /* +2 for dash and terminating NIL byte */
557 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
558 }
559 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
560 if (ret) {
561 uint64_t *grid_dimension = ret;
562 grid_dimension[0] = 3;
563 }
564 return 1 * sizeof(uint64_t);
565
566 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
567 if (ret) {
568 uint64_t *grid_size = ret;
569 grid_size[0] = 65535;
570 grid_size[1] = 65535;
571 grid_size[2] = 1;
572 }
573 return 3 * sizeof(uint64_t) ;
574
575 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
576 if (ret) {
577 uint64_t *block_size = ret;
578 block_size[0] = 256;
579 block_size[1] = 256;
580 block_size[2] = 256;
581 }
582 return 3 * sizeof(uint64_t);
583
584 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
585 if (ret) {
586 uint64_t *max_threads_per_block = ret;
587 *max_threads_per_block = 256;
588 }
589 return sizeof(uint64_t);
590
591 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
592 if (ret) {
593 uint64_t *max_global_size = ret;
594 uint64_t max_mem_alloc_size;
595
596 r600_get_compute_param(screen,
597 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
598 &max_mem_alloc_size);
599
600 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
601 * 1/4 of the MAX_GLOBAL_SIZE. Since the
602 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
603 * make sure we never report more than
604 * 4 * MAX_MEM_ALLOC_SIZE.
605 */
606 *max_global_size = MIN2(4 * max_mem_alloc_size,
607 rscreen->info.gart_size +
608 rscreen->info.vram_size);
609 }
610 return sizeof(uint64_t);
611
612 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
613 if (ret) {
614 uint64_t *max_local_size = ret;
615 /* Value reported by the closed source driver. */
616 *max_local_size = 32768;
617 }
618 return sizeof(uint64_t);
619
620 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
621 if (ret) {
622 uint64_t *max_input_size = ret;
623 /* Value reported by the closed source driver. */
624 *max_input_size = 1024;
625 }
626 return sizeof(uint64_t);
627
628 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
629 if (ret) {
630 uint64_t *max_mem_alloc_size = ret;
631
632 /* XXX: The limit in older kernels is 256 MB. We
633 * should add a query here for newer kernels.
634 */
635 *max_mem_alloc_size = 256 * 1024 * 1024;
636 }
637 return sizeof(uint64_t);
638
639 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
640 if (ret) {
641 uint32_t *max_clock_frequency = ret;
642 *max_clock_frequency = rscreen->info.max_sclk;
643 }
644 return sizeof(uint32_t);
645
646 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
647 if (ret) {
648 uint32_t *max_compute_units = ret;
649 *max_compute_units = rscreen->info.max_compute_units;
650 }
651 return sizeof(uint32_t);
652
653 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
654 if (ret) {
655 uint32_t *images_supported = ret;
656 *images_supported = 0;
657 }
658 return sizeof(uint32_t);
659 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
660 break; /* unused */
661 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
662 if (ret) {
663 uint32_t *subgroup_size = ret;
664 *subgroup_size = r600_wavefront_size(rscreen->family);
665 }
666 return sizeof(uint32_t);
667 }
668
669 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
670 return 0;
671 }
672
673 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
674 {
675 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
676
677 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
678 rscreen->info.r600_clock_crystal_freq;
679 }
680
681 static int r600_get_driver_query_info(struct pipe_screen *screen,
682 unsigned index,
683 struct pipe_driver_query_info *info)
684 {
685 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
686 struct pipe_driver_query_info list[] = {
687 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
688 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
689 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
690 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}},
691 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
692 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES},
693 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
694 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
695 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
696 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}},
697 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}},
698 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
699 };
700 unsigned num_queries;
701
702 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
703 num_queries = Elements(list);
704 else
705 num_queries = 8;
706
707 if (!info)
708 return num_queries;
709
710 if (index >= num_queries)
711 return 0;
712
713 *info = list[index];
714 return 1;
715 }
716
717 static void r600_fence_reference(struct pipe_screen *screen,
718 struct pipe_fence_handle **ptr,
719 struct pipe_fence_handle *fence)
720 {
721 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
722
723 rws->fence_reference(ptr, fence);
724 }
725
726 static boolean r600_fence_finish(struct pipe_screen *screen,
727 struct pipe_fence_handle *fence,
728 uint64_t timeout)
729 {
730 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
731
732 return rws->fence_wait(rws, fence, timeout);
733 }
734
735 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
736 uint32_t tiling_config)
737 {
738 switch ((tiling_config & 0xe) >> 1) {
739 case 0:
740 rscreen->tiling_info.num_channels = 1;
741 break;
742 case 1:
743 rscreen->tiling_info.num_channels = 2;
744 break;
745 case 2:
746 rscreen->tiling_info.num_channels = 4;
747 break;
748 case 3:
749 rscreen->tiling_info.num_channels = 8;
750 break;
751 default:
752 return false;
753 }
754
755 switch ((tiling_config & 0x30) >> 4) {
756 case 0:
757 rscreen->tiling_info.num_banks = 4;
758 break;
759 case 1:
760 rscreen->tiling_info.num_banks = 8;
761 break;
762 default:
763 return false;
764
765 }
766 switch ((tiling_config & 0xc0) >> 6) {
767 case 0:
768 rscreen->tiling_info.group_bytes = 256;
769 break;
770 case 1:
771 rscreen->tiling_info.group_bytes = 512;
772 break;
773 default:
774 return false;
775 }
776 return true;
777 }
778
779 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
780 uint32_t tiling_config)
781 {
782 switch (tiling_config & 0xf) {
783 case 0:
784 rscreen->tiling_info.num_channels = 1;
785 break;
786 case 1:
787 rscreen->tiling_info.num_channels = 2;
788 break;
789 case 2:
790 rscreen->tiling_info.num_channels = 4;
791 break;
792 case 3:
793 rscreen->tiling_info.num_channels = 8;
794 break;
795 default:
796 return false;
797 }
798
799 switch ((tiling_config & 0xf0) >> 4) {
800 case 0:
801 rscreen->tiling_info.num_banks = 4;
802 break;
803 case 1:
804 rscreen->tiling_info.num_banks = 8;
805 break;
806 case 2:
807 rscreen->tiling_info.num_banks = 16;
808 break;
809 default:
810 return false;
811 }
812
813 switch ((tiling_config & 0xf00) >> 8) {
814 case 0:
815 rscreen->tiling_info.group_bytes = 256;
816 break;
817 case 1:
818 rscreen->tiling_info.group_bytes = 512;
819 break;
820 default:
821 return false;
822 }
823 return true;
824 }
825
826 static bool r600_init_tiling(struct r600_common_screen *rscreen)
827 {
828 uint32_t tiling_config = rscreen->info.r600_tiling_config;
829
830 /* set default group bytes, overridden by tiling info ioctl */
831 if (rscreen->chip_class <= R700) {
832 rscreen->tiling_info.group_bytes = 256;
833 } else {
834 rscreen->tiling_info.group_bytes = 512;
835 }
836
837 if (!tiling_config)
838 return true;
839
840 if (rscreen->chip_class <= R700) {
841 return r600_interpret_tiling(rscreen, tiling_config);
842 } else {
843 return evergreen_interpret_tiling(rscreen, tiling_config);
844 }
845 }
846
847 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
848 const struct pipe_resource *templ)
849 {
850 if (templ->target == PIPE_BUFFER) {
851 return r600_buffer_create(screen, templ, 4096);
852 } else {
853 return r600_texture_create(screen, templ);
854 }
855 }
856
857 bool r600_common_screen_init(struct r600_common_screen *rscreen,
858 struct radeon_winsys *ws)
859 {
860 ws->query_info(ws, &rscreen->info);
861
862 rscreen->b.get_name = r600_get_name;
863 rscreen->b.get_vendor = r600_get_vendor;
864 rscreen->b.get_device_vendor = r600_get_device_vendor;
865 rscreen->b.get_compute_param = r600_get_compute_param;
866 rscreen->b.get_paramf = r600_get_paramf;
867 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
868 rscreen->b.get_timestamp = r600_get_timestamp;
869 rscreen->b.fence_finish = r600_fence_finish;
870 rscreen->b.fence_reference = r600_fence_reference;
871 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
872 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
873
874 if (rscreen->info.has_uvd) {
875 rscreen->b.get_video_param = rvid_get_video_param;
876 rscreen->b.is_video_format_supported = rvid_is_format_supported;
877 } else {
878 rscreen->b.get_video_param = r600_get_video_param;
879 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
880 }
881
882 r600_init_screen_texture_functions(rscreen);
883
884 rscreen->ws = ws;
885 rscreen->family = rscreen->info.family;
886 rscreen->chip_class = rscreen->info.chip_class;
887 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
888
889 if (!r600_init_tiling(rscreen)) {
890 return false;
891 }
892 util_format_s3tc_init();
893 pipe_mutex_init(rscreen->aux_context_lock);
894 pipe_mutex_init(rscreen->gpu_load_mutex);
895
896 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
897 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
898 PIPE_BIND_CUSTOM,
899 PIPE_USAGE_STAGING,
900 4096);
901 if (rscreen->trace_bo) {
902 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
903 PIPE_TRANSFER_UNSYNCHRONIZED);
904 }
905 }
906
907 if (rscreen->debug_flags & DBG_INFO) {
908 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
909 printf("family = %i\n", rscreen->info.family);
910 printf("chip_class = %i\n", rscreen->info.chip_class);
911 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
912 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
913 printf("max_sclk = %i\n", rscreen->info.max_sclk);
914 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
915 printf("max_se = %i\n", rscreen->info.max_se);
916 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
917 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
918 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
919 printf("has_uvd = %i\n", rscreen->info.has_uvd);
920 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
921 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
922 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
923 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
924 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
925 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
926 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
927 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
928 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
929 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
930 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
931 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
932 }
933 return true;
934 }
935
936 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
937 {
938 r600_gpu_load_kill_thread(rscreen);
939
940 pipe_mutex_destroy(rscreen->gpu_load_mutex);
941 pipe_mutex_destroy(rscreen->aux_context_lock);
942 rscreen->aux_context->destroy(rscreen->aux_context);
943
944 if (rscreen->trace_bo)
945 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
946
947 rscreen->ws->destroy(rscreen->ws);
948 FREE(rscreen);
949 }
950
951 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
952 const struct tgsi_token *tokens)
953 {
954 /* Compute shader don't have tgsi_tokens */
955 if (!tokens)
956 return (rscreen->debug_flags & DBG_CS) != 0;
957
958 switch (tgsi_get_processor_type(tokens)) {
959 case TGSI_PROCESSOR_VERTEX:
960 return (rscreen->debug_flags & DBG_VS) != 0;
961 case TGSI_PROCESSOR_TESS_CTRL:
962 return (rscreen->debug_flags & DBG_TCS) != 0;
963 case TGSI_PROCESSOR_TESS_EVAL:
964 return (rscreen->debug_flags & DBG_TES) != 0;
965 case TGSI_PROCESSOR_GEOMETRY:
966 return (rscreen->debug_flags & DBG_GS) != 0;
967 case TGSI_PROCESSOR_FRAGMENT:
968 return (rscreen->debug_flags & DBG_PS) != 0;
969 case TGSI_PROCESSOR_COMPUTE:
970 return (rscreen->debug_flags & DBG_CS) != 0;
971 default:
972 return false;
973 }
974 }
975
976 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
977 unsigned offset, unsigned size, unsigned value,
978 bool is_framebuffer)
979 {
980 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
981
982 pipe_mutex_lock(rscreen->aux_context_lock);
983 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
984 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
985 pipe_mutex_unlock(rscreen->aux_context_lock);
986 }