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gallium/radeon: display cumulative results for some driver queries
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->queries_suspended_for_flush = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 r600_suspend_timer_queries(ctx);
139 ctx->queries_suspended_for_flush = true;
140 }
141
142 ctx->streamout.suspended = false;
143 if (ctx->streamout.begin_emitted) {
144 r600_emit_streamout_end(ctx);
145 ctx->streamout.suspended = true;
146 }
147 }
148
149 void r600_postflush_resume_features(struct r600_common_context *ctx)
150 {
151 if (ctx->streamout.suspended) {
152 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
153 r600_streamout_buffers_dirty(ctx);
154 }
155
156 /* resume queries */
157 if (ctx->queries_suspended_for_flush) {
158 r600_resume_nontimer_queries(ctx);
159 r600_resume_timer_queries(ctx);
160 }
161
162 /* Re-enable render condition. */
163 if (ctx->saved_render_cond) {
164 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
165 ctx->saved_render_cond_cond,
166 ctx->saved_render_cond_mode);
167 }
168 }
169
170 static void r600_flush_from_st(struct pipe_context *ctx,
171 struct pipe_fence_handle **fence,
172 unsigned flags)
173 {
174 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
175 unsigned rflags = 0;
176
177 if (flags & PIPE_FLUSH_END_OF_FRAME)
178 rflags |= RADEON_FLUSH_END_OF_FRAME;
179
180 if (rctx->rings.dma.cs) {
181 rctx->rings.dma.flush(rctx, rflags, NULL);
182 }
183 rctx->rings.gfx.flush(rctx, rflags, fence);
184 }
185
186 static void r600_flush_dma_ring(void *ctx, unsigned flags,
187 struct pipe_fence_handle **fence)
188 {
189 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
190 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
191
192 if (!cs->cdw) {
193 return;
194 }
195
196 rctx->rings.dma.flushing = true;
197 rctx->ws->cs_flush(cs, flags, fence, 0);
198 rctx->rings.dma.flushing = false;
199 }
200
201 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
202 {
203 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
204 unsigned latest = rctx->ws->query_value(rctx->ws,
205 RADEON_GPU_RESET_COUNTER);
206
207 if (rctx->gpu_reset_counter == latest)
208 return PIPE_NO_RESET;
209
210 rctx->gpu_reset_counter = latest;
211 return PIPE_UNKNOWN_CONTEXT_RESET;
212 }
213
214 bool r600_common_context_init(struct r600_common_context *rctx,
215 struct r600_common_screen *rscreen)
216 {
217 util_slab_create(&rctx->pool_transfers,
218 sizeof(struct r600_transfer), 64,
219 UTIL_SLAB_SINGLETHREADED);
220
221 rctx->screen = rscreen;
222 rctx->ws = rscreen->ws;
223 rctx->family = rscreen->family;
224 rctx->chip_class = rscreen->chip_class;
225
226 if (rscreen->family == CHIP_HAWAII)
227 rctx->max_db = 16;
228 else if (rscreen->chip_class >= EVERGREEN)
229 rctx->max_db = 8;
230 else
231 rctx->max_db = 4;
232
233 rctx->b.transfer_map = u_transfer_map_vtbl;
234 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
235 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
236 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
237 rctx->b.memory_barrier = r600_memory_barrier;
238 rctx->b.flush = r600_flush_from_st;
239
240 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
241 rctx->b.get_device_reset_status = r600_get_reset_status;
242 rctx->gpu_reset_counter =
243 rctx->ws->query_value(rctx->ws,
244 RADEON_GPU_RESET_COUNTER);
245 }
246
247 LIST_INITHEAD(&rctx->texture_buffers);
248
249 r600_init_context_texture_functions(rctx);
250 r600_streamout_init(rctx);
251 r600_query_init(rctx);
252 cayman_init_msaa(&rctx->b);
253
254 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
255 0, PIPE_USAGE_DEFAULT, TRUE);
256 if (!rctx->allocator_so_filled_size)
257 return false;
258
259 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
260 PIPE_BIND_INDEX_BUFFER |
261 PIPE_BIND_CONSTANT_BUFFER);
262 if (!rctx->uploader)
263 return false;
264
265 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
266 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
267 r600_flush_dma_ring,
268 rctx, NULL);
269 rctx->rings.dma.flush = r600_flush_dma_ring;
270 }
271
272 return true;
273 }
274
275 void r600_common_context_cleanup(struct r600_common_context *rctx)
276 {
277 if (rctx->rings.gfx.cs) {
278 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
279 }
280 if (rctx->rings.dma.cs) {
281 rctx->ws->cs_destroy(rctx->rings.dma.cs);
282 }
283
284 if (rctx->uploader) {
285 u_upload_destroy(rctx->uploader);
286 }
287
288 util_slab_destroy(&rctx->pool_transfers);
289
290 if (rctx->allocator_so_filled_size) {
291 u_suballocator_destroy(rctx->allocator_so_filled_size);
292 }
293 }
294
295 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
296 {
297 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
298 struct r600_resource *rr = (struct r600_resource *)r;
299
300 if (r == NULL) {
301 return;
302 }
303
304 /*
305 * The idea is to compute a gross estimate of memory requirement of
306 * each draw call. After each draw call, memory will be precisely
307 * accounted. So the uncertainty is only on the current draw call.
308 * In practice this gave very good estimate (+/- 10% of the target
309 * memory limit).
310 */
311 if (rr->domains & RADEON_DOMAIN_GTT) {
312 rctx->gtt += rr->buf->size;
313 }
314 if (rr->domains & RADEON_DOMAIN_VRAM) {
315 rctx->vram += rr->buf->size;
316 }
317 }
318
319 /*
320 * pipe_screen
321 */
322
323 static const struct debug_named_value common_debug_options[] = {
324 /* logging */
325 { "tex", DBG_TEX, "Print texture info" },
326 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
327 { "compute", DBG_COMPUTE, "Print compute info" },
328 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
329 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
330 { "info", DBG_INFO, "Print driver information" },
331
332 /* shaders */
333 { "fs", DBG_FS, "Print fetch shaders" },
334 { "vs", DBG_VS, "Print vertex shaders" },
335 { "gs", DBG_GS, "Print geometry shaders" },
336 { "ps", DBG_PS, "Print pixel shaders" },
337 { "cs", DBG_CS, "Print compute shaders" },
338 { "tcs", DBG_TCS, "Print tessellation control shaders" },
339 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
340 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
341 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
342 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
343
344 /* features */
345 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
346 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
347 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
348 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
349 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
350 { "notiling", DBG_NO_TILING, "Disable tiling" },
351 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
352 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
353 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
354
355 DEBUG_NAMED_VALUE_END /* must be last */
356 };
357
358 static const char* r600_get_vendor(struct pipe_screen* pscreen)
359 {
360 return "X.Org";
361 }
362
363 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
364 {
365 return "AMD";
366 }
367
368 static const char* r600_get_name(struct pipe_screen* pscreen)
369 {
370 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
371
372 switch (rscreen->family) {
373 case CHIP_R600: return "AMD R600";
374 case CHIP_RV610: return "AMD RV610";
375 case CHIP_RV630: return "AMD RV630";
376 case CHIP_RV670: return "AMD RV670";
377 case CHIP_RV620: return "AMD RV620";
378 case CHIP_RV635: return "AMD RV635";
379 case CHIP_RS780: return "AMD RS780";
380 case CHIP_RS880: return "AMD RS880";
381 case CHIP_RV770: return "AMD RV770";
382 case CHIP_RV730: return "AMD RV730";
383 case CHIP_RV710: return "AMD RV710";
384 case CHIP_RV740: return "AMD RV740";
385 case CHIP_CEDAR: return "AMD CEDAR";
386 case CHIP_REDWOOD: return "AMD REDWOOD";
387 case CHIP_JUNIPER: return "AMD JUNIPER";
388 case CHIP_CYPRESS: return "AMD CYPRESS";
389 case CHIP_HEMLOCK: return "AMD HEMLOCK";
390 case CHIP_PALM: return "AMD PALM";
391 case CHIP_SUMO: return "AMD SUMO";
392 case CHIP_SUMO2: return "AMD SUMO2";
393 case CHIP_BARTS: return "AMD BARTS";
394 case CHIP_TURKS: return "AMD TURKS";
395 case CHIP_CAICOS: return "AMD CAICOS";
396 case CHIP_CAYMAN: return "AMD CAYMAN";
397 case CHIP_ARUBA: return "AMD ARUBA";
398 case CHIP_TAHITI: return "AMD TAHITI";
399 case CHIP_PITCAIRN: return "AMD PITCAIRN";
400 case CHIP_VERDE: return "AMD CAPE VERDE";
401 case CHIP_OLAND: return "AMD OLAND";
402 case CHIP_HAINAN: return "AMD HAINAN";
403 case CHIP_BONAIRE: return "AMD BONAIRE";
404 case CHIP_KAVERI: return "AMD KAVERI";
405 case CHIP_KABINI: return "AMD KABINI";
406 case CHIP_HAWAII: return "AMD HAWAII";
407 case CHIP_MULLINS: return "AMD MULLINS";
408 default: return "AMD unknown";
409 }
410 }
411
412 static float r600_get_paramf(struct pipe_screen* pscreen,
413 enum pipe_capf param)
414 {
415 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
416
417 switch (param) {
418 case PIPE_CAPF_MAX_LINE_WIDTH:
419 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
420 case PIPE_CAPF_MAX_POINT_WIDTH:
421 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
422 if (rscreen->family >= CHIP_CEDAR)
423 return 16384.0f;
424 else
425 return 8192.0f;
426 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
427 return 16.0f;
428 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
429 return 16.0f;
430 case PIPE_CAPF_GUARD_BAND_LEFT:
431 case PIPE_CAPF_GUARD_BAND_TOP:
432 case PIPE_CAPF_GUARD_BAND_RIGHT:
433 case PIPE_CAPF_GUARD_BAND_BOTTOM:
434 return 0.0f;
435 }
436 return 0.0f;
437 }
438
439 static int r600_get_video_param(struct pipe_screen *screen,
440 enum pipe_video_profile profile,
441 enum pipe_video_entrypoint entrypoint,
442 enum pipe_video_cap param)
443 {
444 switch (param) {
445 case PIPE_VIDEO_CAP_SUPPORTED:
446 return vl_profile_supported(screen, profile, entrypoint);
447 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
448 return 1;
449 case PIPE_VIDEO_CAP_MAX_WIDTH:
450 case PIPE_VIDEO_CAP_MAX_HEIGHT:
451 return vl_video_buffer_max_size(screen);
452 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
453 return PIPE_FORMAT_NV12;
454 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
455 return false;
456 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
457 return false;
458 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
459 return true;
460 case PIPE_VIDEO_CAP_MAX_LEVEL:
461 return vl_level_supported(screen, profile);
462 default:
463 return 0;
464 }
465 }
466
467 const char *r600_get_llvm_processor_name(enum radeon_family family)
468 {
469 switch (family) {
470 case CHIP_R600:
471 case CHIP_RV630:
472 case CHIP_RV635:
473 case CHIP_RV670:
474 return "r600";
475 case CHIP_RV610:
476 case CHIP_RV620:
477 case CHIP_RS780:
478 case CHIP_RS880:
479 return "rs880";
480 case CHIP_RV710:
481 return "rv710";
482 case CHIP_RV730:
483 return "rv730";
484 case CHIP_RV740:
485 case CHIP_RV770:
486 return "rv770";
487 case CHIP_PALM:
488 case CHIP_CEDAR:
489 return "cedar";
490 case CHIP_SUMO:
491 case CHIP_SUMO2:
492 return "sumo";
493 case CHIP_REDWOOD:
494 return "redwood";
495 case CHIP_JUNIPER:
496 return "juniper";
497 case CHIP_HEMLOCK:
498 case CHIP_CYPRESS:
499 return "cypress";
500 case CHIP_BARTS:
501 return "barts";
502 case CHIP_TURKS:
503 return "turks";
504 case CHIP_CAICOS:
505 return "caicos";
506 case CHIP_CAYMAN:
507 case CHIP_ARUBA:
508 return "cayman";
509
510 case CHIP_TAHITI: return "tahiti";
511 case CHIP_PITCAIRN: return "pitcairn";
512 case CHIP_VERDE: return "verde";
513 case CHIP_OLAND: return "oland";
514 case CHIP_HAINAN: return "hainan";
515 case CHIP_BONAIRE: return "bonaire";
516 case CHIP_KABINI: return "kabini";
517 case CHIP_KAVERI: return "kaveri";
518 case CHIP_HAWAII: return "hawaii";
519 case CHIP_MULLINS:
520 #if HAVE_LLVM >= 0x0305
521 return "mullins";
522 #else
523 return "kabini";
524 #endif
525 default: return "";
526 }
527 }
528
529 static int r600_get_compute_param(struct pipe_screen *screen,
530 enum pipe_compute_cap param,
531 void *ret)
532 {
533 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
534
535 //TODO: select these params by asic
536 switch (param) {
537 case PIPE_COMPUTE_CAP_IR_TARGET: {
538 const char *gpu;
539 const char *triple;
540 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
541 triple = "r600--";
542 } else {
543 triple = "amdgcn--";
544 }
545 switch(rscreen->family) {
546 /* Clang < 3.6 is missing Hainan in its list of
547 * GPUs, so we need to use the name of a similar GPU.
548 */
549 #if HAVE_LLVM < 0x0306
550 case CHIP_HAINAN:
551 gpu = "oland";
552 break;
553 #endif
554 default:
555 gpu = r600_get_llvm_processor_name(rscreen->family);
556 break;
557 }
558 if (ret) {
559 sprintf(ret, "%s-%s", gpu, triple);
560 }
561 /* +2 for dash and terminating NIL byte */
562 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
563 }
564 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
565 if (ret) {
566 uint64_t *grid_dimension = ret;
567 grid_dimension[0] = 3;
568 }
569 return 1 * sizeof(uint64_t);
570
571 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
572 if (ret) {
573 uint64_t *grid_size = ret;
574 grid_size[0] = 65535;
575 grid_size[1] = 65535;
576 grid_size[2] = 1;
577 }
578 return 3 * sizeof(uint64_t) ;
579
580 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
581 if (ret) {
582 uint64_t *block_size = ret;
583 block_size[0] = 256;
584 block_size[1] = 256;
585 block_size[2] = 256;
586 }
587 return 3 * sizeof(uint64_t);
588
589 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
590 if (ret) {
591 uint64_t *max_threads_per_block = ret;
592 *max_threads_per_block = 256;
593 }
594 return sizeof(uint64_t);
595
596 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
597 if (ret) {
598 uint64_t *max_global_size = ret;
599 uint64_t max_mem_alloc_size;
600
601 r600_get_compute_param(screen,
602 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
603 &max_mem_alloc_size);
604
605 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
606 * 1/4 of the MAX_GLOBAL_SIZE. Since the
607 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
608 * make sure we never report more than
609 * 4 * MAX_MEM_ALLOC_SIZE.
610 */
611 *max_global_size = MIN2(4 * max_mem_alloc_size,
612 rscreen->info.gart_size +
613 rscreen->info.vram_size);
614 }
615 return sizeof(uint64_t);
616
617 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
618 if (ret) {
619 uint64_t *max_local_size = ret;
620 /* Value reported by the closed source driver. */
621 *max_local_size = 32768;
622 }
623 return sizeof(uint64_t);
624
625 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
626 if (ret) {
627 uint64_t *max_input_size = ret;
628 /* Value reported by the closed source driver. */
629 *max_input_size = 1024;
630 }
631 return sizeof(uint64_t);
632
633 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
634 if (ret) {
635 uint64_t *max_mem_alloc_size = ret;
636
637 /* XXX: The limit in older kernels is 256 MB. We
638 * should add a query here for newer kernels.
639 */
640 *max_mem_alloc_size = 256 * 1024 * 1024;
641 }
642 return sizeof(uint64_t);
643
644 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
645 if (ret) {
646 uint32_t *max_clock_frequency = ret;
647 *max_clock_frequency = rscreen->info.max_sclk;
648 }
649 return sizeof(uint32_t);
650
651 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
652 if (ret) {
653 uint32_t *max_compute_units = ret;
654 *max_compute_units = rscreen->info.max_compute_units;
655 }
656 return sizeof(uint32_t);
657
658 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
659 if (ret) {
660 uint32_t *images_supported = ret;
661 *images_supported = 0;
662 }
663 return sizeof(uint32_t);
664 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
665 break; /* unused */
666 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
667 if (ret) {
668 uint32_t *subgroup_size = ret;
669 *subgroup_size = r600_wavefront_size(rscreen->family);
670 }
671 return sizeof(uint32_t);
672 }
673
674 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
675 return 0;
676 }
677
678 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
679 {
680 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
681
682 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
683 rscreen->info.r600_clock_crystal_freq;
684 }
685
686 static int r600_get_driver_query_info(struct pipe_screen *screen,
687 unsigned index,
688 struct pipe_driver_query_info *info)
689 {
690 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
691 struct pipe_driver_query_info list[] = {
692 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
693 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
694 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
695 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
696 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
697 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
698 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
699 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
700 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
701 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
702 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
703 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
704 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
705 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
706 };
707 unsigned num_queries;
708
709 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
710 num_queries = Elements(list);
711 else
712 num_queries = 8;
713
714 if (!info)
715 return num_queries;
716
717 if (index >= num_queries)
718 return 0;
719
720 *info = list[index];
721 return 1;
722 }
723
724 static void r600_fence_reference(struct pipe_screen *screen,
725 struct pipe_fence_handle **ptr,
726 struct pipe_fence_handle *fence)
727 {
728 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
729
730 rws->fence_reference(ptr, fence);
731 }
732
733 static boolean r600_fence_finish(struct pipe_screen *screen,
734 struct pipe_fence_handle *fence,
735 uint64_t timeout)
736 {
737 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
738
739 return rws->fence_wait(rws, fence, timeout);
740 }
741
742 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
743 uint32_t tiling_config)
744 {
745 switch ((tiling_config & 0xe) >> 1) {
746 case 0:
747 rscreen->tiling_info.num_channels = 1;
748 break;
749 case 1:
750 rscreen->tiling_info.num_channels = 2;
751 break;
752 case 2:
753 rscreen->tiling_info.num_channels = 4;
754 break;
755 case 3:
756 rscreen->tiling_info.num_channels = 8;
757 break;
758 default:
759 return false;
760 }
761
762 switch ((tiling_config & 0x30) >> 4) {
763 case 0:
764 rscreen->tiling_info.num_banks = 4;
765 break;
766 case 1:
767 rscreen->tiling_info.num_banks = 8;
768 break;
769 default:
770 return false;
771
772 }
773 switch ((tiling_config & 0xc0) >> 6) {
774 case 0:
775 rscreen->tiling_info.group_bytes = 256;
776 break;
777 case 1:
778 rscreen->tiling_info.group_bytes = 512;
779 break;
780 default:
781 return false;
782 }
783 return true;
784 }
785
786 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
787 uint32_t tiling_config)
788 {
789 switch (tiling_config & 0xf) {
790 case 0:
791 rscreen->tiling_info.num_channels = 1;
792 break;
793 case 1:
794 rscreen->tiling_info.num_channels = 2;
795 break;
796 case 2:
797 rscreen->tiling_info.num_channels = 4;
798 break;
799 case 3:
800 rscreen->tiling_info.num_channels = 8;
801 break;
802 default:
803 return false;
804 }
805
806 switch ((tiling_config & 0xf0) >> 4) {
807 case 0:
808 rscreen->tiling_info.num_banks = 4;
809 break;
810 case 1:
811 rscreen->tiling_info.num_banks = 8;
812 break;
813 case 2:
814 rscreen->tiling_info.num_banks = 16;
815 break;
816 default:
817 return false;
818 }
819
820 switch ((tiling_config & 0xf00) >> 8) {
821 case 0:
822 rscreen->tiling_info.group_bytes = 256;
823 break;
824 case 1:
825 rscreen->tiling_info.group_bytes = 512;
826 break;
827 default:
828 return false;
829 }
830 return true;
831 }
832
833 static bool r600_init_tiling(struct r600_common_screen *rscreen)
834 {
835 uint32_t tiling_config = rscreen->info.r600_tiling_config;
836
837 /* set default group bytes, overridden by tiling info ioctl */
838 if (rscreen->chip_class <= R700) {
839 rscreen->tiling_info.group_bytes = 256;
840 } else {
841 rscreen->tiling_info.group_bytes = 512;
842 }
843
844 if (!tiling_config)
845 return true;
846
847 if (rscreen->chip_class <= R700) {
848 return r600_interpret_tiling(rscreen, tiling_config);
849 } else {
850 return evergreen_interpret_tiling(rscreen, tiling_config);
851 }
852 }
853
854 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
855 const struct pipe_resource *templ)
856 {
857 if (templ->target == PIPE_BUFFER) {
858 return r600_buffer_create(screen, templ, 4096);
859 } else {
860 return r600_texture_create(screen, templ);
861 }
862 }
863
864 bool r600_common_screen_init(struct r600_common_screen *rscreen,
865 struct radeon_winsys *ws)
866 {
867 ws->query_info(ws, &rscreen->info);
868
869 rscreen->b.get_name = r600_get_name;
870 rscreen->b.get_vendor = r600_get_vendor;
871 rscreen->b.get_device_vendor = r600_get_device_vendor;
872 rscreen->b.get_compute_param = r600_get_compute_param;
873 rscreen->b.get_paramf = r600_get_paramf;
874 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
875 rscreen->b.get_timestamp = r600_get_timestamp;
876 rscreen->b.fence_finish = r600_fence_finish;
877 rscreen->b.fence_reference = r600_fence_reference;
878 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
879 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
880
881 if (rscreen->info.has_uvd) {
882 rscreen->b.get_video_param = rvid_get_video_param;
883 rscreen->b.is_video_format_supported = rvid_is_format_supported;
884 } else {
885 rscreen->b.get_video_param = r600_get_video_param;
886 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
887 }
888
889 r600_init_screen_texture_functions(rscreen);
890
891 rscreen->ws = ws;
892 rscreen->family = rscreen->info.family;
893 rscreen->chip_class = rscreen->info.chip_class;
894 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
895
896 if (!r600_init_tiling(rscreen)) {
897 return false;
898 }
899 util_format_s3tc_init();
900 pipe_mutex_init(rscreen->aux_context_lock);
901 pipe_mutex_init(rscreen->gpu_load_mutex);
902
903 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
904 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
905 PIPE_BIND_CUSTOM,
906 PIPE_USAGE_STAGING,
907 4096);
908 if (rscreen->trace_bo) {
909 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
910 PIPE_TRANSFER_UNSYNCHRONIZED);
911 }
912 }
913
914 if (rscreen->debug_flags & DBG_INFO) {
915 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
916 printf("family = %i\n", rscreen->info.family);
917 printf("chip_class = %i\n", rscreen->info.chip_class);
918 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
919 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
920 printf("max_sclk = %i\n", rscreen->info.max_sclk);
921 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
922 printf("max_se = %i\n", rscreen->info.max_se);
923 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
924 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
925 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
926 printf("has_uvd = %i\n", rscreen->info.has_uvd);
927 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
928 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
929 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
930 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
931 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
932 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
933 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
934 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
935 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
936 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
937 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
938 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
939 }
940 return true;
941 }
942
943 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
944 {
945 r600_gpu_load_kill_thread(rscreen);
946
947 pipe_mutex_destroy(rscreen->gpu_load_mutex);
948 pipe_mutex_destroy(rscreen->aux_context_lock);
949 rscreen->aux_context->destroy(rscreen->aux_context);
950
951 if (rscreen->trace_bo)
952 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
953
954 rscreen->ws->destroy(rscreen->ws);
955 FREE(rscreen);
956 }
957
958 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
959 const struct tgsi_token *tokens)
960 {
961 /* Compute shader don't have tgsi_tokens */
962 if (!tokens)
963 return (rscreen->debug_flags & DBG_CS) != 0;
964
965 switch (tgsi_get_processor_type(tokens)) {
966 case TGSI_PROCESSOR_VERTEX:
967 return (rscreen->debug_flags & DBG_VS) != 0;
968 case TGSI_PROCESSOR_TESS_CTRL:
969 return (rscreen->debug_flags & DBG_TCS) != 0;
970 case TGSI_PROCESSOR_TESS_EVAL:
971 return (rscreen->debug_flags & DBG_TES) != 0;
972 case TGSI_PROCESSOR_GEOMETRY:
973 return (rscreen->debug_flags & DBG_GS) != 0;
974 case TGSI_PROCESSOR_FRAGMENT:
975 return (rscreen->debug_flags & DBG_PS) != 0;
976 case TGSI_PROCESSOR_COMPUTE:
977 return (rscreen->debug_flags & DBG_CS) != 0;
978 default:
979 return false;
980 }
981 }
982
983 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
984 unsigned offset, unsigned size, unsigned value,
985 bool is_framebuffer)
986 {
987 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
988
989 pipe_mutex_lock(rscreen->aux_context_lock);
990 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
991 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
992 pipe_mutex_unlock(rscreen->aux_context_lock);
993 }