2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_upload_mgr.h"
33 #include "vl/vl_decoder.h"
34 #include "vl/vl_video_buffer.h"
35 #include "radeon/radeon_video.h"
42 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
)
44 /* The number of dwords we already used in the DMA so far. */
45 num_dw
+= ctx
->rings
.dma
.cs
->cdw
;
46 /* Flush if there's not enough space. */
47 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
48 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
52 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
56 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
58 /* Disable render condition. */
59 ctx
->saved_render_cond
= NULL
;
60 ctx
->saved_render_cond_cond
= FALSE
;
61 ctx
->saved_render_cond_mode
= 0;
62 if (ctx
->current_render_cond
) {
63 ctx
->saved_render_cond
= ctx
->current_render_cond
;
64 ctx
->saved_render_cond_cond
= ctx
->current_render_cond_cond
;
65 ctx
->saved_render_cond_mode
= ctx
->current_render_cond_mode
;
66 ctx
->b
.render_condition(&ctx
->b
, NULL
, FALSE
, 0);
70 ctx
->nontimer_queries_suspended
= false;
71 if (ctx
->num_cs_dw_nontimer_queries_suspend
) {
72 r600_suspend_nontimer_queries(ctx
);
73 ctx
->nontimer_queries_suspended
= true;
76 ctx
->streamout
.suspended
= false;
77 if (ctx
->streamout
.begin_emitted
) {
78 r600_emit_streamout_end(ctx
);
79 ctx
->streamout
.suspended
= true;
83 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
85 if (ctx
->streamout
.suspended
) {
86 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
87 r600_streamout_buffers_dirty(ctx
);
91 if (ctx
->nontimer_queries_suspended
) {
92 r600_resume_nontimer_queries(ctx
);
95 /* Re-enable render condition. */
96 if (ctx
->saved_render_cond
) {
97 ctx
->b
.render_condition(&ctx
->b
, ctx
->saved_render_cond
,
98 ctx
->saved_render_cond_cond
,
99 ctx
->saved_render_cond_mode
);
103 static void r600_flush_from_st(struct pipe_context
*ctx
,
104 struct pipe_fence_handle
**fence
,
107 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
110 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
111 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
113 if (rctx
->rings
.dma
.cs
) {
114 rctx
->rings
.dma
.flush(rctx
, rflags
, NULL
);
116 rctx
->rings
.gfx
.flush(rctx
, rflags
, fence
);
119 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
120 struct pipe_fence_handle
**fence
)
122 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
123 struct radeon_winsys_cs
*cs
= rctx
->rings
.dma
.cs
;
129 rctx
->rings
.dma
.flushing
= true;
130 rctx
->ws
->cs_flush(cs
, flags
, fence
, 0);
131 rctx
->rings
.dma
.flushing
= false;
134 bool r600_common_context_init(struct r600_common_context
*rctx
,
135 struct r600_common_screen
*rscreen
)
137 util_slab_create(&rctx
->pool_transfers
,
138 sizeof(struct r600_transfer
), 64,
139 UTIL_SLAB_SINGLETHREADED
);
141 rctx
->screen
= rscreen
;
142 rctx
->ws
= rscreen
->ws
;
143 rctx
->family
= rscreen
->family
;
144 rctx
->chip_class
= rscreen
->chip_class
;
145 rctx
->max_db
= rscreen
->chip_class
>= EVERGREEN
? 8 : 4;
147 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
148 rctx
->b
.transfer_flush_region
= u_default_transfer_flush_region
;
149 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
150 rctx
->b
.transfer_inline_write
= u_default_transfer_inline_write
;
151 rctx
->b
.memory_barrier
= r600_memory_barrier
;
152 rctx
->b
.flush
= r600_flush_from_st
;
154 r600_init_context_texture_functions(rctx
);
155 r600_streamout_init(rctx
);
156 r600_query_init(rctx
);
157 cayman_init_msaa(&rctx
->b
);
159 rctx
->allocator_so_filled_size
= u_suballocator_create(&rctx
->b
, 4096, 4,
160 0, PIPE_USAGE_DEFAULT
, TRUE
);
161 if (!rctx
->allocator_so_filled_size
)
164 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024, 256,
165 PIPE_BIND_INDEX_BUFFER
|
166 PIPE_BIND_CONSTANT_BUFFER
);
170 if (rscreen
->info
.r600_has_dma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
171 rctx
->rings
.dma
.cs
= rctx
->ws
->cs_create(rctx
->ws
, RING_DMA
,
174 rctx
->rings
.dma
.flush
= r600_flush_dma_ring
;
180 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
182 if (rctx
->rings
.gfx
.cs
) {
183 rctx
->ws
->cs_destroy(rctx
->rings
.gfx
.cs
);
185 if (rctx
->rings
.dma
.cs
) {
186 rctx
->ws
->cs_destroy(rctx
->rings
.dma
.cs
);
189 if (rctx
->uploader
) {
190 u_upload_destroy(rctx
->uploader
);
193 util_slab_destroy(&rctx
->pool_transfers
);
195 if (rctx
->allocator_so_filled_size
) {
196 u_suballocator_destroy(rctx
->allocator_so_filled_size
);
200 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
202 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
203 struct r600_resource
*rr
= (struct r600_resource
*)r
;
210 * The idea is to compute a gross estimate of memory requirement of
211 * each draw call. After each draw call, memory will be precisely
212 * accounted. So the uncertainty is only on the current draw call.
213 * In practice this gave very good estimate (+/- 10% of the target
216 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
217 rctx
->gtt
+= rr
->buf
->size
;
219 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
220 rctx
->vram
+= rr
->buf
->size
;
228 static const struct debug_named_value common_debug_options
[] = {
230 { "tex", DBG_TEX
, "Print texture info" },
231 { "texmip", DBG_TEXMIP
, "Print texture info (mipmapped only)" },
232 { "compute", DBG_COMPUTE
, "Print compute info" },
233 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
234 { "trace_cs", DBG_TRACE_CS
, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
237 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
240 { "fs", DBG_FS
, "Print fetch shaders" },
241 { "vs", DBG_VS
, "Print vertex shaders" },
242 { "gs", DBG_GS
, "Print geometry shaders" },
243 { "ps", DBG_PS
, "Print pixel shaders" },
244 { "cs", DBG_CS
, "Print compute shaders" },
246 { "hyperz", DBG_HYPERZ
, "Enable Hyper-Z" },
247 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
248 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
250 DEBUG_NAMED_VALUE_END
/* must be last */
253 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
258 static const char* r600_get_name(struct pipe_screen
* pscreen
)
260 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
262 switch (rscreen
->family
) {
263 case CHIP_R600
: return "AMD R600";
264 case CHIP_RV610
: return "AMD RV610";
265 case CHIP_RV630
: return "AMD RV630";
266 case CHIP_RV670
: return "AMD RV670";
267 case CHIP_RV620
: return "AMD RV620";
268 case CHIP_RV635
: return "AMD RV635";
269 case CHIP_RS780
: return "AMD RS780";
270 case CHIP_RS880
: return "AMD RS880";
271 case CHIP_RV770
: return "AMD RV770";
272 case CHIP_RV730
: return "AMD RV730";
273 case CHIP_RV710
: return "AMD RV710";
274 case CHIP_RV740
: return "AMD RV740";
275 case CHIP_CEDAR
: return "AMD CEDAR";
276 case CHIP_REDWOOD
: return "AMD REDWOOD";
277 case CHIP_JUNIPER
: return "AMD JUNIPER";
278 case CHIP_CYPRESS
: return "AMD CYPRESS";
279 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
280 case CHIP_PALM
: return "AMD PALM";
281 case CHIP_SUMO
: return "AMD SUMO";
282 case CHIP_SUMO2
: return "AMD SUMO2";
283 case CHIP_BARTS
: return "AMD BARTS";
284 case CHIP_TURKS
: return "AMD TURKS";
285 case CHIP_CAICOS
: return "AMD CAICOS";
286 case CHIP_CAYMAN
: return "AMD CAYMAN";
287 case CHIP_ARUBA
: return "AMD ARUBA";
288 case CHIP_TAHITI
: return "AMD TAHITI";
289 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
290 case CHIP_VERDE
: return "AMD CAPE VERDE";
291 case CHIP_OLAND
: return "AMD OLAND";
292 case CHIP_HAINAN
: return "AMD HAINAN";
293 case CHIP_BONAIRE
: return "AMD BONAIRE";
294 case CHIP_KAVERI
: return "AMD KAVERI";
295 case CHIP_KABINI
: return "AMD KABINI";
296 case CHIP_HAWAII
: return "AMD HAWAII";
297 case CHIP_MULLINS
: return "AMD MULLINS";
298 default: return "AMD unknown";
302 static float r600_get_paramf(struct pipe_screen
* pscreen
,
303 enum pipe_capf param
)
305 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
308 case PIPE_CAPF_MAX_LINE_WIDTH
:
309 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
310 case PIPE_CAPF_MAX_POINT_WIDTH
:
311 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
312 if (rscreen
->family
>= CHIP_CEDAR
)
316 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
318 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
320 case PIPE_CAPF_GUARD_BAND_LEFT
:
321 case PIPE_CAPF_GUARD_BAND_TOP
:
322 case PIPE_CAPF_GUARD_BAND_RIGHT
:
323 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
329 static int r600_get_video_param(struct pipe_screen
*screen
,
330 enum pipe_video_profile profile
,
331 enum pipe_video_entrypoint entrypoint
,
332 enum pipe_video_cap param
)
335 case PIPE_VIDEO_CAP_SUPPORTED
:
336 return vl_profile_supported(screen
, profile
, entrypoint
);
337 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
339 case PIPE_VIDEO_CAP_MAX_WIDTH
:
340 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
341 return vl_video_buffer_max_size(screen
);
342 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
343 return PIPE_FORMAT_NV12
;
344 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
346 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
348 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
350 case PIPE_VIDEO_CAP_MAX_LEVEL
:
351 return vl_level_supported(screen
, profile
);
357 const char *r600_get_llvm_processor_name(enum radeon_family family
)
400 case CHIP_TAHITI
: return "tahiti";
401 case CHIP_PITCAIRN
: return "pitcairn";
402 case CHIP_VERDE
: return "verde";
403 case CHIP_OLAND
: return "oland";
404 #if HAVE_LLVM <= 0x0303
406 fprintf(stderr
, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
410 case CHIP_HAINAN
: return "hainan";
411 case CHIP_BONAIRE
: return "bonaire";
412 case CHIP_KABINI
: return "kabini";
413 case CHIP_KAVERI
: return "kaveri";
414 case CHIP_HAWAII
: return "hawaii";
416 #if HAVE_LLVM >= 0x0305
426 static int r600_get_compute_param(struct pipe_screen
*screen
,
427 enum pipe_compute_cap param
,
430 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
432 //TODO: select these params by asic
434 case PIPE_COMPUTE_CAP_IR_TARGET
: {
435 const char *gpu
= r600_get_llvm_processor_name(rscreen
->family
);
437 sprintf(ret
, "%s-r600--", gpu
);
439 return (8 + strlen(gpu
)) * sizeof(char);
441 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
443 uint64_t *grid_dimension
= ret
;
444 grid_dimension
[0] = 3;
446 return 1 * sizeof(uint64_t);
448 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
450 uint64_t *grid_size
= ret
;
451 grid_size
[0] = 65535;
452 grid_size
[1] = 65535;
455 return 3 * sizeof(uint64_t) ;
457 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
459 uint64_t *block_size
= ret
;
464 return 3 * sizeof(uint64_t);
466 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
468 uint64_t *max_threads_per_block
= ret
;
469 *max_threads_per_block
= 256;
471 return sizeof(uint64_t);
473 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
475 uint64_t *max_global_size
= ret
;
476 /* XXX: This is what the proprietary driver reports, we
477 * may want to use a different value. */
478 /* XXX: Not sure what to put here for SI. */
479 if (rscreen
->chip_class
>= SI
)
480 *max_global_size
= 2000000000;
482 *max_global_size
= 201326592;
484 return sizeof(uint64_t);
486 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
488 uint64_t *max_local_size
= ret
;
489 /* Value reported by the closed source driver. */
490 *max_local_size
= 32768;
492 return sizeof(uint64_t);
494 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
496 uint64_t *max_input_size
= ret
;
497 /* Value reported by the closed source driver. */
498 *max_input_size
= 1024;
500 return sizeof(uint64_t);
502 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
504 uint64_t max_global_size
;
505 uint64_t *max_mem_alloc_size
= ret
;
506 r600_get_compute_param(screen
, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
, &max_global_size
);
507 /* OpenCL requres this value be at least
508 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
509 * I'm really not sure what value to report here, but
510 * MAX_GLOBAL_SIZE / 4 seems resonable.
512 *max_mem_alloc_size
= max_global_size
/ 4;
514 return sizeof(uint64_t);
516 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
518 uint32_t *max_clock_frequency
= ret
;
519 *max_clock_frequency
= rscreen
->info
.max_sclk
;
521 return sizeof(uint32_t);
523 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
525 uint32_t *max_compute_units
= ret
;
526 *max_compute_units
= rscreen
->info
.max_compute_units
;
528 return sizeof(uint32_t);
531 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
536 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
538 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
540 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
541 rscreen
->info
.r600_clock_crystal_freq
;
544 static int r600_get_driver_query_info(struct pipe_screen
*screen
,
546 struct pipe_driver_query_info
*info
)
548 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
549 struct pipe_driver_query_info list
[] = {
550 {"draw-calls", R600_QUERY_DRAW_CALLS
, 0},
551 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM
, rscreen
->info
.vram_size
, TRUE
},
552 {"requested-GTT", R600_QUERY_REQUESTED_GTT
, rscreen
->info
.gart_size
, TRUE
},
553 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME
, 0, FALSE
},
554 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES
, 0, FALSE
},
555 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED
, 0, TRUE
},
556 {"VRAM-usage", R600_QUERY_VRAM_USAGE
, rscreen
->info
.vram_size
, TRUE
},
557 {"GTT-usage", R600_QUERY_GTT_USAGE
, rscreen
->info
.gart_size
, TRUE
},
561 return Elements(list
);
563 if (index
>= Elements(list
))
570 static void r600_fence_reference(struct pipe_screen
*screen
,
571 struct pipe_fence_handle
**ptr
,
572 struct pipe_fence_handle
*fence
)
574 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
576 rws
->fence_reference(ptr
, fence
);
579 static boolean
r600_fence_signalled(struct pipe_screen
*screen
,
580 struct pipe_fence_handle
*fence
)
582 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
584 return rws
->fence_wait(rws
, fence
, 0);
587 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
588 struct pipe_fence_handle
*fence
,
591 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
593 return rws
->fence_wait(rws
, fence
, timeout
);
596 static bool r600_interpret_tiling(struct r600_common_screen
*rscreen
,
597 uint32_t tiling_config
)
599 switch ((tiling_config
& 0xe) >> 1) {
601 rscreen
->tiling_info
.num_channels
= 1;
604 rscreen
->tiling_info
.num_channels
= 2;
607 rscreen
->tiling_info
.num_channels
= 4;
610 rscreen
->tiling_info
.num_channels
= 8;
616 switch ((tiling_config
& 0x30) >> 4) {
618 rscreen
->tiling_info
.num_banks
= 4;
621 rscreen
->tiling_info
.num_banks
= 8;
627 switch ((tiling_config
& 0xc0) >> 6) {
629 rscreen
->tiling_info
.group_bytes
= 256;
632 rscreen
->tiling_info
.group_bytes
= 512;
640 static bool evergreen_interpret_tiling(struct r600_common_screen
*rscreen
,
641 uint32_t tiling_config
)
643 switch (tiling_config
& 0xf) {
645 rscreen
->tiling_info
.num_channels
= 1;
648 rscreen
->tiling_info
.num_channels
= 2;
651 rscreen
->tiling_info
.num_channels
= 4;
654 rscreen
->tiling_info
.num_channels
= 8;
660 switch ((tiling_config
& 0xf0) >> 4) {
662 rscreen
->tiling_info
.num_banks
= 4;
665 rscreen
->tiling_info
.num_banks
= 8;
668 rscreen
->tiling_info
.num_banks
= 16;
674 switch ((tiling_config
& 0xf00) >> 8) {
676 rscreen
->tiling_info
.group_bytes
= 256;
679 rscreen
->tiling_info
.group_bytes
= 512;
687 static bool r600_init_tiling(struct r600_common_screen
*rscreen
)
689 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
691 /* set default group bytes, overridden by tiling info ioctl */
692 if (rscreen
->chip_class
<= R700
) {
693 rscreen
->tiling_info
.group_bytes
= 256;
695 rscreen
->tiling_info
.group_bytes
= 512;
701 if (rscreen
->chip_class
<= R700
) {
702 return r600_interpret_tiling(rscreen
, tiling_config
);
704 return evergreen_interpret_tiling(rscreen
, tiling_config
);
708 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
709 const struct pipe_resource
*templ
)
711 if (templ
->target
== PIPE_BUFFER
) {
712 return r600_buffer_create(screen
, templ
, 4096);
714 return r600_texture_create(screen
, templ
);
718 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
719 struct radeon_winsys
*ws
)
721 ws
->query_info(ws
, &rscreen
->info
);
723 rscreen
->b
.get_name
= r600_get_name
;
724 rscreen
->b
.get_vendor
= r600_get_vendor
;
725 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
726 rscreen
->b
.get_paramf
= r600_get_paramf
;
727 rscreen
->b
.get_driver_query_info
= r600_get_driver_query_info
;
728 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
729 rscreen
->b
.fence_finish
= r600_fence_finish
;
730 rscreen
->b
.fence_reference
= r600_fence_reference
;
731 rscreen
->b
.fence_signalled
= r600_fence_signalled
;
732 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
734 if (rscreen
->info
.has_uvd
) {
735 rscreen
->b
.get_video_param
= rvid_get_video_param
;
736 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
738 rscreen
->b
.get_video_param
= r600_get_video_param
;
739 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
742 r600_init_screen_texture_functions(rscreen
);
745 rscreen
->family
= rscreen
->info
.family
;
746 rscreen
->chip_class
= rscreen
->info
.chip_class
;
747 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
749 if (!r600_init_tiling(rscreen
)) {
752 util_format_s3tc_init();
753 pipe_mutex_init(rscreen
->aux_context_lock
);
755 if (rscreen
->info
.drm_minor
>= 28 && (rscreen
->debug_flags
& DBG_TRACE_CS
)) {
756 rscreen
->trace_bo
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
,
760 if (rscreen
->trace_bo
) {
761 rscreen
->trace_ptr
= rscreen
->ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
762 PIPE_TRANSFER_UNSYNCHRONIZED
);
769 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
771 pipe_mutex_destroy(rscreen
->aux_context_lock
);
772 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
774 if (rscreen
->trace_bo
) {
775 rscreen
->ws
->buffer_unmap(rscreen
->trace_bo
->cs_buf
);
776 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
779 rscreen
->ws
->destroy(rscreen
->ws
);
783 static unsigned tgsi_get_processor_type(const struct tgsi_token
*tokens
)
785 struct tgsi_parse_context parse
;
787 if (tgsi_parse_init( &parse
, tokens
) != TGSI_PARSE_OK
) {
788 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__
, __LINE__
);
791 return parse
.FullHeader
.Processor
.Processor
;
794 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
795 const struct tgsi_token
*tokens
)
797 /* Compute shader don't have tgsi_tokens */
799 return (rscreen
->debug_flags
& DBG_CS
) != 0;
801 switch (tgsi_get_processor_type(tokens
)) {
802 case TGSI_PROCESSOR_VERTEX
:
803 return (rscreen
->debug_flags
& DBG_VS
) != 0;
804 case TGSI_PROCESSOR_GEOMETRY
:
805 return (rscreen
->debug_flags
& DBG_GS
) != 0;
806 case TGSI_PROCESSOR_FRAGMENT
:
807 return (rscreen
->debug_flags
& DBG_PS
) != 0;
808 case TGSI_PROCESSOR_COMPUTE
:
809 return (rscreen
->debug_flags
& DBG_CS
) != 0;
815 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
816 unsigned offset
, unsigned size
, unsigned value
)
818 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
820 pipe_mutex_lock(rscreen
->aux_context_lock
);
821 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
);
822 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
823 pipe_mutex_unlock(rscreen
->aux_context_lock
);