src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  43 {
  44 }
  45
  46 static void r600_flush_dma_ring(void *ctx, unsigned flags)
  47 {
  48         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  49         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
  50
  51         if (!cs->cdw) {
  52                 return;
  53         }
  54
  55         rctx->rings.dma.flushing = true;
  56         rctx->ws->cs_flush(cs, flags, 0);
  57         rctx->rings.dma.flushing = false;
  58 }
  59
  60 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
  61 {
  62         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  63
  64         rctx->rings.dma.flush(rctx, flags);
  65 }
  66
  67 bool r600_common_context_init(struct r600_common_context *rctx,
  68                               struct r600_common_screen *rscreen)
  69 {
  70         util_slab_create(&rctx->pool_transfers,
  71                          sizeof(struct r600_transfer), 64,
  72                          UTIL_SLAB_SINGLETHREADED);
  73
  74         rctx->screen = rscreen;
  75         rctx->ws = rscreen->ws;
  76         rctx->family = rscreen->family;
  77         rctx->chip_class = rscreen->chip_class;
  78         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
  79
  80         rctx->b.transfer_map = u_transfer_map_vtbl;
  81         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
  82         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
  83         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
  84         rctx->b.memory_barrier = r600_memory_barrier;
  85
  86         r600_init_context_texture_functions(rctx);
  87         r600_streamout_init(rctx);
  88         r600_query_init(rctx);
  89
  90         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
  91                                                                0, PIPE_USAGE_DEFAULT, TRUE);
  92         if (!rctx->allocator_so_filled_size)
  93                 return false;
  94
  95         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
  96                                         PIPE_BIND_INDEX_BUFFER |
  97                                         PIPE_BIND_CONSTANT_BUFFER);
  98         if (!rctx->uploader)
  99                 return false;
 100
 101         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 102                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA, NULL);
 103                 rctx->rings.dma.flush = r600_flush_dma_ring;
 104                 rctx->ws->cs_set_flush_callback(rctx->rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 105         }
 106
 107         return true;
 108 }
 109
 110 void r600_common_context_cleanup(struct r600_common_context *rctx)
 111 {
 112         if (rctx->rings.gfx.cs) {
 113                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 114         }
 115         if (rctx->rings.dma.cs) {
 116                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 117         }
 118
 119         if (rctx->uploader) {
 120                 u_upload_destroy(rctx->uploader);
 121         }
 122
 123         util_slab_destroy(&rctx->pool_transfers);
 124
 125         if (rctx->allocator_so_filled_size) {
 126                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 127         }
 128 }
 129
 130 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 131 {
 132         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 133         struct r600_resource *rr = (struct r600_resource *)r;
 134
 135         if (r == NULL) {
 136                 return;
 137         }
 138
 139         /*
 140          * The idea is to compute a gross estimate of memory requirement of
 141          * each draw call. After each draw call, memory will be precisely
 142          * accounted. So the uncertainty is only on the current draw call.
 143          * In practice this gave very good estimate (+/- 10% of the target
 144          * memory limit).
 145          */
 146         if (rr->domains & RADEON_DOMAIN_GTT) {
 147                 rctx->gtt += rr->buf->size;
 148         }
 149         if (rr->domains & RADEON_DOMAIN_VRAM) {
 150                 rctx->vram += rr->buf->size;
 151         }
 152 }
 153
 154 /*
 155  * pipe_screen
 156  */
 157
 158 static const struct debug_named_value common_debug_options[] = {
 159         /* logging */
 160         { "tex", DBG_TEX, "Print texture info" },
 161         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 162         { "compute", DBG_COMPUTE, "Print compute info" },
 163         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 164         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 165
 166         /* features */
 167         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 168
 169         /* shaders */
 170         { "fs", DBG_FS, "Print fetch shaders" },
 171         { "vs", DBG_VS, "Print vertex shaders" },
 172         { "gs", DBG_GS, "Print geometry shaders" },
 173         { "ps", DBG_PS, "Print pixel shaders" },
 174         { "cs", DBG_CS, "Print compute shaders" },
 175
 176         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 177         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 178         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 179
 180         DEBUG_NAMED_VALUE_END /* must be last */
 181 };
 182
 183 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 184 {
 185         return "X.Org";
 186 }
 187
 188 static const char* r600_get_name(struct pipe_screen* pscreen)
 189 {
 190         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 191
 192         switch (rscreen->family) {
 193         case CHIP_R600: return "AMD R600";
 194         case CHIP_RV610: return "AMD RV610";
 195         case CHIP_RV630: return "AMD RV630";
 196         case CHIP_RV670: return "AMD RV670";
 197         case CHIP_RV620: return "AMD RV620";
 198         case CHIP_RV635: return "AMD RV635";
 199         case CHIP_RS780: return "AMD RS780";
 200         case CHIP_RS880: return "AMD RS880";
 201         case CHIP_RV770: return "AMD RV770";
 202         case CHIP_RV730: return "AMD RV730";
 203         case CHIP_RV710: return "AMD RV710";
 204         case CHIP_RV740: return "AMD RV740";
 205         case CHIP_CEDAR: return "AMD CEDAR";
 206         case CHIP_REDWOOD: return "AMD REDWOOD";
 207         case CHIP_JUNIPER: return "AMD JUNIPER";
 208         case CHIP_CYPRESS: return "AMD CYPRESS";
 209         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 210         case CHIP_PALM: return "AMD PALM";
 211         case CHIP_SUMO: return "AMD SUMO";
 212         case CHIP_SUMO2: return "AMD SUMO2";
 213         case CHIP_BARTS: return "AMD BARTS";
 214         case CHIP_TURKS: return "AMD TURKS";
 215         case CHIP_CAICOS: return "AMD CAICOS";
 216         case CHIP_CAYMAN: return "AMD CAYMAN";
 217         case CHIP_ARUBA: return "AMD ARUBA";
 218         case CHIP_TAHITI: return "AMD TAHITI";
 219         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 220         case CHIP_VERDE: return "AMD CAPE VERDE";
 221         case CHIP_OLAND: return "AMD OLAND";
 222         case CHIP_HAINAN: return "AMD HAINAN";
 223         case CHIP_BONAIRE: return "AMD BONAIRE";
 224         case CHIP_KAVERI: return "AMD KAVERI";
 225         case CHIP_KABINI: return "AMD KABINI";
 226         case CHIP_HAWAII: return "AMD HAWAII";
 227         default: return "AMD unknown";
 228         }
 229 }
 230
 231 static float r600_get_paramf(struct pipe_screen* pscreen,
 232                              enum pipe_capf param)
 233 {
 234         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 235
 236         switch (param) {
 237         case PIPE_CAPF_MAX_LINE_WIDTH:
 238         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 239         case PIPE_CAPF_MAX_POINT_WIDTH:
 240         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 241                 if (rscreen->family >= CHIP_CEDAR)
 242                         return 16384.0f;
 243                 else
 244                         return 8192.0f;
 245         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 246                 return 16.0f;
 247         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 248                 return 16.0f;
 249         case PIPE_CAPF_GUARD_BAND_LEFT:
 250         case PIPE_CAPF_GUARD_BAND_TOP:
 251         case PIPE_CAPF_GUARD_BAND_RIGHT:
 252         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 253                 return 0.0f;
 254         }
 255         return 0.0f;
 256 }
 257
 258 static int r600_get_video_param(struct pipe_screen *screen,
 259                                 enum pipe_video_profile profile,
 260                                 enum pipe_video_entrypoint entrypoint,
 261                                 enum pipe_video_cap param)
 262 {
 263         switch (param) {
 264         case PIPE_VIDEO_CAP_SUPPORTED:
 265                 return vl_profile_supported(screen, profile, entrypoint);
 266         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 267                 return 1;
 268         case PIPE_VIDEO_CAP_MAX_WIDTH:
 269         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 270                 return vl_video_buffer_max_size(screen);
 271         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 272                 return PIPE_FORMAT_NV12;
 273         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 274                 return false;
 275         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 276                 return false;
 277         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 278                 return true;
 279         case PIPE_VIDEO_CAP_MAX_LEVEL:
 280                 return vl_level_supported(screen, profile);
 281         default:
 282                 return 0;
 283         }
 284 }
 285
 286 const char *r600_get_llvm_processor_name(enum radeon_family family)
 287 {
 288         switch (family) {
 289         case CHIP_R600:
 290         case CHIP_RV630:
 291         case CHIP_RV635:
 292         case CHIP_RV670:
 293                 return "r600";
 294         case CHIP_RV610:
 295         case CHIP_RV620:
 296         case CHIP_RS780:
 297         case CHIP_RS880:
 298                 return "rs880";
 299         case CHIP_RV710:
 300                 return "rv710";
 301         case CHIP_RV730:
 302                 return "rv730";
 303         case CHIP_RV740:
 304         case CHIP_RV770:
 305                 return "rv770";
 306         case CHIP_PALM:
 307         case CHIP_CEDAR:
 308                 return "cedar";
 309         case CHIP_SUMO:
 310         case CHIP_SUMO2:
 311                 return "sumo";
 312         case CHIP_REDWOOD:
 313                 return "redwood";
 314         case CHIP_JUNIPER:
 315                 return "juniper";
 316         case CHIP_HEMLOCK:
 317         case CHIP_CYPRESS:
 318                 return "cypress";
 319         case CHIP_BARTS:
 320                 return "barts";
 321         case CHIP_TURKS:
 322                 return "turks";
 323         case CHIP_CAICOS:
 324                 return "caicos";
 325         case CHIP_CAYMAN:
 326         case CHIP_ARUBA:
 327                 return "cayman";
 328
 329         case CHIP_TAHITI: return "tahiti";
 330         case CHIP_PITCAIRN: return "pitcairn";
 331         case CHIP_VERDE: return "verde";
 332         case CHIP_OLAND: return "oland";
 333 #if HAVE_LLVM <= 0x0303
 334         default:
 335                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 336                         __func__, family);
 337                 return "SI";
 338 #else
 339         case CHIP_HAINAN: return "hainan";
 340         case CHIP_BONAIRE: return "bonaire";
 341         case CHIP_KABINI: return "kabini";
 342         case CHIP_KAVERI: return "kaveri";
 343         case CHIP_HAWAII: return "hawaii";
 344         default: return "";
 345 #endif
 346         }
 347 }
 348
 349 static int r600_get_compute_param(struct pipe_screen *screen,
 350         enum pipe_compute_cap param,
 351         void *ret)
 352 {
 353         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 354
 355         //TODO: select these params by asic
 356         switch (param) {
 357         case PIPE_COMPUTE_CAP_IR_TARGET: {
 358                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 359                 if (ret) {
 360                         sprintf(ret, "%s-r600--", gpu);
 361                 }
 362                 return (8 + strlen(gpu)) * sizeof(char);
 363         }
 364         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 365                 if (ret) {
 366                         uint64_t *grid_dimension = ret;
 367                         grid_dimension[0] = 3;
 368                 }
 369                 return 1 * sizeof(uint64_t);
 370
 371         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 372                 if (ret) {
 373                         uint64_t *grid_size = ret;
 374                         grid_size[0] = 65535;
 375                         grid_size[1] = 65535;
 376                         grid_size[2] = 1;
 377                 }
 378                 return 3 * sizeof(uint64_t) ;
 379
 380         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 381                 if (ret) {
 382                         uint64_t *block_size = ret;
 383                         block_size[0] = 256;
 384                         block_size[1] = 256;
 385                         block_size[2] = 256;
 386                 }
 387                 return 3 * sizeof(uint64_t);
 388
 389         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 390                 if (ret) {
 391                         uint64_t *max_threads_per_block = ret;
 392                         *max_threads_per_block = 256;
 393                 }
 394                 return sizeof(uint64_t);
 395
 396         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 397                 if (ret) {
 398                         uint64_t *max_global_size = ret;
 399                         /* XXX: This is what the proprietary driver reports, we
 400                          * may want to use a different value. */
 401                         /* XXX: Not sure what to put here for SI. */
 402                         if (rscreen->chip_class >= SI)
 403                                 *max_global_size = 2000000000;
 404                         else
 405                                 *max_global_size = 201326592;
 406                 }
 407                 return sizeof(uint64_t);
 408
 409         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 410                 if (ret) {
 411                         uint64_t *max_local_size = ret;
 412                         /* Value reported by the closed source driver. */
 413                         *max_local_size = 32768;
 414                 }
 415                 return sizeof(uint64_t);
 416
 417         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 418                 if (ret) {
 419                         uint64_t *max_input_size = ret;
 420                         /* Value reported by the closed source driver. */
 421                         *max_input_size = 1024;
 422                 }
 423                 return sizeof(uint64_t);
 424
 425         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 426                 if (ret) {
 427                         uint64_t max_global_size;
 428                         uint64_t *max_mem_alloc_size = ret;
 429                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 430                         /* OpenCL requres this value be at least
 431                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 432                          * I'm really not sure what value to report here, but
 433                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 434                          */
 435                         *max_mem_alloc_size = max_global_size / 4;
 436                 }
 437                 return sizeof(uint64_t);
 438
 439         default:
 440                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 441                 return 0;
 442         }
 443 }
 444
 445 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 446 {
 447         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 448
 449         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 450                         rscreen->info.r600_clock_crystal_freq;
 451 }
 452
 453 static int r600_get_driver_query_info(struct pipe_screen *screen,
 454                                       unsigned index,
 455                                       struct pipe_driver_query_info *info)
 456 {
 457         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 458         struct pipe_driver_query_info list[] = {
 459                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 460                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 461                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 462                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 463         };
 464
 465         if (!info)
 466                 return Elements(list);
 467
 468         if (index >= Elements(list))
 469                 return 0;
 470
 471         *info = list[index];
 472         return 1;
 473 }
 474
 475 static void r600_fence_reference(struct pipe_screen *screen,
 476                                  struct pipe_fence_handle **ptr,
 477                                  struct pipe_fence_handle *fence)
 478 {
 479         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 480
 481         rws->fence_reference(ptr, fence);
 482 }
 483
 484 static boolean r600_fence_signalled(struct pipe_screen *screen,
 485                                     struct pipe_fence_handle *fence)
 486 {
 487         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 488
 489         return rws->fence_wait(rws, fence, 0);
 490 }
 491
 492 static boolean r600_fence_finish(struct pipe_screen *screen,
 493                                  struct pipe_fence_handle *fence,
 494                                  uint64_t timeout)
 495 {
 496         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 497
 498         return rws->fence_wait(rws, fence, timeout);
 499 }
 500
 501 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 502                                   uint32_t tiling_config)
 503 {
 504         switch ((tiling_config & 0xe) >> 1) {
 505         case 0:
 506                 rscreen->tiling_info.num_channels = 1;
 507                 break;
 508         case 1:
 509                 rscreen->tiling_info.num_channels = 2;
 510                 break;
 511         case 2:
 512                 rscreen->tiling_info.num_channels = 4;
 513                 break;
 514         case 3:
 515                 rscreen->tiling_info.num_channels = 8;
 516                 break;
 517         default:
 518                 return false;
 519         }
 520
 521         switch ((tiling_config & 0x30) >> 4) {
 522         case 0:
 523                 rscreen->tiling_info.num_banks = 4;
 524                 break;
 525         case 1:
 526                 rscreen->tiling_info.num_banks = 8;
 527                 break;
 528         default:
 529                 return false;
 530
 531         }
 532         switch ((tiling_config & 0xc0) >> 6) {
 533         case 0:
 534                 rscreen->tiling_info.group_bytes = 256;
 535                 break;
 536         case 1:
 537                 rscreen->tiling_info.group_bytes = 512;
 538                 break;
 539         default:
 540                 return false;
 541         }
 542         return true;
 543 }
 544
 545 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 546                                        uint32_t tiling_config)
 547 {
 548         switch (tiling_config & 0xf) {
 549         case 0:
 550                 rscreen->tiling_info.num_channels = 1;
 551                 break;
 552         case 1:
 553                 rscreen->tiling_info.num_channels = 2;
 554                 break;
 555         case 2:
 556                 rscreen->tiling_info.num_channels = 4;
 557                 break;
 558         case 3:
 559                 rscreen->tiling_info.num_channels = 8;
 560                 break;
 561         default:
 562                 return false;
 563         }
 564
 565         switch ((tiling_config & 0xf0) >> 4) {
 566         case 0:
 567                 rscreen->tiling_info.num_banks = 4;
 568                 break;
 569         case 1:
 570                 rscreen->tiling_info.num_banks = 8;
 571                 break;
 572         case 2:
 573                 rscreen->tiling_info.num_banks = 16;
 574                 break;
 575         default:
 576                 return false;
 577         }
 578
 579         switch ((tiling_config & 0xf00) >> 8) {
 580         case 0:
 581                 rscreen->tiling_info.group_bytes = 256;
 582                 break;
 583         case 1:
 584                 rscreen->tiling_info.group_bytes = 512;
 585                 break;
 586         default:
 587                 return false;
 588         }
 589         return true;
 590 }
 591
 592 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 593 {
 594         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 595
 596         /* set default group bytes, overridden by tiling info ioctl */
 597         if (rscreen->chip_class <= R700) {
 598                 rscreen->tiling_info.group_bytes = 256;
 599         } else {
 600                 rscreen->tiling_info.group_bytes = 512;
 601         }
 602
 603         if (!tiling_config)
 604                 return true;
 605
 606         if (rscreen->chip_class <= R700) {
 607                 return r600_interpret_tiling(rscreen, tiling_config);
 608         } else {
 609                 return evergreen_interpret_tiling(rscreen, tiling_config);
 610         }
 611 }
 612
 613 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 614                                                   const struct pipe_resource *templ)
 615 {
 616         if (templ->target == PIPE_BUFFER) {
 617                 return r600_buffer_create(screen, templ, 4096);
 618         } else {
 619                 return r600_texture_create(screen, templ);
 620         }
 621 }
 622
 623 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 624                              struct radeon_winsys *ws)
 625 {
 626         ws->query_info(ws, &rscreen->info);
 627
 628         rscreen->b.get_name = r600_get_name;
 629         rscreen->b.get_vendor = r600_get_vendor;
 630         rscreen->b.get_compute_param = r600_get_compute_param;
 631         rscreen->b.get_paramf = r600_get_paramf;
 632         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 633         rscreen->b.get_timestamp = r600_get_timestamp;
 634         rscreen->b.fence_finish = r600_fence_finish;
 635         rscreen->b.fence_reference = r600_fence_reference;
 636         rscreen->b.fence_signalled = r600_fence_signalled;
 637         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 638
 639         if (rscreen->info.has_uvd) {
 640                 rscreen->b.get_video_param = rvid_get_video_param;
 641                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 642         } else {
 643                 rscreen->b.get_video_param = r600_get_video_param;
 644                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 645         }
 646
 647         r600_init_screen_texture_functions(rscreen);
 648
 649         rscreen->ws = ws;
 650         rscreen->family = rscreen->info.family;
 651         rscreen->chip_class = rscreen->info.chip_class;
 652         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 653
 654         if (!r600_init_tiling(rscreen)) {
 655                 return false;
 656         }
 657         util_format_s3tc_init();
 658         pipe_mutex_init(rscreen->aux_context_lock);
 659
 660         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 661                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 662                                                                                 PIPE_BIND_CUSTOM,
 663                                                                                 PIPE_USAGE_STAGING,
 664                                                                                 4096);
 665                 if (rscreen->trace_bo) {
 666                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 667                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 668                 }
 669         }
 670
 671         return true;
 672 }
 673
 674 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 675 {
 676         pipe_mutex_destroy(rscreen->aux_context_lock);
 677         rscreen->aux_context->destroy(rscreen->aux_context);
 678
 679         if (rscreen->trace_bo) {
 680                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 681                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 682         }
 683
 684         rscreen->ws->destroy(rscreen->ws);
 685         FREE(rscreen);
 686 }
 687
 688 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 689 {
 690         struct tgsi_parse_context parse;
 691
 692         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 693                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 694                 return ~0;
 695         }
 696         return parse.FullHeader.Processor.Processor;
 697 }
 698
 699 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 700                           const struct tgsi_token *tokens)
 701 {
 702         /* Compute shader don't have tgsi_tokens */
 703         if (!tokens)
 704                 return (rscreen->debug_flags & DBG_CS) != 0;
 705
 706         switch (tgsi_get_processor_type(tokens)) {
 707         case TGSI_PROCESSOR_VERTEX:
 708                 return (rscreen->debug_flags & DBG_VS) != 0;
 709         case TGSI_PROCESSOR_GEOMETRY:
 710                 return (rscreen->debug_flags & DBG_GS) != 0;
 711         case TGSI_PROCESSOR_FRAGMENT:
 712                 return (rscreen->debug_flags & DBG_PS) != 0;
 713         case TGSI_PROCESSOR_COMPUTE:
 714                 return (rscreen->debug_flags & DBG_CS) != 0;
 715         default:
 716                 return false;
 717         }
 718 }
 719
 720 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 721                               unsigned offset, unsigned size, unsigned value)
 722 {
 723         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 724
 725         pipe_mutex_lock(rscreen->aux_context_lock);
 726         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 727         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 728         pipe_mutex_unlock(rscreen->aux_context_lock);
 729 }