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radeonsi: remove Constant Engine support
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112
113 if (ctx->chip_class >= GFX9) {
114 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
115 * counters) must immediately precede every timestamp event to
116 * prevent a GPU hang on GFX9.
117 *
118 * Occlusion queries don't need to do it here, because they
119 * always do ZPASS_DONE before the timestamp.
120 */
121 if (ctx->chip_class == GFX9 &&
122 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
123 query_type != PIPE_QUERY_OCCLUSION_PREDICATE) {
124 struct r600_resource *scratch = ctx->eop_bug_scratch;
125
126 assert(16 * ctx->screen->info.num_render_backends <=
127 scratch->b.b.width0);
128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
129 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
130 radeon_emit(cs, scratch->gpu_address);
131 radeon_emit(cs, scratch->gpu_address >> 32);
132
133 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
134 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
135 }
136
137 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
138 radeon_emit(cs, op);
139 radeon_emit(cs, EOP_DATA_SEL(data_sel));
140 radeon_emit(cs, va); /* address lo */
141 radeon_emit(cs, va >> 32); /* address hi */
142 radeon_emit(cs, new_fence); /* immediate data lo */
143 radeon_emit(cs, 0); /* immediate data hi */
144 radeon_emit(cs, 0); /* unused */
145 } else {
146 if (ctx->chip_class == CIK ||
147 ctx->chip_class == VI) {
148 struct r600_resource *scratch = ctx->eop_bug_scratch;
149 uint64_t va = scratch->gpu_address;
150
151 /* Two EOP events are required to make all engines go idle
152 * (and optional cache flushes executed) before the timestamp
153 * is written.
154 */
155 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
156 radeon_emit(cs, op);
157 radeon_emit(cs, va);
158 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
159 radeon_emit(cs, 0); /* immediate data */
160 radeon_emit(cs, 0); /* unused */
161
162 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
163 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
164 }
165
166 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
167 radeon_emit(cs, op);
168 radeon_emit(cs, va);
169 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
170 radeon_emit(cs, new_fence); /* immediate data */
171 radeon_emit(cs, 0); /* unused */
172 }
173
174 if (buf)
175 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
176 RADEON_PRIO_QUERY);
177 }
178
179 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
180 {
181 unsigned dwords = 6;
182
183 if (screen->chip_class == CIK ||
184 screen->chip_class == VI)
185 dwords *= 2;
186
187 if (!screen->info.has_virtual_memory)
188 dwords += 2;
189
190 return dwords;
191 }
192
193 void r600_gfx_wait_fence(struct r600_common_context *ctx,
194 uint64_t va, uint32_t ref, uint32_t mask)
195 {
196 struct radeon_winsys_cs *cs = ctx->gfx.cs;
197
198 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
199 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
200 radeon_emit(cs, va);
201 radeon_emit(cs, va >> 32);
202 radeon_emit(cs, ref); /* reference value */
203 radeon_emit(cs, mask); /* mask */
204 radeon_emit(cs, 4); /* poll interval */
205 }
206
207 void r600_draw_rectangle(struct blitter_context *blitter,
208 int x1, int y1, int x2, int y2, float depth,
209 enum blitter_attrib_type type,
210 const union pipe_color_union *attrib)
211 {
212 struct r600_common_context *rctx =
213 (struct r600_common_context*)util_blitter_get_pipe(blitter);
214 struct pipe_viewport_state viewport;
215 struct pipe_resource *buf = NULL;
216 unsigned offset = 0;
217 float *vb;
218
219 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
220 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
221 return;
222 }
223
224 /* Some operations (like color resolve on r6xx) don't work
225 * with the conventional primitive types.
226 * One that works is PT_RECTLIST, which we use here. */
227
228 /* setup viewport */
229 viewport.scale[0] = 1.0f;
230 viewport.scale[1] = 1.0f;
231 viewport.scale[2] = 1.0f;
232 viewport.translate[0] = 0.0f;
233 viewport.translate[1] = 0.0f;
234 viewport.translate[2] = 0.0f;
235 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
236
237 /* Upload vertices. The hw rectangle has only 3 vertices,
238 * I guess the 4th one is derived from the first 3.
239 * The vertex specification should match u_blitter's vertex element state. */
240 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
241 rctx->screen->info.tcc_cache_line_size,
242 &offset, &buf, (void**)&vb);
243 if (!buf)
244 return;
245
246 vb[0] = x1;
247 vb[1] = y1;
248 vb[2] = depth;
249 vb[3] = 1;
250
251 vb[8] = x1;
252 vb[9] = y2;
253 vb[10] = depth;
254 vb[11] = 1;
255
256 vb[16] = x2;
257 vb[17] = y1;
258 vb[18] = depth;
259 vb[19] = 1;
260
261 if (attrib) {
262 memcpy(vb+4, attrib->f, sizeof(float)*4);
263 memcpy(vb+12, attrib->f, sizeof(float)*4);
264 memcpy(vb+20, attrib->f, sizeof(float)*4);
265 }
266
267 /* draw */
268 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
269 R600_PRIM_RECTANGLE_LIST, 3, 2);
270 pipe_resource_reference(&buf, NULL);
271 }
272
273 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
274 {
275 struct radeon_winsys_cs *cs = rctx->dma.cs;
276
277 /* NOP waits for idle on Evergreen and later. */
278 if (rctx->chip_class >= CIK)
279 radeon_emit(cs, 0x00000000); /* NOP */
280 else if (rctx->chip_class >= EVERGREEN)
281 radeon_emit(cs, 0xf0000000); /* NOP */
282 else {
283 /* TODO: R600-R700 should use the FENCE packet.
284 * CS checker support is required. */
285 }
286 }
287
288 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
289 struct r600_resource *dst, struct r600_resource *src)
290 {
291 uint64_t vram = ctx->dma.cs->used_vram;
292 uint64_t gtt = ctx->dma.cs->used_gart;
293
294 if (dst) {
295 vram += dst->vram_usage;
296 gtt += dst->gart_usage;
297 }
298 if (src) {
299 vram += src->vram_usage;
300 gtt += src->gart_usage;
301 }
302
303 /* Flush the GFX IB if DMA depends on it. */
304 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
305 ((dst &&
306 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
307 RADEON_USAGE_READWRITE)) ||
308 (src &&
309 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
310 RADEON_USAGE_WRITE))))
311 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
312
313 /* Flush if there's not enough space, or if the memory usage per IB
314 * is too large.
315 *
316 * IBs using too little memory are limited by the IB submission overhead.
317 * IBs using too much memory are limited by the kernel/TTM overhead.
318 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
319 *
320 * This heuristic makes sure that DMA requests are executed
321 * very soon after the call is made and lowers memory usage.
322 * It improves texture upload performance by keeping the DMA
323 * engine busy while uploads are being submitted.
324 */
325 num_dw++; /* for emit_wait_idle below */
326 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
327 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
328 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
329 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
330 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
331 }
332
333 /* Wait for idle if either buffer has been used in the IB before to
334 * prevent read-after-write hazards.
335 */
336 if ((dst &&
337 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
338 RADEON_USAGE_READWRITE)) ||
339 (src &&
340 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
341 RADEON_USAGE_WRITE)))
342 r600_dma_emit_wait_idle(ctx);
343
344 /* If GPUVM is not supported, the CS checker needs 2 entries
345 * in the buffer list per packet, which has to be done manually.
346 */
347 if (ctx->screen->info.has_virtual_memory) {
348 if (dst)
349 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
350 RADEON_USAGE_WRITE,
351 RADEON_PRIO_SDMA_BUFFER);
352 if (src)
353 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
354 RADEON_USAGE_READ,
355 RADEON_PRIO_SDMA_BUFFER);
356 }
357
358 /* this function is called before all DMA calls, so increment this. */
359 ctx->num_dma_calls++;
360 }
361
362 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
363 {
364 }
365
366 void r600_preflush_suspend_features(struct r600_common_context *ctx)
367 {
368 /* suspend queries */
369 if (!LIST_IS_EMPTY(&ctx->active_queries))
370 r600_suspend_queries(ctx);
371
372 ctx->streamout.suspended = false;
373 if (ctx->streamout.begin_emitted) {
374 r600_emit_streamout_end(ctx);
375 ctx->streamout.suspended = true;
376 }
377 }
378
379 void r600_postflush_resume_features(struct r600_common_context *ctx)
380 {
381 if (ctx->streamout.suspended) {
382 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
383 r600_streamout_buffers_dirty(ctx);
384 }
385
386 /* resume queries */
387 if (!LIST_IS_EMPTY(&ctx->active_queries))
388 r600_resume_queries(ctx);
389 }
390
391 static void r600_flush_from_st(struct pipe_context *ctx,
392 struct pipe_fence_handle **fence,
393 unsigned flags)
394 {
395 struct pipe_screen *screen = ctx->screen;
396 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
397 struct radeon_winsys *ws = rctx->ws;
398 struct pipe_fence_handle *gfx_fence = NULL;
399 struct pipe_fence_handle *sdma_fence = NULL;
400 bool deferred_fence = false;
401 unsigned rflags = RADEON_FLUSH_ASYNC;
402
403 if (flags & PIPE_FLUSH_END_OF_FRAME)
404 rflags |= RADEON_FLUSH_END_OF_FRAME;
405
406 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
407 if (rctx->dma.cs)
408 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
409
410 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
411 if (fence)
412 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
413 if (!(flags & PIPE_FLUSH_DEFERRED))
414 ws->cs_sync_flush(rctx->gfx.cs);
415 } else {
416 /* Instead of flushing, create a deferred fence. Constraints:
417 * - The state tracker must allow a deferred flush.
418 * - The state tracker must request a fence.
419 * Thread safety in fence_finish must be ensured by the state tracker.
420 */
421 if (flags & PIPE_FLUSH_DEFERRED && fence) {
422 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
423 deferred_fence = true;
424 } else {
425 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
426 }
427 }
428
429 /* Both engines can signal out of order, so we need to keep both fences. */
430 if (fence) {
431 struct r600_multi_fence *multi_fence =
432 CALLOC_STRUCT(r600_multi_fence);
433 if (!multi_fence)
434 return;
435
436 multi_fence->reference.count = 1;
437 /* If both fences are NULL, fence_finish will always return true. */
438 multi_fence->gfx = gfx_fence;
439 multi_fence->sdma = sdma_fence;
440
441 if (deferred_fence) {
442 multi_fence->gfx_unflushed.ctx = rctx;
443 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
444 }
445
446 screen->fence_reference(screen, fence, NULL);
447 *fence = (struct pipe_fence_handle*)multi_fence;
448 }
449
450 if (!(flags & PIPE_FLUSH_DEFERRED)) {
451 if (rctx->dma.cs)
452 ws->cs_sync_flush(rctx->dma.cs);
453 ws->cs_sync_flush(rctx->gfx.cs);
454 }
455 }
456
457 static void r600_flush_dma_ring(void *ctx, unsigned flags,
458 struct pipe_fence_handle **fence)
459 {
460 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
461 struct radeon_winsys_cs *cs = rctx->dma.cs;
462 struct radeon_saved_cs saved;
463 bool check_vm =
464 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
465 rctx->check_vm_faults;
466
467 if (!radeon_emitted(cs, 0)) {
468 if (fence)
469 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
470 return;
471 }
472
473 if (check_vm)
474 radeon_save_cs(rctx->ws, cs, &saved, true);
475
476 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
477 if (fence)
478 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
479
480 if (check_vm) {
481 /* Use conservative timeout 800ms, after which we won't wait any
482 * longer and assume the GPU is hung.
483 */
484 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
485
486 rctx->check_vm_faults(rctx, &saved, RING_DMA);
487 radeon_clear_saved_cs(&saved);
488 }
489 }
490
491 /**
492 * Store a linearized copy of all chunks of \p cs together with the buffer
493 * list in \p saved.
494 */
495 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
496 struct radeon_saved_cs *saved, bool get_buffer_list)
497 {
498 void *buf;
499 unsigned i;
500
501 /* Save the IB chunks. */
502 saved->num_dw = cs->prev_dw + cs->current.cdw;
503 saved->ib = MALLOC(4 * saved->num_dw);
504 if (!saved->ib)
505 goto oom;
506
507 buf = saved->ib;
508 for (i = 0; i < cs->num_prev; ++i) {
509 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
510 buf += cs->prev[i].cdw;
511 }
512 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
513
514 if (!get_buffer_list)
515 return;
516
517 /* Save the buffer list. */
518 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
519 saved->bo_list = CALLOC(saved->bo_count,
520 sizeof(saved->bo_list[0]));
521 if (!saved->bo_list) {
522 FREE(saved->ib);
523 goto oom;
524 }
525 ws->cs_get_buffer_list(cs, saved->bo_list);
526
527 return;
528
529 oom:
530 fprintf(stderr, "%s: out of memory\n", __func__);
531 memset(saved, 0, sizeof(*saved));
532 }
533
534 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
535 {
536 FREE(saved->ib);
537 FREE(saved->bo_list);
538
539 memset(saved, 0, sizeof(*saved));
540 }
541
542 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
543 {
544 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
545 unsigned latest = rctx->ws->query_value(rctx->ws,
546 RADEON_GPU_RESET_COUNTER);
547
548 if (rctx->gpu_reset_counter == latest)
549 return PIPE_NO_RESET;
550
551 rctx->gpu_reset_counter = latest;
552 return PIPE_UNKNOWN_CONTEXT_RESET;
553 }
554
555 static void r600_set_debug_callback(struct pipe_context *ctx,
556 const struct pipe_debug_callback *cb)
557 {
558 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
559
560 if (cb)
561 rctx->debug = *cb;
562 else
563 memset(&rctx->debug, 0, sizeof(rctx->debug));
564 }
565
566 static void r600_set_device_reset_callback(struct pipe_context *ctx,
567 const struct pipe_device_reset_callback *cb)
568 {
569 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
570
571 if (cb)
572 rctx->device_reset_callback = *cb;
573 else
574 memset(&rctx->device_reset_callback, 0,
575 sizeof(rctx->device_reset_callback));
576 }
577
578 bool r600_check_device_reset(struct r600_common_context *rctx)
579 {
580 enum pipe_reset_status status;
581
582 if (!rctx->device_reset_callback.reset)
583 return false;
584
585 if (!rctx->b.get_device_reset_status)
586 return false;
587
588 status = rctx->b.get_device_reset_status(&rctx->b);
589 if (status == PIPE_NO_RESET)
590 return false;
591
592 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
593 return true;
594 }
595
596 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
597 struct pipe_resource *dst,
598 uint64_t offset, uint64_t size,
599 unsigned value)
600 {
601 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
602
603 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
604 }
605
606 static bool r600_resource_commit(struct pipe_context *pctx,
607 struct pipe_resource *resource,
608 unsigned level, struct pipe_box *box,
609 bool commit)
610 {
611 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
612 struct r600_resource *res = r600_resource(resource);
613
614 /*
615 * Since buffer commitment changes cannot be pipelined, we need to
616 * (a) flush any pending commands that refer to the buffer we're about
617 * to change, and
618 * (b) wait for threaded submit to finish, including those that were
619 * triggered by some other, earlier operation.
620 */
621 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
622 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
623 res->buf, RADEON_USAGE_READWRITE)) {
624 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
625 }
626 if (radeon_emitted(ctx->dma.cs, 0) &&
627 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
628 res->buf, RADEON_USAGE_READWRITE)) {
629 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
630 }
631
632 ctx->ws->cs_sync_flush(ctx->dma.cs);
633 ctx->ws->cs_sync_flush(ctx->gfx.cs);
634
635 assert(resource->target == PIPE_BUFFER);
636
637 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
638 }
639
640 bool r600_common_context_init(struct r600_common_context *rctx,
641 struct r600_common_screen *rscreen,
642 unsigned context_flags)
643 {
644 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
645 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
646
647 rctx->screen = rscreen;
648 rctx->ws = rscreen->ws;
649 rctx->family = rscreen->family;
650 rctx->chip_class = rscreen->chip_class;
651
652 rctx->b.invalidate_resource = r600_invalidate_resource;
653 rctx->b.resource_commit = r600_resource_commit;
654 rctx->b.transfer_map = u_transfer_map_vtbl;
655 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
656 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
657 rctx->b.texture_subdata = u_default_texture_subdata;
658 rctx->b.memory_barrier = r600_memory_barrier;
659 rctx->b.flush = r600_flush_from_st;
660 rctx->b.set_debug_callback = r600_set_debug_callback;
661 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
662
663 /* evergreen_compute.c has a special codepath for global buffers.
664 * Everything else can use the direct path.
665 */
666 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
667 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
668 rctx->b.buffer_subdata = u_default_buffer_subdata;
669 else
670 rctx->b.buffer_subdata = r600_buffer_subdata;
671
672 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
673 rctx->b.get_device_reset_status = r600_get_reset_status;
674 rctx->gpu_reset_counter =
675 rctx->ws->query_value(rctx->ws,
676 RADEON_GPU_RESET_COUNTER);
677 }
678
679 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
680
681 r600_init_context_texture_functions(rctx);
682 r600_init_viewport_functions(rctx);
683 r600_streamout_init(rctx);
684 r600_query_init(rctx);
685 cayman_init_msaa(&rctx->b);
686
687 if (rctx->chip_class == CIK ||
688 rctx->chip_class == VI ||
689 rctx->chip_class == GFX9) {
690 rctx->eop_bug_scratch = (struct r600_resource*)
691 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
692 16 * rscreen->info.num_render_backends);
693 if (!rctx->eop_bug_scratch)
694 return false;
695 }
696
697 rctx->allocator_zeroed_memory =
698 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
699 0, PIPE_USAGE_DEFAULT, 0, true);
700 if (!rctx->allocator_zeroed_memory)
701 return false;
702
703 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
704 0, PIPE_USAGE_STREAM);
705 if (!rctx->b.stream_uploader)
706 return false;
707
708 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
709 0, PIPE_USAGE_DEFAULT);
710 if (!rctx->b.const_uploader)
711 return false;
712
713 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
714 if (!rctx->ctx)
715 return false;
716
717 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
718 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
719 r600_flush_dma_ring,
720 rctx);
721 rctx->dma.flush = r600_flush_dma_ring;
722 }
723
724 return true;
725 }
726
727 void r600_common_context_cleanup(struct r600_common_context *rctx)
728 {
729 unsigned i,j;
730
731 /* Release DCC stats. */
732 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
733 assert(!rctx->dcc_stats[i].query_active);
734
735 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
736 if (rctx->dcc_stats[i].ps_stats[j])
737 rctx->b.destroy_query(&rctx->b,
738 rctx->dcc_stats[i].ps_stats[j]);
739
740 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
741 }
742
743 if (rctx->query_result_shader)
744 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
745
746 if (rctx->gfx.cs)
747 rctx->ws->cs_destroy(rctx->gfx.cs);
748 if (rctx->dma.cs)
749 rctx->ws->cs_destroy(rctx->dma.cs);
750 if (rctx->ctx)
751 rctx->ws->ctx_destroy(rctx->ctx);
752
753 if (rctx->b.stream_uploader)
754 u_upload_destroy(rctx->b.stream_uploader);
755 if (rctx->b.const_uploader)
756 u_upload_destroy(rctx->b.const_uploader);
757
758 slab_destroy_child(&rctx->pool_transfers);
759 slab_destroy_child(&rctx->pool_transfers_unsync);
760
761 if (rctx->allocator_zeroed_memory) {
762 u_suballocator_destroy(rctx->allocator_zeroed_memory);
763 }
764 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
765 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
766 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
767 }
768
769 /*
770 * pipe_screen
771 */
772
773 static const struct debug_named_value common_debug_options[] = {
774 /* logging */
775 { "tex", DBG_TEX, "Print texture info" },
776 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
777 { "compute", DBG_COMPUTE, "Print compute info" },
778 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
779 { "info", DBG_INFO, "Print driver information" },
780
781 /* shaders */
782 { "fs", DBG_FS, "Print fetch shaders" },
783 { "vs", DBG_VS, "Print vertex shaders" },
784 { "gs", DBG_GS, "Print geometry shaders" },
785 { "ps", DBG_PS, "Print pixel shaders" },
786 { "cs", DBG_CS, "Print compute shaders" },
787 { "tcs", DBG_TCS, "Print tessellation control shaders" },
788 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
789 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
790 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
791 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
792 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
793 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
794 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
795
796 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
797 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
798 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
799 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
800
801 /* features */
802 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
803 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
804 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
805 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
806 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
807 { "notiling", DBG_NO_TILING, "Disable tiling" },
808 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
809 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
810 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
811 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
812 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
813 { "nodcc", DBG_NO_DCC, "Disable DCC." },
814 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
815 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
816 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
817 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
818 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
819 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
820
821 DEBUG_NAMED_VALUE_END /* must be last */
822 };
823
824 static const char* r600_get_vendor(struct pipe_screen* pscreen)
825 {
826 return "X.Org";
827 }
828
829 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
830 {
831 return "AMD";
832 }
833
834 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
835 {
836 if (!ws->get_chip_name)
837 return NULL;
838 return ws->get_chip_name(ws);
839 }
840
841 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
842 {
843 switch (rscreen->info.family) {
844 case CHIP_R600: return "AMD R600";
845 case CHIP_RV610: return "AMD RV610";
846 case CHIP_RV630: return "AMD RV630";
847 case CHIP_RV670: return "AMD RV670";
848 case CHIP_RV620: return "AMD RV620";
849 case CHIP_RV635: return "AMD RV635";
850 case CHIP_RS780: return "AMD RS780";
851 case CHIP_RS880: return "AMD RS880";
852 case CHIP_RV770: return "AMD RV770";
853 case CHIP_RV730: return "AMD RV730";
854 case CHIP_RV710: return "AMD RV710";
855 case CHIP_RV740: return "AMD RV740";
856 case CHIP_CEDAR: return "AMD CEDAR";
857 case CHIP_REDWOOD: return "AMD REDWOOD";
858 case CHIP_JUNIPER: return "AMD JUNIPER";
859 case CHIP_CYPRESS: return "AMD CYPRESS";
860 case CHIP_HEMLOCK: return "AMD HEMLOCK";
861 case CHIP_PALM: return "AMD PALM";
862 case CHIP_SUMO: return "AMD SUMO";
863 case CHIP_SUMO2: return "AMD SUMO2";
864 case CHIP_BARTS: return "AMD BARTS";
865 case CHIP_TURKS: return "AMD TURKS";
866 case CHIP_CAICOS: return "AMD CAICOS";
867 case CHIP_CAYMAN: return "AMD CAYMAN";
868 case CHIP_ARUBA: return "AMD ARUBA";
869 case CHIP_TAHITI: return "AMD TAHITI";
870 case CHIP_PITCAIRN: return "AMD PITCAIRN";
871 case CHIP_VERDE: return "AMD CAPE VERDE";
872 case CHIP_OLAND: return "AMD OLAND";
873 case CHIP_HAINAN: return "AMD HAINAN";
874 case CHIP_BONAIRE: return "AMD BONAIRE";
875 case CHIP_KAVERI: return "AMD KAVERI";
876 case CHIP_KABINI: return "AMD KABINI";
877 case CHIP_HAWAII: return "AMD HAWAII";
878 case CHIP_MULLINS: return "AMD MULLINS";
879 case CHIP_TONGA: return "AMD TONGA";
880 case CHIP_ICELAND: return "AMD ICELAND";
881 case CHIP_CARRIZO: return "AMD CARRIZO";
882 case CHIP_FIJI: return "AMD FIJI";
883 case CHIP_POLARIS10: return "AMD POLARIS10";
884 case CHIP_POLARIS11: return "AMD POLARIS11";
885 case CHIP_POLARIS12: return "AMD POLARIS12";
886 case CHIP_STONEY: return "AMD STONEY";
887 case CHIP_VEGA10: return "AMD VEGA10";
888 case CHIP_RAVEN: return "AMD RAVEN";
889 default: return "AMD unknown";
890 }
891 }
892
893 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
894 {
895 /* Don't use the cache if shader dumping is enabled. */
896 if (rscreen->debug_flags &
897 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
898 return;
899
900 uint32_t mesa_timestamp;
901 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
902 &mesa_timestamp)) {
903 char *timestamp_str;
904 int res = -1;
905 if (rscreen->chip_class < SI) {
906 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
907 }
908 #if HAVE_LLVM
909 else {
910 uint32_t llvm_timestamp;
911 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
912 &llvm_timestamp)) {
913 res = asprintf(&timestamp_str, "%u_%u",
914 mesa_timestamp, llvm_timestamp);
915 }
916 }
917 #endif
918 if (res != -1) {
919 /* These flags affect shader compilation. */
920 uint64_t shader_debug_flags =
921 rscreen->debug_flags &
922 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
923 DBG_SI_SCHED |
924 DBG_UNSAFE_MATH);
925
926 rscreen->disk_shader_cache =
927 disk_cache_create(r600_get_family_name(rscreen),
928 timestamp_str,
929 shader_debug_flags);
930 free(timestamp_str);
931 }
932 }
933 }
934
935 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
936 {
937 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
938 return rscreen->disk_shader_cache;
939 }
940
941 static const char* r600_get_name(struct pipe_screen* pscreen)
942 {
943 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
944
945 return rscreen->renderer_string;
946 }
947
948 static float r600_get_paramf(struct pipe_screen* pscreen,
949 enum pipe_capf param)
950 {
951 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
952
953 switch (param) {
954 case PIPE_CAPF_MAX_LINE_WIDTH:
955 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
956 case PIPE_CAPF_MAX_POINT_WIDTH:
957 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
958 if (rscreen->family >= CHIP_CEDAR)
959 return 16384.0f;
960 else
961 return 8192.0f;
962 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
963 return 16.0f;
964 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
965 return 16.0f;
966 case PIPE_CAPF_GUARD_BAND_LEFT:
967 case PIPE_CAPF_GUARD_BAND_TOP:
968 case PIPE_CAPF_GUARD_BAND_RIGHT:
969 case PIPE_CAPF_GUARD_BAND_BOTTOM:
970 return 0.0f;
971 }
972 return 0.0f;
973 }
974
975 static int r600_get_video_param(struct pipe_screen *screen,
976 enum pipe_video_profile profile,
977 enum pipe_video_entrypoint entrypoint,
978 enum pipe_video_cap param)
979 {
980 switch (param) {
981 case PIPE_VIDEO_CAP_SUPPORTED:
982 return vl_profile_supported(screen, profile, entrypoint);
983 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
984 return 1;
985 case PIPE_VIDEO_CAP_MAX_WIDTH:
986 case PIPE_VIDEO_CAP_MAX_HEIGHT:
987 return vl_video_buffer_max_size(screen);
988 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
989 return PIPE_FORMAT_NV12;
990 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
991 return false;
992 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
993 return false;
994 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
995 return true;
996 case PIPE_VIDEO_CAP_MAX_LEVEL:
997 return vl_level_supported(screen, profile);
998 default:
999 return 0;
1000 }
1001 }
1002
1003 const char *r600_get_llvm_processor_name(enum radeon_family family)
1004 {
1005 switch (family) {
1006 case CHIP_R600:
1007 case CHIP_RV630:
1008 case CHIP_RV635:
1009 case CHIP_RV670:
1010 return "r600";
1011 case CHIP_RV610:
1012 case CHIP_RV620:
1013 case CHIP_RS780:
1014 case CHIP_RS880:
1015 return "rs880";
1016 case CHIP_RV710:
1017 return "rv710";
1018 case CHIP_RV730:
1019 return "rv730";
1020 case CHIP_RV740:
1021 case CHIP_RV770:
1022 return "rv770";
1023 case CHIP_PALM:
1024 case CHIP_CEDAR:
1025 return "cedar";
1026 case CHIP_SUMO:
1027 case CHIP_SUMO2:
1028 return "sumo";
1029 case CHIP_REDWOOD:
1030 return "redwood";
1031 case CHIP_JUNIPER:
1032 return "juniper";
1033 case CHIP_HEMLOCK:
1034 case CHIP_CYPRESS:
1035 return "cypress";
1036 case CHIP_BARTS:
1037 return "barts";
1038 case CHIP_TURKS:
1039 return "turks";
1040 case CHIP_CAICOS:
1041 return "caicos";
1042 case CHIP_CAYMAN:
1043 case CHIP_ARUBA:
1044 return "cayman";
1045
1046 case CHIP_TAHITI: return "tahiti";
1047 case CHIP_PITCAIRN: return "pitcairn";
1048 case CHIP_VERDE: return "verde";
1049 case CHIP_OLAND: return "oland";
1050 case CHIP_HAINAN: return "hainan";
1051 case CHIP_BONAIRE: return "bonaire";
1052 case CHIP_KABINI: return "kabini";
1053 case CHIP_KAVERI: return "kaveri";
1054 case CHIP_HAWAII: return "hawaii";
1055 case CHIP_MULLINS:
1056 return "mullins";
1057 case CHIP_TONGA: return "tonga";
1058 case CHIP_ICELAND: return "iceland";
1059 case CHIP_CARRIZO: return "carrizo";
1060 case CHIP_FIJI:
1061 return "fiji";
1062 case CHIP_STONEY:
1063 return "stoney";
1064 case CHIP_POLARIS10:
1065 return "polaris10";
1066 case CHIP_POLARIS11:
1067 case CHIP_POLARIS12: /* same as polaris11 */
1068 return "polaris11";
1069 case CHIP_VEGA10:
1070 case CHIP_RAVEN:
1071 return "gfx900";
1072 default:
1073 return "";
1074 }
1075 }
1076
1077 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1078 enum pipe_shader_ir ir_type)
1079 {
1080 if (ir_type != PIPE_SHADER_IR_TGSI)
1081 return 256;
1082
1083 /* Only 16 waves per thread-group on gfx9. */
1084 if (screen->chip_class >= GFX9)
1085 return 1024;
1086
1087 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1088 * round number.
1089 */
1090 if (screen->chip_class >= SI)
1091 return 2048;
1092
1093 return 256;
1094 }
1095
1096 static int r600_get_compute_param(struct pipe_screen *screen,
1097 enum pipe_shader_ir ir_type,
1098 enum pipe_compute_cap param,
1099 void *ret)
1100 {
1101 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1102
1103 //TODO: select these params by asic
1104 switch (param) {
1105 case PIPE_COMPUTE_CAP_IR_TARGET: {
1106 const char *gpu;
1107 const char *triple;
1108 if (rscreen->family <= CHIP_ARUBA) {
1109 triple = "r600--";
1110 } else {
1111 if (HAVE_LLVM < 0x0400) {
1112 triple = "amdgcn--";
1113 } else {
1114 triple = "amdgcn-mesa-mesa3d";
1115 }
1116 }
1117 switch(rscreen->family) {
1118 /* Clang < 3.6 is missing Hainan in its list of
1119 * GPUs, so we need to use the name of a similar GPU.
1120 */
1121 default:
1122 gpu = r600_get_llvm_processor_name(rscreen->family);
1123 break;
1124 }
1125 if (ret) {
1126 sprintf(ret, "%s-%s", gpu, triple);
1127 }
1128 /* +2 for dash and terminating NIL byte */
1129 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1130 }
1131 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1132 if (ret) {
1133 uint64_t *grid_dimension = ret;
1134 grid_dimension[0] = 3;
1135 }
1136 return 1 * sizeof(uint64_t);
1137
1138 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1139 if (ret) {
1140 uint64_t *grid_size = ret;
1141 grid_size[0] = 65535;
1142 grid_size[1] = 65535;
1143 grid_size[2] = 65535;
1144 }
1145 return 3 * sizeof(uint64_t) ;
1146
1147 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1148 if (ret) {
1149 uint64_t *block_size = ret;
1150 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1151 block_size[0] = threads_per_block;
1152 block_size[1] = threads_per_block;
1153 block_size[2] = threads_per_block;
1154 }
1155 return 3 * sizeof(uint64_t);
1156
1157 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1158 if (ret) {
1159 uint64_t *max_threads_per_block = ret;
1160 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1161 }
1162 return sizeof(uint64_t);
1163 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1164 if (ret) {
1165 uint32_t *address_bits = ret;
1166 address_bits[0] = 32;
1167 if (rscreen->chip_class >= SI)
1168 address_bits[0] = 64;
1169 }
1170 return 1 * sizeof(uint32_t);
1171
1172 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1173 if (ret) {
1174 uint64_t *max_global_size = ret;
1175 uint64_t max_mem_alloc_size;
1176
1177 r600_get_compute_param(screen, ir_type,
1178 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1179 &max_mem_alloc_size);
1180
1181 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1182 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1183 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1184 * make sure we never report more than
1185 * 4 * MAX_MEM_ALLOC_SIZE.
1186 */
1187 *max_global_size = MIN2(4 * max_mem_alloc_size,
1188 MAX2(rscreen->info.gart_size,
1189 rscreen->info.vram_size));
1190 }
1191 return sizeof(uint64_t);
1192
1193 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1194 if (ret) {
1195 uint64_t *max_local_size = ret;
1196 /* Value reported by the closed source driver. */
1197 *max_local_size = 32768;
1198 }
1199 return sizeof(uint64_t);
1200
1201 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1202 if (ret) {
1203 uint64_t *max_input_size = ret;
1204 /* Value reported by the closed source driver. */
1205 *max_input_size = 1024;
1206 }
1207 return sizeof(uint64_t);
1208
1209 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1210 if (ret) {
1211 uint64_t *max_mem_alloc_size = ret;
1212
1213 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1214 }
1215 return sizeof(uint64_t);
1216
1217 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1218 if (ret) {
1219 uint32_t *max_clock_frequency = ret;
1220 *max_clock_frequency = rscreen->info.max_shader_clock;
1221 }
1222 return sizeof(uint32_t);
1223
1224 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1225 if (ret) {
1226 uint32_t *max_compute_units = ret;
1227 *max_compute_units = rscreen->info.num_good_compute_units;
1228 }
1229 return sizeof(uint32_t);
1230
1231 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1232 if (ret) {
1233 uint32_t *images_supported = ret;
1234 *images_supported = 0;
1235 }
1236 return sizeof(uint32_t);
1237 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1238 break; /* unused */
1239 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1240 if (ret) {
1241 uint32_t *subgroup_size = ret;
1242 *subgroup_size = r600_wavefront_size(rscreen->family);
1243 }
1244 return sizeof(uint32_t);
1245 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1246 if (ret) {
1247 uint64_t *max_variable_threads_per_block = ret;
1248 if (rscreen->chip_class >= SI &&
1249 ir_type == PIPE_SHADER_IR_TGSI)
1250 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1251 else
1252 *max_variable_threads_per_block = 0;
1253 }
1254 return sizeof(uint64_t);
1255 }
1256
1257 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1258 return 0;
1259 }
1260
1261 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1262 {
1263 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1264
1265 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1266 rscreen->info.clock_crystal_freq;
1267 }
1268
1269 static void r600_fence_reference(struct pipe_screen *screen,
1270 struct pipe_fence_handle **dst,
1271 struct pipe_fence_handle *src)
1272 {
1273 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1274 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1275 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1276
1277 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1278 ws->fence_reference(&(*rdst)->gfx, NULL);
1279 ws->fence_reference(&(*rdst)->sdma, NULL);
1280 FREE(*rdst);
1281 }
1282 *rdst = rsrc;
1283 }
1284
1285 static boolean r600_fence_finish(struct pipe_screen *screen,
1286 struct pipe_context *ctx,
1287 struct pipe_fence_handle *fence,
1288 uint64_t timeout)
1289 {
1290 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1291 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1292 struct r600_common_context *rctx;
1293 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1294
1295 ctx = threaded_context_unwrap_sync(ctx);
1296 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1297
1298 if (rfence->sdma) {
1299 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1300 return false;
1301
1302 /* Recompute the timeout after waiting. */
1303 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1304 int64_t time = os_time_get_nano();
1305 timeout = abs_timeout > time ? abs_timeout - time : 0;
1306 }
1307 }
1308
1309 if (!rfence->gfx)
1310 return true;
1311
1312 /* Flush the gfx IB if it hasn't been flushed yet. */
1313 if (rctx &&
1314 rfence->gfx_unflushed.ctx == rctx &&
1315 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1316 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1317 rfence->gfx_unflushed.ctx = NULL;
1318
1319 if (!timeout)
1320 return false;
1321
1322 /* Recompute the timeout after all that. */
1323 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1324 int64_t time = os_time_get_nano();
1325 timeout = abs_timeout > time ? abs_timeout - time : 0;
1326 }
1327 }
1328
1329 return rws->fence_wait(rws, rfence->gfx, timeout);
1330 }
1331
1332 static void r600_query_memory_info(struct pipe_screen *screen,
1333 struct pipe_memory_info *info)
1334 {
1335 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1336 struct radeon_winsys *ws = rscreen->ws;
1337 unsigned vram_usage, gtt_usage;
1338
1339 info->total_device_memory = rscreen->info.vram_size / 1024;
1340 info->total_staging_memory = rscreen->info.gart_size / 1024;
1341
1342 /* The real TTM memory usage is somewhat random, because:
1343 *
1344 * 1) TTM delays freeing memory, because it can only free it after
1345 * fences expire.
1346 *
1347 * 2) The memory usage can be really low if big VRAM evictions are
1348 * taking place, but the real usage is well above the size of VRAM.
1349 *
1350 * Instead, return statistics of this process.
1351 */
1352 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1353 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1354
1355 info->avail_device_memory =
1356 vram_usage <= info->total_device_memory ?
1357 info->total_device_memory - vram_usage : 0;
1358 info->avail_staging_memory =
1359 gtt_usage <= info->total_staging_memory ?
1360 info->total_staging_memory - gtt_usage : 0;
1361
1362 info->device_memory_evicted =
1363 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1364
1365 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1366 info->nr_device_memory_evictions =
1367 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1368 else
1369 /* Just return the number of evicted 64KB pages. */
1370 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1371 }
1372
1373 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1374 const struct pipe_resource *templ)
1375 {
1376 if (templ->target == PIPE_BUFFER) {
1377 return r600_buffer_create(screen, templ, 256);
1378 } else {
1379 return r600_texture_create(screen, templ);
1380 }
1381 }
1382
1383 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1384 struct radeon_winsys *ws)
1385 {
1386 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1387 struct utsname uname_data;
1388 const char *chip_name;
1389
1390 ws->query_info(ws, &rscreen->info);
1391 rscreen->ws = ws;
1392
1393 if ((chip_name = r600_get_marketing_name(ws)))
1394 snprintf(family_name, sizeof(family_name), "%s / ",
1395 r600_get_family_name(rscreen) + 4);
1396 else
1397 chip_name = r600_get_family_name(rscreen);
1398
1399 if (uname(&uname_data) == 0)
1400 snprintf(kernel_version, sizeof(kernel_version),
1401 " / %s", uname_data.release);
1402
1403 if (HAVE_LLVM > 0) {
1404 snprintf(llvm_string, sizeof(llvm_string),
1405 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1406 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1407 }
1408
1409 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1410 "%s (%sDRM %i.%i.%i%s%s)",
1411 chip_name, family_name, rscreen->info.drm_major,
1412 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1413 kernel_version, llvm_string);
1414
1415 rscreen->b.get_name = r600_get_name;
1416 rscreen->b.get_vendor = r600_get_vendor;
1417 rscreen->b.get_device_vendor = r600_get_device_vendor;
1418 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1419 rscreen->b.get_compute_param = r600_get_compute_param;
1420 rscreen->b.get_paramf = r600_get_paramf;
1421 rscreen->b.get_timestamp = r600_get_timestamp;
1422 rscreen->b.fence_finish = r600_fence_finish;
1423 rscreen->b.fence_reference = r600_fence_reference;
1424 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1425 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1426 rscreen->b.query_memory_info = r600_query_memory_info;
1427
1428 if (rscreen->info.has_hw_decode) {
1429 rscreen->b.get_video_param = rvid_get_video_param;
1430 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1431 } else {
1432 rscreen->b.get_video_param = r600_get_video_param;
1433 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1434 }
1435
1436 r600_init_screen_texture_functions(rscreen);
1437 r600_init_screen_query_functions(rscreen);
1438
1439 rscreen->family = rscreen->info.family;
1440 rscreen->chip_class = rscreen->info.chip_class;
1441 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1442 rscreen->has_rbplus = false;
1443 rscreen->rbplus_allowed = false;
1444
1445 r600_disk_cache_create(rscreen);
1446
1447 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1448
1449 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1450 if (rscreen->force_aniso >= 0) {
1451 printf("radeon: Forcing anisotropy filter to %ix\n",
1452 /* round down to a power of two */
1453 1 << util_logbase2(rscreen->force_aniso));
1454 }
1455
1456 util_format_s3tc_init();
1457 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1458 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1459
1460 if (rscreen->debug_flags & DBG_INFO) {
1461 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1462 rscreen->info.pci_domain, rscreen->info.pci_bus,
1463 rscreen->info.pci_dev, rscreen->info.pci_func);
1464 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1465 printf("family = %i (%s)\n", rscreen->info.family,
1466 r600_get_family_name(rscreen));
1467 printf("chip_class = %i\n", rscreen->info.chip_class);
1468 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1469 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1470 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1471 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1472 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1473 printf("max_alloc_size = %i MB\n",
1474 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1475 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1476 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1477 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1478 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1479 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1480 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1481 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1482 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1483 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1484 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1485 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1486 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1487 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1488 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1489 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1490 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1491 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1492 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1493 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1494
1495 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1496 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1497 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1498 printf("max_se = %i\n", rscreen->info.max_se);
1499 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1500
1501 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1502 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1503 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1504 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1505 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1506 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1507 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1508 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1509 }
1510 return true;
1511 }
1512
1513 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1514 {
1515 r600_perfcounters_destroy(rscreen);
1516 r600_gpu_load_kill_thread(rscreen);
1517
1518 mtx_destroy(&rscreen->gpu_load_mutex);
1519 mtx_destroy(&rscreen->aux_context_lock);
1520 rscreen->aux_context->destroy(rscreen->aux_context);
1521
1522 slab_destroy_parent(&rscreen->pool_transfers);
1523
1524 disk_cache_destroy(rscreen->disk_shader_cache);
1525 rscreen->ws->destroy(rscreen->ws);
1526 FREE(rscreen);
1527 }
1528
1529 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1530 unsigned processor)
1531 {
1532 switch (processor) {
1533 case PIPE_SHADER_VERTEX:
1534 return (rscreen->debug_flags & DBG_VS) != 0;
1535 case PIPE_SHADER_TESS_CTRL:
1536 return (rscreen->debug_flags & DBG_TCS) != 0;
1537 case PIPE_SHADER_TESS_EVAL:
1538 return (rscreen->debug_flags & DBG_TES) != 0;
1539 case PIPE_SHADER_GEOMETRY:
1540 return (rscreen->debug_flags & DBG_GS) != 0;
1541 case PIPE_SHADER_FRAGMENT:
1542 return (rscreen->debug_flags & DBG_PS) != 0;
1543 case PIPE_SHADER_COMPUTE:
1544 return (rscreen->debug_flags & DBG_CS) != 0;
1545 default:
1546 return false;
1547 }
1548 }
1549
1550 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1551 {
1552 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1553 r600_can_dump_shader(rscreen, processor);
1554 }
1555
1556 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1557 uint64_t offset, uint64_t size, unsigned value)
1558 {
1559 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1560
1561 mtx_lock(&rscreen->aux_context_lock);
1562 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1563 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1564 mtx_unlock(&rscreen->aux_context_lock);
1565 }