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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "os/os_time.h"
35 #include "vl/vl_decoder.h"
36 #include "vl/vl_video_buffer.h"
37 #include "radeon/radeon_video.h"
38 #include <inttypes.h>
39
40 #ifndef HAVE_LLVM
41 #define HAVE_LLVM 0
42 #endif
43
44 struct r600_multi_fence {
45 struct pipe_reference reference;
46 struct pipe_fence_handle *gfx;
47 struct pipe_fence_handle *sdma;
48 };
49
50 /*
51 * pipe_context
52 */
53
54 void r600_draw_rectangle(struct blitter_context *blitter,
55 int x1, int y1, int x2, int y2, float depth,
56 enum blitter_attrib_type type,
57 const union pipe_color_union *attrib)
58 {
59 struct r600_common_context *rctx =
60 (struct r600_common_context*)util_blitter_get_pipe(blitter);
61 struct pipe_viewport_state viewport;
62 struct pipe_resource *buf = NULL;
63 unsigned offset = 0;
64 float *vb;
65
66 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
67 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
68 return;
69 }
70
71 /* Some operations (like color resolve on r6xx) don't work
72 * with the conventional primitive types.
73 * One that works is PT_RECTLIST, which we use here. */
74
75 /* setup viewport */
76 viewport.scale[0] = 1.0f;
77 viewport.scale[1] = 1.0f;
78 viewport.scale[2] = 1.0f;
79 viewport.translate[0] = 0.0f;
80 viewport.translate[1] = 0.0f;
81 viewport.translate[2] = 0.0f;
82 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
83
84 /* Upload vertices. The hw rectangle has only 3 vertices,
85 * I guess the 4th one is derived from the first 3.
86 * The vertex specification should match u_blitter's vertex element state. */
87 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
88 if (!buf)
89 return;
90
91 vb[0] = x1;
92 vb[1] = y1;
93 vb[2] = depth;
94 vb[3] = 1;
95
96 vb[8] = x1;
97 vb[9] = y2;
98 vb[10] = depth;
99 vb[11] = 1;
100
101 vb[16] = x2;
102 vb[17] = y1;
103 vb[18] = depth;
104 vb[19] = 1;
105
106 if (attrib) {
107 memcpy(vb+4, attrib->f, sizeof(float)*4);
108 memcpy(vb+12, attrib->f, sizeof(float)*4);
109 memcpy(vb+20, attrib->f, sizeof(float)*4);
110 }
111
112 /* draw */
113 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
114 R600_PRIM_RECTANGLE_LIST, 3, 2);
115 pipe_resource_reference(&buf, NULL);
116 }
117
118 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
119 {
120 /* Flush the GFX IB if it's not empty. */
121 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
122 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
123
124 /* Flush if there's not enough space. */
125 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
126 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
127 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
128 }
129 }
130
131 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
132 {
133 }
134
135 void r600_preflush_suspend_features(struct r600_common_context *ctx)
136 {
137 /* suspend queries */
138 ctx->queries_suspended_for_flush = false;
139 if (ctx->num_cs_dw_nontimer_queries_suspend) {
140 r600_suspend_nontimer_queries(ctx);
141 r600_suspend_timer_queries(ctx);
142 ctx->queries_suspended_for_flush = true;
143 }
144
145 ctx->streamout.suspended = false;
146 if (ctx->streamout.begin_emitted) {
147 r600_emit_streamout_end(ctx);
148 ctx->streamout.suspended = true;
149 }
150 }
151
152 void r600_postflush_resume_features(struct r600_common_context *ctx)
153 {
154 if (ctx->streamout.suspended) {
155 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
156 r600_streamout_buffers_dirty(ctx);
157 }
158
159 /* resume queries */
160 if (ctx->queries_suspended_for_flush) {
161 r600_resume_nontimer_queries(ctx);
162 r600_resume_timer_queries(ctx);
163 }
164 }
165
166 static void r600_flush_from_st(struct pipe_context *ctx,
167 struct pipe_fence_handle **fence,
168 unsigned flags)
169 {
170 struct pipe_screen *screen = ctx->screen;
171 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
172 unsigned rflags = 0;
173 struct pipe_fence_handle *gfx_fence = NULL;
174 struct pipe_fence_handle *sdma_fence = NULL;
175
176 if (flags & PIPE_FLUSH_END_OF_FRAME)
177 rflags |= RADEON_FLUSH_END_OF_FRAME;
178
179 if (rctx->dma.cs) {
180 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
181 }
182 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
183
184 /* Both engines can signal out of order, so we need to keep both fences. */
185 if (gfx_fence || sdma_fence) {
186 struct r600_multi_fence *multi_fence =
187 CALLOC_STRUCT(r600_multi_fence);
188 if (!multi_fence)
189 return;
190
191 multi_fence->reference.count = 1;
192 multi_fence->gfx = gfx_fence;
193 multi_fence->sdma = sdma_fence;
194
195 screen->fence_reference(screen, fence, NULL);
196 *fence = (struct pipe_fence_handle*)multi_fence;
197 }
198 }
199
200 static void r600_flush_dma_ring(void *ctx, unsigned flags,
201 struct pipe_fence_handle **fence)
202 {
203 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
204 struct radeon_winsys_cs *cs = rctx->dma.cs;
205
206 if (cs->cdw)
207 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
208 if (fence)
209 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
210 }
211
212 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
213 {
214 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
215 unsigned latest = rctx->ws->query_value(rctx->ws,
216 RADEON_GPU_RESET_COUNTER);
217
218 if (rctx->gpu_reset_counter == latest)
219 return PIPE_NO_RESET;
220
221 rctx->gpu_reset_counter = latest;
222 return PIPE_UNKNOWN_CONTEXT_RESET;
223 }
224
225 bool r600_common_context_init(struct r600_common_context *rctx,
226 struct r600_common_screen *rscreen)
227 {
228 util_slab_create(&rctx->pool_transfers,
229 sizeof(struct r600_transfer), 64,
230 UTIL_SLAB_SINGLETHREADED);
231
232 rctx->screen = rscreen;
233 rctx->ws = rscreen->ws;
234 rctx->family = rscreen->family;
235 rctx->chip_class = rscreen->chip_class;
236
237 if (rscreen->family == CHIP_HAWAII)
238 rctx->max_db = 16;
239 else if (rscreen->chip_class >= EVERGREEN)
240 rctx->max_db = 8;
241 else
242 rctx->max_db = 4;
243
244 rctx->b.transfer_map = u_transfer_map_vtbl;
245 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
246 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
247 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
248 rctx->b.memory_barrier = r600_memory_barrier;
249 rctx->b.flush = r600_flush_from_st;
250
251 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
252 rctx->b.get_device_reset_status = r600_get_reset_status;
253 rctx->gpu_reset_counter =
254 rctx->ws->query_value(rctx->ws,
255 RADEON_GPU_RESET_COUNTER);
256 }
257
258 LIST_INITHEAD(&rctx->texture_buffers);
259
260 r600_init_context_texture_functions(rctx);
261 r600_streamout_init(rctx);
262 r600_query_init(rctx);
263 cayman_init_msaa(&rctx->b);
264
265 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
266 0, PIPE_USAGE_DEFAULT, TRUE);
267 if (!rctx->allocator_so_filled_size)
268 return false;
269
270 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
271 PIPE_BIND_INDEX_BUFFER |
272 PIPE_BIND_CONSTANT_BUFFER);
273 if (!rctx->uploader)
274 return false;
275
276 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
277 if (!rctx->ctx)
278 return false;
279
280 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
281 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
282 r600_flush_dma_ring,
283 rctx, NULL);
284 rctx->dma.flush = r600_flush_dma_ring;
285 }
286
287 return true;
288 }
289
290 void r600_common_context_cleanup(struct r600_common_context *rctx)
291 {
292 if (rctx->gfx.cs)
293 rctx->ws->cs_destroy(rctx->gfx.cs);
294 if (rctx->dma.cs)
295 rctx->ws->cs_destroy(rctx->dma.cs);
296 if (rctx->ctx)
297 rctx->ws->ctx_destroy(rctx->ctx);
298
299 if (rctx->uploader) {
300 u_upload_destroy(rctx->uploader);
301 }
302
303 util_slab_destroy(&rctx->pool_transfers);
304
305 if (rctx->allocator_so_filled_size) {
306 u_suballocator_destroy(rctx->allocator_so_filled_size);
307 }
308 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
309 }
310
311 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
312 {
313 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
314 struct r600_resource *rr = (struct r600_resource *)r;
315
316 if (r == NULL) {
317 return;
318 }
319
320 /*
321 * The idea is to compute a gross estimate of memory requirement of
322 * each draw call. After each draw call, memory will be precisely
323 * accounted. So the uncertainty is only on the current draw call.
324 * In practice this gave very good estimate (+/- 10% of the target
325 * memory limit).
326 */
327 if (rr->domains & RADEON_DOMAIN_GTT) {
328 rctx->gtt += rr->buf->size;
329 }
330 if (rr->domains & RADEON_DOMAIN_VRAM) {
331 rctx->vram += rr->buf->size;
332 }
333 }
334
335 /*
336 * pipe_screen
337 */
338
339 static const struct debug_named_value common_debug_options[] = {
340 /* logging */
341 { "tex", DBG_TEX, "Print texture info" },
342 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
343 { "compute", DBG_COMPUTE, "Print compute info" },
344 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
345 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
346 { "info", DBG_INFO, "Print driver information" },
347
348 /* shaders */
349 { "fs", DBG_FS, "Print fetch shaders" },
350 { "vs", DBG_VS, "Print vertex shaders" },
351 { "gs", DBG_GS, "Print geometry shaders" },
352 { "ps", DBG_PS, "Print pixel shaders" },
353 { "cs", DBG_CS, "Print compute shaders" },
354 { "tcs", DBG_TCS, "Print tessellation control shaders" },
355 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
356 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
357 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
358 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
359
360 /* features */
361 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
362 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
363 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
364 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
365 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
366 { "notiling", DBG_NO_TILING, "Disable tiling" },
367 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
368 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
369 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
370 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
371 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
372 { "nodcc", DBG_NO_DCC, "Disable DCC." },
373 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
374
375 DEBUG_NAMED_VALUE_END /* must be last */
376 };
377
378 static const char* r600_get_vendor(struct pipe_screen* pscreen)
379 {
380 return "X.Org";
381 }
382
383 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
384 {
385 return "AMD";
386 }
387
388 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
389 {
390 switch (rscreen->info.family) {
391 case CHIP_R600: return "AMD R600";
392 case CHIP_RV610: return "AMD RV610";
393 case CHIP_RV630: return "AMD RV630";
394 case CHIP_RV670: return "AMD RV670";
395 case CHIP_RV620: return "AMD RV620";
396 case CHIP_RV635: return "AMD RV635";
397 case CHIP_RS780: return "AMD RS780";
398 case CHIP_RS880: return "AMD RS880";
399 case CHIP_RV770: return "AMD RV770";
400 case CHIP_RV730: return "AMD RV730";
401 case CHIP_RV710: return "AMD RV710";
402 case CHIP_RV740: return "AMD RV740";
403 case CHIP_CEDAR: return "AMD CEDAR";
404 case CHIP_REDWOOD: return "AMD REDWOOD";
405 case CHIP_JUNIPER: return "AMD JUNIPER";
406 case CHIP_CYPRESS: return "AMD CYPRESS";
407 case CHIP_HEMLOCK: return "AMD HEMLOCK";
408 case CHIP_PALM: return "AMD PALM";
409 case CHIP_SUMO: return "AMD SUMO";
410 case CHIP_SUMO2: return "AMD SUMO2";
411 case CHIP_BARTS: return "AMD BARTS";
412 case CHIP_TURKS: return "AMD TURKS";
413 case CHIP_CAICOS: return "AMD CAICOS";
414 case CHIP_CAYMAN: return "AMD CAYMAN";
415 case CHIP_ARUBA: return "AMD ARUBA";
416 case CHIP_TAHITI: return "AMD TAHITI";
417 case CHIP_PITCAIRN: return "AMD PITCAIRN";
418 case CHIP_VERDE: return "AMD CAPE VERDE";
419 case CHIP_OLAND: return "AMD OLAND";
420 case CHIP_HAINAN: return "AMD HAINAN";
421 case CHIP_BONAIRE: return "AMD BONAIRE";
422 case CHIP_KAVERI: return "AMD KAVERI";
423 case CHIP_KABINI: return "AMD KABINI";
424 case CHIP_HAWAII: return "AMD HAWAII";
425 case CHIP_MULLINS: return "AMD MULLINS";
426 case CHIP_TONGA: return "AMD TONGA";
427 case CHIP_ICELAND: return "AMD ICELAND";
428 case CHIP_CARRIZO: return "AMD CARRIZO";
429 case CHIP_FIJI: return "AMD FIJI";
430 case CHIP_STONEY: return "AMD STONEY";
431 default: return "AMD unknown";
432 }
433 }
434
435 static const char* r600_get_name(struct pipe_screen* pscreen)
436 {
437 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
438
439 return rscreen->renderer_string;
440 }
441
442 static float r600_get_paramf(struct pipe_screen* pscreen,
443 enum pipe_capf param)
444 {
445 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
446
447 switch (param) {
448 case PIPE_CAPF_MAX_LINE_WIDTH:
449 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
450 case PIPE_CAPF_MAX_POINT_WIDTH:
451 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
452 if (rscreen->family >= CHIP_CEDAR)
453 return 16384.0f;
454 else
455 return 8192.0f;
456 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
457 return 16.0f;
458 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
459 return 16.0f;
460 case PIPE_CAPF_GUARD_BAND_LEFT:
461 case PIPE_CAPF_GUARD_BAND_TOP:
462 case PIPE_CAPF_GUARD_BAND_RIGHT:
463 case PIPE_CAPF_GUARD_BAND_BOTTOM:
464 return 0.0f;
465 }
466 return 0.0f;
467 }
468
469 static int r600_get_video_param(struct pipe_screen *screen,
470 enum pipe_video_profile profile,
471 enum pipe_video_entrypoint entrypoint,
472 enum pipe_video_cap param)
473 {
474 switch (param) {
475 case PIPE_VIDEO_CAP_SUPPORTED:
476 return vl_profile_supported(screen, profile, entrypoint);
477 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
478 return 1;
479 case PIPE_VIDEO_CAP_MAX_WIDTH:
480 case PIPE_VIDEO_CAP_MAX_HEIGHT:
481 return vl_video_buffer_max_size(screen);
482 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
483 return PIPE_FORMAT_NV12;
484 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
485 return false;
486 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
487 return false;
488 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
489 return true;
490 case PIPE_VIDEO_CAP_MAX_LEVEL:
491 return vl_level_supported(screen, profile);
492 default:
493 return 0;
494 }
495 }
496
497 const char *r600_get_llvm_processor_name(enum radeon_family family)
498 {
499 switch (family) {
500 case CHIP_R600:
501 case CHIP_RV630:
502 case CHIP_RV635:
503 case CHIP_RV670:
504 return "r600";
505 case CHIP_RV610:
506 case CHIP_RV620:
507 case CHIP_RS780:
508 case CHIP_RS880:
509 return "rs880";
510 case CHIP_RV710:
511 return "rv710";
512 case CHIP_RV730:
513 return "rv730";
514 case CHIP_RV740:
515 case CHIP_RV770:
516 return "rv770";
517 case CHIP_PALM:
518 case CHIP_CEDAR:
519 return "cedar";
520 case CHIP_SUMO:
521 case CHIP_SUMO2:
522 return "sumo";
523 case CHIP_REDWOOD:
524 return "redwood";
525 case CHIP_JUNIPER:
526 return "juniper";
527 case CHIP_HEMLOCK:
528 case CHIP_CYPRESS:
529 return "cypress";
530 case CHIP_BARTS:
531 return "barts";
532 case CHIP_TURKS:
533 return "turks";
534 case CHIP_CAICOS:
535 return "caicos";
536 case CHIP_CAYMAN:
537 case CHIP_ARUBA:
538 return "cayman";
539
540 case CHIP_TAHITI: return "tahiti";
541 case CHIP_PITCAIRN: return "pitcairn";
542 case CHIP_VERDE: return "verde";
543 case CHIP_OLAND: return "oland";
544 case CHIP_HAINAN: return "hainan";
545 case CHIP_BONAIRE: return "bonaire";
546 case CHIP_KABINI: return "kabini";
547 case CHIP_KAVERI: return "kaveri";
548 case CHIP_HAWAII: return "hawaii";
549 case CHIP_MULLINS:
550 return "mullins";
551 case CHIP_TONGA: return "tonga";
552 case CHIP_ICELAND: return "iceland";
553 case CHIP_CARRIZO: return "carrizo";
554 case CHIP_FIJI: return "fiji";
555 #if HAVE_LLVM <= 0x0307
556 case CHIP_STONEY: return "carrizo";
557 #else
558 case CHIP_STONEY: return "stoney";
559 #endif
560 default: return "";
561 }
562 }
563
564 static int r600_get_compute_param(struct pipe_screen *screen,
565 enum pipe_compute_cap param,
566 void *ret)
567 {
568 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
569
570 //TODO: select these params by asic
571 switch (param) {
572 case PIPE_COMPUTE_CAP_IR_TARGET: {
573 const char *gpu;
574 const char *triple;
575 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
576 triple = "r600--";
577 } else {
578 triple = "amdgcn--";
579 }
580 switch(rscreen->family) {
581 /* Clang < 3.6 is missing Hainan in its list of
582 * GPUs, so we need to use the name of a similar GPU.
583 */
584 #if HAVE_LLVM < 0x0306
585 case CHIP_HAINAN:
586 gpu = "oland";
587 break;
588 #endif
589 default:
590 gpu = r600_get_llvm_processor_name(rscreen->family);
591 break;
592 }
593 if (ret) {
594 sprintf(ret, "%s-%s", gpu, triple);
595 }
596 /* +2 for dash and terminating NIL byte */
597 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
598 }
599 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
600 if (ret) {
601 uint64_t *grid_dimension = ret;
602 grid_dimension[0] = 3;
603 }
604 return 1 * sizeof(uint64_t);
605
606 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
607 if (ret) {
608 uint64_t *grid_size = ret;
609 grid_size[0] = 65535;
610 grid_size[1] = 65535;
611 grid_size[2] = 1;
612 }
613 return 3 * sizeof(uint64_t) ;
614
615 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
616 if (ret) {
617 uint64_t *block_size = ret;
618 block_size[0] = 256;
619 block_size[1] = 256;
620 block_size[2] = 256;
621 }
622 return 3 * sizeof(uint64_t);
623
624 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
625 if (ret) {
626 uint64_t *max_threads_per_block = ret;
627 *max_threads_per_block = 256;
628 }
629 return sizeof(uint64_t);
630
631 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
632 if (ret) {
633 uint64_t *max_global_size = ret;
634 uint64_t max_mem_alloc_size;
635
636 r600_get_compute_param(screen,
637 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
638 &max_mem_alloc_size);
639
640 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
641 * 1/4 of the MAX_GLOBAL_SIZE. Since the
642 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
643 * make sure we never report more than
644 * 4 * MAX_MEM_ALLOC_SIZE.
645 */
646 *max_global_size = MIN2(4 * max_mem_alloc_size,
647 rscreen->info.gart_size +
648 rscreen->info.vram_size);
649 }
650 return sizeof(uint64_t);
651
652 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
653 if (ret) {
654 uint64_t *max_local_size = ret;
655 /* Value reported by the closed source driver. */
656 *max_local_size = 32768;
657 }
658 return sizeof(uint64_t);
659
660 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
661 if (ret) {
662 uint64_t *max_input_size = ret;
663 /* Value reported by the closed source driver. */
664 *max_input_size = 1024;
665 }
666 return sizeof(uint64_t);
667
668 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
669 if (ret) {
670 uint64_t *max_mem_alloc_size = ret;
671
672 /* XXX: The limit in older kernels is 256 MB. We
673 * should add a query here for newer kernels.
674 */
675 *max_mem_alloc_size = 256 * 1024 * 1024;
676 }
677 return sizeof(uint64_t);
678
679 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
680 if (ret) {
681 uint32_t *max_clock_frequency = ret;
682 *max_clock_frequency = rscreen->info.max_sclk;
683 }
684 return sizeof(uint32_t);
685
686 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
687 if (ret) {
688 uint32_t *max_compute_units = ret;
689 *max_compute_units = rscreen->info.max_compute_units;
690 }
691 return sizeof(uint32_t);
692
693 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
694 if (ret) {
695 uint32_t *images_supported = ret;
696 *images_supported = 0;
697 }
698 return sizeof(uint32_t);
699 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
700 break; /* unused */
701 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
702 if (ret) {
703 uint32_t *subgroup_size = ret;
704 *subgroup_size = r600_wavefront_size(rscreen->family);
705 }
706 return sizeof(uint32_t);
707 }
708
709 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
710 return 0;
711 }
712
713 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
714 {
715 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
716
717 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
718 rscreen->info.r600_clock_crystal_freq;
719 }
720
721 static int r600_get_driver_query_info(struct pipe_screen *screen,
722 unsigned index,
723 struct pipe_driver_query_info *info)
724 {
725 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
726 struct pipe_driver_query_info list[] = {
727 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
728 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
729 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
730 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
731 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
732 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
733 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
734 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
735 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
736 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
737 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
738 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
739 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
740 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
741 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
742 {"temperature", R600_QUERY_GPU_TEMPERATURE, {125}},
743 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
744 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
745 };
746 unsigned num_queries;
747
748 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
749 num_queries = Elements(list);
750 else if (rscreen->info.drm_major == 3)
751 num_queries = Elements(list) - 3;
752 else
753 num_queries = Elements(list) - 4;
754
755 if (!info)
756 return num_queries;
757
758 if (index >= num_queries)
759 return 0;
760
761 *info = list[index];
762 return 1;
763 }
764
765 static void r600_fence_reference(struct pipe_screen *screen,
766 struct pipe_fence_handle **dst,
767 struct pipe_fence_handle *src)
768 {
769 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
770 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
771 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
772
773 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
774 ws->fence_reference(&(*rdst)->gfx, NULL);
775 ws->fence_reference(&(*rdst)->sdma, NULL);
776 FREE(*rdst);
777 }
778 *rdst = rsrc;
779 }
780
781 static boolean r600_fence_finish(struct pipe_screen *screen,
782 struct pipe_fence_handle *fence,
783 uint64_t timeout)
784 {
785 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
786 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
787 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
788
789 if (rfence->sdma) {
790 if (!rws->fence_wait(rws, rfence->sdma, timeout))
791 return false;
792
793 /* Recompute the timeout after waiting. */
794 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
795 int64_t time = os_time_get_nano();
796 timeout = abs_timeout > time ? abs_timeout - time : 0;
797 }
798 }
799
800 if (!rfence->gfx)
801 return true;
802
803 return rws->fence_wait(rws, rfence->gfx, timeout);
804 }
805
806 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
807 uint32_t tiling_config)
808 {
809 switch ((tiling_config & 0xe) >> 1) {
810 case 0:
811 rscreen->tiling_info.num_channels = 1;
812 break;
813 case 1:
814 rscreen->tiling_info.num_channels = 2;
815 break;
816 case 2:
817 rscreen->tiling_info.num_channels = 4;
818 break;
819 case 3:
820 rscreen->tiling_info.num_channels = 8;
821 break;
822 default:
823 return false;
824 }
825
826 switch ((tiling_config & 0x30) >> 4) {
827 case 0:
828 rscreen->tiling_info.num_banks = 4;
829 break;
830 case 1:
831 rscreen->tiling_info.num_banks = 8;
832 break;
833 default:
834 return false;
835
836 }
837 switch ((tiling_config & 0xc0) >> 6) {
838 case 0:
839 rscreen->tiling_info.group_bytes = 256;
840 break;
841 case 1:
842 rscreen->tiling_info.group_bytes = 512;
843 break;
844 default:
845 return false;
846 }
847 return true;
848 }
849
850 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
851 uint32_t tiling_config)
852 {
853 switch (tiling_config & 0xf) {
854 case 0:
855 rscreen->tiling_info.num_channels = 1;
856 break;
857 case 1:
858 rscreen->tiling_info.num_channels = 2;
859 break;
860 case 2:
861 rscreen->tiling_info.num_channels = 4;
862 break;
863 case 3:
864 rscreen->tiling_info.num_channels = 8;
865 break;
866 default:
867 return false;
868 }
869
870 switch ((tiling_config & 0xf0) >> 4) {
871 case 0:
872 rscreen->tiling_info.num_banks = 4;
873 break;
874 case 1:
875 rscreen->tiling_info.num_banks = 8;
876 break;
877 case 2:
878 rscreen->tiling_info.num_banks = 16;
879 break;
880 default:
881 return false;
882 }
883
884 switch ((tiling_config & 0xf00) >> 8) {
885 case 0:
886 rscreen->tiling_info.group_bytes = 256;
887 break;
888 case 1:
889 rscreen->tiling_info.group_bytes = 512;
890 break;
891 default:
892 return false;
893 }
894 return true;
895 }
896
897 static bool r600_init_tiling(struct r600_common_screen *rscreen)
898 {
899 uint32_t tiling_config = rscreen->info.r600_tiling_config;
900
901 /* set default group bytes, overridden by tiling info ioctl */
902 if (rscreen->chip_class <= R700) {
903 rscreen->tiling_info.group_bytes = 256;
904 } else {
905 rscreen->tiling_info.group_bytes = 512;
906 }
907
908 if (!tiling_config)
909 return true;
910
911 if (rscreen->chip_class <= R700) {
912 return r600_interpret_tiling(rscreen, tiling_config);
913 } else {
914 return evergreen_interpret_tiling(rscreen, tiling_config);
915 }
916 }
917
918 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
919 const struct pipe_resource *templ)
920 {
921 if (templ->target == PIPE_BUFFER) {
922 return r600_buffer_create(screen, templ, 4096);
923 } else {
924 return r600_texture_create(screen, templ);
925 }
926 }
927
928 bool r600_common_screen_init(struct r600_common_screen *rscreen,
929 struct radeon_winsys *ws)
930 {
931 char llvm_string[32] = {};
932
933 ws->query_info(ws, &rscreen->info);
934
935 #if HAVE_LLVM
936 snprintf(llvm_string, sizeof(llvm_string),
937 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
938 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
939 #endif
940
941 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
942 "%s (DRM %i.%i.%i%s)",
943 r600_get_chip_name(rscreen), rscreen->info.drm_major,
944 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
945 llvm_string);
946
947 rscreen->b.get_name = r600_get_name;
948 rscreen->b.get_vendor = r600_get_vendor;
949 rscreen->b.get_device_vendor = r600_get_device_vendor;
950 rscreen->b.get_compute_param = r600_get_compute_param;
951 rscreen->b.get_paramf = r600_get_paramf;
952 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
953 rscreen->b.get_timestamp = r600_get_timestamp;
954 rscreen->b.fence_finish = r600_fence_finish;
955 rscreen->b.fence_reference = r600_fence_reference;
956 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
957 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
958
959 if (rscreen->info.has_uvd) {
960 rscreen->b.get_video_param = rvid_get_video_param;
961 rscreen->b.is_video_format_supported = rvid_is_format_supported;
962 } else {
963 rscreen->b.get_video_param = r600_get_video_param;
964 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
965 }
966
967 r600_init_screen_texture_functions(rscreen);
968
969 rscreen->ws = ws;
970 rscreen->family = rscreen->info.family;
971 rscreen->chip_class = rscreen->info.chip_class;
972 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
973
974 if (!r600_init_tiling(rscreen)) {
975 return false;
976 }
977 util_format_s3tc_init();
978 pipe_mutex_init(rscreen->aux_context_lock);
979 pipe_mutex_init(rscreen->gpu_load_mutex);
980
981 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
982 rscreen->info.drm_major == 3) &&
983 (rscreen->debug_flags & DBG_TRACE_CS)) {
984 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
985 PIPE_BIND_CUSTOM,
986 PIPE_USAGE_STAGING,
987 4096);
988 if (rscreen->trace_bo) {
989 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
990 PIPE_TRANSFER_UNSYNCHRONIZED);
991 }
992 }
993
994 if (rscreen->debug_flags & DBG_INFO) {
995 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
996 printf("family = %i\n", rscreen->info.family);
997 printf("chip_class = %i\n", rscreen->info.chip_class);
998 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
999 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
1000 printf("max_sclk = %i\n", rscreen->info.max_sclk);
1001 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
1002 printf("max_se = %i\n", rscreen->info.max_se);
1003 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1004 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1005 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1006 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1007 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1008 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
1009 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
1010 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
1011 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
1012 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
1013 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
1014 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
1015 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
1016 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
1017 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
1018 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
1019 }
1020 return true;
1021 }
1022
1023 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1024 {
1025 r600_gpu_load_kill_thread(rscreen);
1026
1027 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1028 pipe_mutex_destroy(rscreen->aux_context_lock);
1029 rscreen->aux_context->destroy(rscreen->aux_context);
1030
1031 if (rscreen->trace_bo)
1032 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
1033
1034 rscreen->ws->destroy(rscreen->ws);
1035 FREE(rscreen);
1036 }
1037
1038 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1039 const struct tgsi_token *tokens)
1040 {
1041 /* Compute shader don't have tgsi_tokens */
1042 if (!tokens)
1043 return (rscreen->debug_flags & DBG_CS) != 0;
1044
1045 switch (tgsi_get_processor_type(tokens)) {
1046 case TGSI_PROCESSOR_VERTEX:
1047 return (rscreen->debug_flags & DBG_VS) != 0;
1048 case TGSI_PROCESSOR_TESS_CTRL:
1049 return (rscreen->debug_flags & DBG_TCS) != 0;
1050 case TGSI_PROCESSOR_TESS_EVAL:
1051 return (rscreen->debug_flags & DBG_TES) != 0;
1052 case TGSI_PROCESSOR_GEOMETRY:
1053 return (rscreen->debug_flags & DBG_GS) != 0;
1054 case TGSI_PROCESSOR_FRAGMENT:
1055 return (rscreen->debug_flags & DBG_PS) != 0;
1056 case TGSI_PROCESSOR_COMPUTE:
1057 return (rscreen->debug_flags & DBG_CS) != 0;
1058 default:
1059 return false;
1060 }
1061 }
1062
1063 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1064 unsigned offset, unsigned size, unsigned value,
1065 bool is_framebuffer)
1066 {
1067 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1068
1069 pipe_mutex_lock(rscreen->aux_context_lock);
1070 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1071 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1072 pipe_mutex_unlock(rscreen->aux_context_lock);
1073 }