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gallium/radeon: implement get_query_result_resource (v2)
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 void r600_gfx_write_fence(struct r600_common_context *ctx,
84 uint64_t va, uint32_t old_value, uint32_t new_value)
85 {
86 struct radeon_winsys_cs *cs = ctx->gfx.cs;
87
88 if (ctx->chip_class == CIK) {
89 /* Two EOP events are required to make all engines go idle
90 * (and optional cache flushes executed) before the timestamp
91 * is written.
92 */
93 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
94 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
95 EVENT_INDEX(5));
96 radeon_emit(cs, va);
97 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
98 radeon_emit(cs, old_value); /* immediate data */
99 radeon_emit(cs, 0); /* unused */
100 }
101
102 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
103 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
104 EVENT_INDEX(5));
105 radeon_emit(cs, va);
106 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
107 radeon_emit(cs, new_value); /* immediate data */
108 radeon_emit(cs, 0); /* unused */
109 }
110
111 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
112 {
113 unsigned dwords = 6;
114
115 if (screen->chip_class == CIK)
116 dwords *= 2;
117
118 return dwords;
119 }
120
121 void r600_gfx_wait_fence(struct r600_common_context *ctx,
122 uint64_t va, uint32_t ref, uint32_t mask)
123 {
124 struct radeon_winsys_cs *cs = ctx->gfx.cs;
125
126 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
127 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
128 radeon_emit(cs, va);
129 radeon_emit(cs, va >> 32);
130 radeon_emit(cs, ref); /* reference value */
131 radeon_emit(cs, mask); /* mask */
132 radeon_emit(cs, 4); /* poll interval */
133 }
134
135 void r600_draw_rectangle(struct blitter_context *blitter,
136 int x1, int y1, int x2, int y2, float depth,
137 enum blitter_attrib_type type,
138 const union pipe_color_union *attrib)
139 {
140 struct r600_common_context *rctx =
141 (struct r600_common_context*)util_blitter_get_pipe(blitter);
142 struct pipe_viewport_state viewport;
143 struct pipe_resource *buf = NULL;
144 unsigned offset = 0;
145 float *vb;
146
147 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
148 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
149 return;
150 }
151
152 /* Some operations (like color resolve on r6xx) don't work
153 * with the conventional primitive types.
154 * One that works is PT_RECTLIST, which we use here. */
155
156 /* setup viewport */
157 viewport.scale[0] = 1.0f;
158 viewport.scale[1] = 1.0f;
159 viewport.scale[2] = 1.0f;
160 viewport.translate[0] = 0.0f;
161 viewport.translate[1] = 0.0f;
162 viewport.translate[2] = 0.0f;
163 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
164
165 /* Upload vertices. The hw rectangle has only 3 vertices,
166 * I guess the 4th one is derived from the first 3.
167 * The vertex specification should match u_blitter's vertex element state. */
168 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
169 if (!buf)
170 return;
171
172 vb[0] = x1;
173 vb[1] = y1;
174 vb[2] = depth;
175 vb[3] = 1;
176
177 vb[8] = x1;
178 vb[9] = y2;
179 vb[10] = depth;
180 vb[11] = 1;
181
182 vb[16] = x2;
183 vb[17] = y1;
184 vb[18] = depth;
185 vb[19] = 1;
186
187 if (attrib) {
188 memcpy(vb+4, attrib->f, sizeof(float)*4);
189 memcpy(vb+12, attrib->f, sizeof(float)*4);
190 memcpy(vb+20, attrib->f, sizeof(float)*4);
191 }
192
193 /* draw */
194 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
195 R600_PRIM_RECTANGLE_LIST, 3, 2);
196 pipe_resource_reference(&buf, NULL);
197 }
198
199 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
200 struct r600_resource *dst, struct r600_resource *src)
201 {
202 uint64_t vram = 0, gtt = 0;
203
204 if (dst) {
205 vram += dst->vram_usage;
206 gtt += dst->gart_usage;
207 }
208 if (src) {
209 vram += src->vram_usage;
210 gtt += src->gart_usage;
211 }
212
213 /* Flush the GFX IB if DMA depends on it. */
214 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
215 ((dst &&
216 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
217 RADEON_USAGE_READWRITE)) ||
218 (src &&
219 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
220 RADEON_USAGE_WRITE))))
221 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
222
223 /* Flush if there's not enough space, or if the memory usage per IB
224 * is too large.
225 */
226 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
227 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
228 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
229 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
230 }
231
232 /* If GPUVM is not supported, the CS checker needs 2 entries
233 * in the buffer list per packet, which has to be done manually.
234 */
235 if (ctx->screen->info.has_virtual_memory) {
236 if (dst)
237 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
238 RADEON_USAGE_WRITE,
239 RADEON_PRIO_SDMA_BUFFER);
240 if (src)
241 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
242 RADEON_USAGE_READ,
243 RADEON_PRIO_SDMA_BUFFER);
244 }
245 }
246
247 /* This is required to prevent read-after-write hazards. */
248 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
249 {
250 struct radeon_winsys_cs *cs = rctx->dma.cs;
251
252 /* done at the end of DMA calls, so increment this. */
253 rctx->num_dma_calls++;
254
255 /* IBs using too little memory are limited by the IB submission overhead.
256 * IBs using too much memory are limited by the kernel/TTM overhead.
257 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
258 *
259 * This heuristic makes sure that DMA requests are executed
260 * very soon after the call is made and lowers memory usage.
261 * It improves texture upload performance by keeping the DMA
262 * engine busy while uploads are being submitted.
263 */
264 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
265 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
266 return;
267 }
268
269 r600_need_dma_space(rctx, 1, NULL, NULL);
270
271 if (!radeon_emitted(cs, 0)) /* empty queue */
272 return;
273
274 /* NOP waits for idle on Evergreen and later. */
275 if (rctx->chip_class >= CIK)
276 radeon_emit(cs, 0x00000000); /* NOP */
277 else if (rctx->chip_class >= EVERGREEN)
278 radeon_emit(cs, 0xf0000000); /* NOP */
279 else {
280 /* TODO: R600-R700 should use the FENCE packet.
281 * CS checker support is required. */
282 }
283 }
284
285 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
286 {
287 }
288
289 void r600_preflush_suspend_features(struct r600_common_context *ctx)
290 {
291 /* suspend queries */
292 if (!LIST_IS_EMPTY(&ctx->active_queries))
293 r600_suspend_queries(ctx);
294
295 ctx->streamout.suspended = false;
296 if (ctx->streamout.begin_emitted) {
297 r600_emit_streamout_end(ctx);
298 ctx->streamout.suspended = true;
299 }
300 }
301
302 void r600_postflush_resume_features(struct r600_common_context *ctx)
303 {
304 if (ctx->streamout.suspended) {
305 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
306 r600_streamout_buffers_dirty(ctx);
307 }
308
309 /* resume queries */
310 if (!LIST_IS_EMPTY(&ctx->active_queries))
311 r600_resume_queries(ctx);
312 }
313
314 static void r600_flush_from_st(struct pipe_context *ctx,
315 struct pipe_fence_handle **fence,
316 unsigned flags)
317 {
318 struct pipe_screen *screen = ctx->screen;
319 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
320 struct radeon_winsys *ws = rctx->ws;
321 unsigned rflags = 0;
322 struct pipe_fence_handle *gfx_fence = NULL;
323 struct pipe_fence_handle *sdma_fence = NULL;
324 bool deferred_fence = false;
325
326 if (flags & PIPE_FLUSH_END_OF_FRAME)
327 rflags |= RADEON_FLUSH_END_OF_FRAME;
328 if (flags & PIPE_FLUSH_DEFERRED)
329 rflags |= RADEON_FLUSH_ASYNC;
330
331 if (rctx->dma.cs) {
332 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
333 }
334
335 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
336 if (fence)
337 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
338 if (!(rflags & RADEON_FLUSH_ASYNC))
339 ws->cs_sync_flush(rctx->gfx.cs);
340 } else {
341 /* Instead of flushing, create a deferred fence. Constraints:
342 * - The state tracker must allow a deferred flush.
343 * - The state tracker must request a fence.
344 * Thread safety in fence_finish must be ensured by the state tracker.
345 */
346 if (flags & PIPE_FLUSH_DEFERRED && fence) {
347 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
348 deferred_fence = true;
349 } else {
350 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
351 }
352 }
353
354 /* Both engines can signal out of order, so we need to keep both fences. */
355 if (fence) {
356 struct r600_multi_fence *multi_fence =
357 CALLOC_STRUCT(r600_multi_fence);
358 if (!multi_fence)
359 return;
360
361 multi_fence->reference.count = 1;
362 /* If both fences are NULL, fence_finish will always return true. */
363 multi_fence->gfx = gfx_fence;
364 multi_fence->sdma = sdma_fence;
365
366 if (deferred_fence) {
367 multi_fence->gfx_unflushed.ctx = rctx;
368 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
369 }
370
371 screen->fence_reference(screen, fence, NULL);
372 *fence = (struct pipe_fence_handle*)multi_fence;
373 }
374 }
375
376 static void r600_flush_dma_ring(void *ctx, unsigned flags,
377 struct pipe_fence_handle **fence)
378 {
379 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
380 struct radeon_winsys_cs *cs = rctx->dma.cs;
381 struct radeon_saved_cs saved;
382 bool check_vm =
383 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
384 rctx->check_vm_faults;
385
386 if (!radeon_emitted(cs, 0)) {
387 if (fence)
388 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
389 return;
390 }
391
392 if (check_vm)
393 radeon_save_cs(rctx->ws, cs, &saved);
394
395 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
396 if (fence)
397 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
398
399 if (check_vm) {
400 /* Use conservative timeout 800ms, after which we won't wait any
401 * longer and assume the GPU is hung.
402 */
403 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
404
405 rctx->check_vm_faults(rctx, &saved, RING_DMA);
406 radeon_clear_saved_cs(&saved);
407 }
408 }
409
410 /**
411 * Store a linearized copy of all chunks of \p cs together with the buffer
412 * list in \p saved.
413 */
414 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
415 struct radeon_saved_cs *saved)
416 {
417 void *buf;
418 unsigned i;
419
420 /* Save the IB chunks. */
421 saved->num_dw = cs->prev_dw + cs->current.cdw;
422 saved->ib = MALLOC(4 * saved->num_dw);
423 if (!saved->ib)
424 goto oom;
425
426 buf = saved->ib;
427 for (i = 0; i < cs->num_prev; ++i) {
428 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
429 buf += cs->prev[i].cdw;
430 }
431 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
432
433 /* Save the buffer list. */
434 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
435 saved->bo_list = CALLOC(saved->bo_count,
436 sizeof(saved->bo_list[0]));
437 if (!saved->bo_list) {
438 FREE(saved->ib);
439 goto oom;
440 }
441 ws->cs_get_buffer_list(cs, saved->bo_list);
442
443 return;
444
445 oom:
446 fprintf(stderr, "%s: out of memory\n", __func__);
447 memset(saved, 0, sizeof(*saved));
448 }
449
450 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
451 {
452 FREE(saved->ib);
453 FREE(saved->bo_list);
454
455 memset(saved, 0, sizeof(*saved));
456 }
457
458 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
459 {
460 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
461 unsigned latest = rctx->ws->query_value(rctx->ws,
462 RADEON_GPU_RESET_COUNTER);
463
464 if (rctx->gpu_reset_counter == latest)
465 return PIPE_NO_RESET;
466
467 rctx->gpu_reset_counter = latest;
468 return PIPE_UNKNOWN_CONTEXT_RESET;
469 }
470
471 static void r600_set_debug_callback(struct pipe_context *ctx,
472 const struct pipe_debug_callback *cb)
473 {
474 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
475
476 if (cb)
477 rctx->debug = *cb;
478 else
479 memset(&rctx->debug, 0, sizeof(rctx->debug));
480 }
481
482 bool r600_common_context_init(struct r600_common_context *rctx,
483 struct r600_common_screen *rscreen,
484 unsigned context_flags)
485 {
486 slab_create(&rctx->pool_transfers,
487 sizeof(struct r600_transfer), 64);
488
489 rctx->screen = rscreen;
490 rctx->ws = rscreen->ws;
491 rctx->family = rscreen->family;
492 rctx->chip_class = rscreen->chip_class;
493
494 if (rscreen->chip_class >= CIK)
495 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
496 else if (rscreen->chip_class >= EVERGREEN)
497 rctx->max_db = 8;
498 else
499 rctx->max_db = 4;
500
501 rctx->b.invalidate_resource = r600_invalidate_resource;
502 rctx->b.transfer_map = u_transfer_map_vtbl;
503 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
504 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
505 rctx->b.texture_subdata = u_default_texture_subdata;
506 rctx->b.memory_barrier = r600_memory_barrier;
507 rctx->b.flush = r600_flush_from_st;
508 rctx->b.set_debug_callback = r600_set_debug_callback;
509
510 /* evergreen_compute.c has a special codepath for global buffers.
511 * Everything else can use the direct path.
512 */
513 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
514 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
515 rctx->b.buffer_subdata = u_default_buffer_subdata;
516 else
517 rctx->b.buffer_subdata = r600_buffer_subdata;
518
519 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
520 rctx->b.get_device_reset_status = r600_get_reset_status;
521 rctx->gpu_reset_counter =
522 rctx->ws->query_value(rctx->ws,
523 RADEON_GPU_RESET_COUNTER);
524 }
525
526 LIST_INITHEAD(&rctx->texture_buffers);
527
528 r600_init_context_texture_functions(rctx);
529 r600_init_viewport_functions(rctx);
530 r600_streamout_init(rctx);
531 r600_query_init(rctx);
532 cayman_init_msaa(&rctx->b);
533
534 rctx->allocator_zeroed_memory =
535 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
536 0, PIPE_USAGE_DEFAULT, true);
537 if (!rctx->allocator_zeroed_memory)
538 return false;
539
540 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
541 PIPE_BIND_INDEX_BUFFER |
542 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
543 if (!rctx->uploader)
544 return false;
545
546 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
547 if (!rctx->ctx)
548 return false;
549
550 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
551 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
552 r600_flush_dma_ring,
553 rctx);
554 rctx->dma.flush = r600_flush_dma_ring;
555 }
556
557 return true;
558 }
559
560 void r600_common_context_cleanup(struct r600_common_context *rctx)
561 {
562 unsigned i,j;
563
564 /* Release DCC stats. */
565 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
566 assert(!rctx->dcc_stats[i].query_active);
567
568 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
569 if (rctx->dcc_stats[i].ps_stats[j])
570 rctx->b.destroy_query(&rctx->b,
571 rctx->dcc_stats[i].ps_stats[j]);
572
573 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
574 }
575
576 if (rctx->query_result_shader)
577 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
578
579 if (rctx->gfx.cs)
580 rctx->ws->cs_destroy(rctx->gfx.cs);
581 if (rctx->dma.cs)
582 rctx->ws->cs_destroy(rctx->dma.cs);
583 if (rctx->ctx)
584 rctx->ws->ctx_destroy(rctx->ctx);
585
586 if (rctx->uploader) {
587 u_upload_destroy(rctx->uploader);
588 }
589
590 slab_destroy(&rctx->pool_transfers);
591
592 if (rctx->allocator_zeroed_memory) {
593 u_suballocator_destroy(rctx->allocator_zeroed_memory);
594 }
595 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
596 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
597 }
598
599 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
600 {
601 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
602 struct r600_resource *rr = (struct r600_resource *)r;
603
604 if (!r) {
605 return;
606 }
607
608 /*
609 * The idea is to compute a gross estimate of memory requirement of
610 * each draw call. After each draw call, memory will be precisely
611 * accounted. So the uncertainty is only on the current draw call.
612 * In practice this gave very good estimate (+/- 10% of the target
613 * memory limit).
614 */
615 rctx->vram += rr->vram_usage;
616 rctx->gtt += rr->gart_usage;
617 }
618
619 /*
620 * pipe_screen
621 */
622
623 static const struct debug_named_value common_debug_options[] = {
624 /* logging */
625 { "tex", DBG_TEX, "Print texture info" },
626 { "compute", DBG_COMPUTE, "Print compute info" },
627 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
628 { "info", DBG_INFO, "Print driver information" },
629
630 /* shaders */
631 { "fs", DBG_FS, "Print fetch shaders" },
632 { "vs", DBG_VS, "Print vertex shaders" },
633 { "gs", DBG_GS, "Print geometry shaders" },
634 { "ps", DBG_PS, "Print pixel shaders" },
635 { "cs", DBG_CS, "Print compute shaders" },
636 { "tcs", DBG_TCS, "Print tessellation control shaders" },
637 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
638 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
639 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
640 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
641 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
642
643 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
644
645 /* features */
646 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
647 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
648 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
649 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
650 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
651 { "notiling", DBG_NO_TILING, "Disable tiling" },
652 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
653 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
654 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
655 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
656 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
657 { "nodcc", DBG_NO_DCC, "Disable DCC." },
658 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
659 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
660 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
661 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
662 { "noce", DBG_NO_CE, "Disable the constant engine"},
663 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
664 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
665
666 DEBUG_NAMED_VALUE_END /* must be last */
667 };
668
669 static const char* r600_get_vendor(struct pipe_screen* pscreen)
670 {
671 return "X.Org";
672 }
673
674 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
675 {
676 return "AMD";
677 }
678
679 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
680 {
681 switch (rscreen->info.family) {
682 case CHIP_R600: return "AMD R600";
683 case CHIP_RV610: return "AMD RV610";
684 case CHIP_RV630: return "AMD RV630";
685 case CHIP_RV670: return "AMD RV670";
686 case CHIP_RV620: return "AMD RV620";
687 case CHIP_RV635: return "AMD RV635";
688 case CHIP_RS780: return "AMD RS780";
689 case CHIP_RS880: return "AMD RS880";
690 case CHIP_RV770: return "AMD RV770";
691 case CHIP_RV730: return "AMD RV730";
692 case CHIP_RV710: return "AMD RV710";
693 case CHIP_RV740: return "AMD RV740";
694 case CHIP_CEDAR: return "AMD CEDAR";
695 case CHIP_REDWOOD: return "AMD REDWOOD";
696 case CHIP_JUNIPER: return "AMD JUNIPER";
697 case CHIP_CYPRESS: return "AMD CYPRESS";
698 case CHIP_HEMLOCK: return "AMD HEMLOCK";
699 case CHIP_PALM: return "AMD PALM";
700 case CHIP_SUMO: return "AMD SUMO";
701 case CHIP_SUMO2: return "AMD SUMO2";
702 case CHIP_BARTS: return "AMD BARTS";
703 case CHIP_TURKS: return "AMD TURKS";
704 case CHIP_CAICOS: return "AMD CAICOS";
705 case CHIP_CAYMAN: return "AMD CAYMAN";
706 case CHIP_ARUBA: return "AMD ARUBA";
707 case CHIP_TAHITI: return "AMD TAHITI";
708 case CHIP_PITCAIRN: return "AMD PITCAIRN";
709 case CHIP_VERDE: return "AMD CAPE VERDE";
710 case CHIP_OLAND: return "AMD OLAND";
711 case CHIP_HAINAN: return "AMD HAINAN";
712 case CHIP_BONAIRE: return "AMD BONAIRE";
713 case CHIP_KAVERI: return "AMD KAVERI";
714 case CHIP_KABINI: return "AMD KABINI";
715 case CHIP_HAWAII: return "AMD HAWAII";
716 case CHIP_MULLINS: return "AMD MULLINS";
717 case CHIP_TONGA: return "AMD TONGA";
718 case CHIP_ICELAND: return "AMD ICELAND";
719 case CHIP_CARRIZO: return "AMD CARRIZO";
720 case CHIP_FIJI: return "AMD FIJI";
721 case CHIP_POLARIS10: return "AMD POLARIS10";
722 case CHIP_POLARIS11: return "AMD POLARIS11";
723 case CHIP_STONEY: return "AMD STONEY";
724 default: return "AMD unknown";
725 }
726 }
727
728 static const char* r600_get_name(struct pipe_screen* pscreen)
729 {
730 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
731
732 return rscreen->renderer_string;
733 }
734
735 static float r600_get_paramf(struct pipe_screen* pscreen,
736 enum pipe_capf param)
737 {
738 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
739
740 switch (param) {
741 case PIPE_CAPF_MAX_LINE_WIDTH:
742 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
743 case PIPE_CAPF_MAX_POINT_WIDTH:
744 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
745 if (rscreen->family >= CHIP_CEDAR)
746 return 16384.0f;
747 else
748 return 8192.0f;
749 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
750 return 16.0f;
751 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
752 return 16.0f;
753 case PIPE_CAPF_GUARD_BAND_LEFT:
754 case PIPE_CAPF_GUARD_BAND_TOP:
755 case PIPE_CAPF_GUARD_BAND_RIGHT:
756 case PIPE_CAPF_GUARD_BAND_BOTTOM:
757 return 0.0f;
758 }
759 return 0.0f;
760 }
761
762 static int r600_get_video_param(struct pipe_screen *screen,
763 enum pipe_video_profile profile,
764 enum pipe_video_entrypoint entrypoint,
765 enum pipe_video_cap param)
766 {
767 switch (param) {
768 case PIPE_VIDEO_CAP_SUPPORTED:
769 return vl_profile_supported(screen, profile, entrypoint);
770 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
771 return 1;
772 case PIPE_VIDEO_CAP_MAX_WIDTH:
773 case PIPE_VIDEO_CAP_MAX_HEIGHT:
774 return vl_video_buffer_max_size(screen);
775 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
776 return PIPE_FORMAT_NV12;
777 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
778 return false;
779 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
780 return false;
781 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
782 return true;
783 case PIPE_VIDEO_CAP_MAX_LEVEL:
784 return vl_level_supported(screen, profile);
785 default:
786 return 0;
787 }
788 }
789
790 const char *r600_get_llvm_processor_name(enum radeon_family family)
791 {
792 switch (family) {
793 case CHIP_R600:
794 case CHIP_RV630:
795 case CHIP_RV635:
796 case CHIP_RV670:
797 return "r600";
798 case CHIP_RV610:
799 case CHIP_RV620:
800 case CHIP_RS780:
801 case CHIP_RS880:
802 return "rs880";
803 case CHIP_RV710:
804 return "rv710";
805 case CHIP_RV730:
806 return "rv730";
807 case CHIP_RV740:
808 case CHIP_RV770:
809 return "rv770";
810 case CHIP_PALM:
811 case CHIP_CEDAR:
812 return "cedar";
813 case CHIP_SUMO:
814 case CHIP_SUMO2:
815 return "sumo";
816 case CHIP_REDWOOD:
817 return "redwood";
818 case CHIP_JUNIPER:
819 return "juniper";
820 case CHIP_HEMLOCK:
821 case CHIP_CYPRESS:
822 return "cypress";
823 case CHIP_BARTS:
824 return "barts";
825 case CHIP_TURKS:
826 return "turks";
827 case CHIP_CAICOS:
828 return "caicos";
829 case CHIP_CAYMAN:
830 case CHIP_ARUBA:
831 return "cayman";
832
833 case CHIP_TAHITI: return "tahiti";
834 case CHIP_PITCAIRN: return "pitcairn";
835 case CHIP_VERDE: return "verde";
836 case CHIP_OLAND: return "oland";
837 case CHIP_HAINAN: return "hainan";
838 case CHIP_BONAIRE: return "bonaire";
839 case CHIP_KABINI: return "kabini";
840 case CHIP_KAVERI: return "kaveri";
841 case CHIP_HAWAII: return "hawaii";
842 case CHIP_MULLINS:
843 return "mullins";
844 case CHIP_TONGA: return "tonga";
845 case CHIP_ICELAND: return "iceland";
846 case CHIP_CARRIZO: return "carrizo";
847 #if HAVE_LLVM <= 0x0307
848 case CHIP_FIJI: return "tonga";
849 case CHIP_STONEY: return "carrizo";
850 #else
851 case CHIP_FIJI: return "fiji";
852 case CHIP_STONEY: return "stoney";
853 #endif
854 #if HAVE_LLVM <= 0x0308
855 case CHIP_POLARIS10: return "tonga";
856 case CHIP_POLARIS11: return "tonga";
857 #else
858 case CHIP_POLARIS10: return "polaris10";
859 case CHIP_POLARIS11: return "polaris11";
860 #endif
861 default: return "";
862 }
863 }
864
865 static int r600_get_compute_param(struct pipe_screen *screen,
866 enum pipe_shader_ir ir_type,
867 enum pipe_compute_cap param,
868 void *ret)
869 {
870 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
871
872 //TODO: select these params by asic
873 switch (param) {
874 case PIPE_COMPUTE_CAP_IR_TARGET: {
875 const char *gpu;
876 const char *triple;
877 if (rscreen->family <= CHIP_ARUBA) {
878 triple = "r600--";
879 } else {
880 if (HAVE_LLVM < 0x0400) {
881 triple = "amdgcn--";
882 } else {
883 triple = "amdgcn-mesa-mesa3d";
884 }
885 }
886 switch(rscreen->family) {
887 /* Clang < 3.6 is missing Hainan in its list of
888 * GPUs, so we need to use the name of a similar GPU.
889 */
890 default:
891 gpu = r600_get_llvm_processor_name(rscreen->family);
892 break;
893 }
894 if (ret) {
895 sprintf(ret, "%s-%s", gpu, triple);
896 }
897 /* +2 for dash and terminating NIL byte */
898 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
899 }
900 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
901 if (ret) {
902 uint64_t *grid_dimension = ret;
903 grid_dimension[0] = 3;
904 }
905 return 1 * sizeof(uint64_t);
906
907 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
908 if (ret) {
909 uint64_t *grid_size = ret;
910 grid_size[0] = 65535;
911 grid_size[1] = 65535;
912 grid_size[2] = 65535;
913 }
914 return 3 * sizeof(uint64_t) ;
915
916 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
917 if (ret) {
918 uint64_t *block_size = ret;
919 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
920 ir_type == PIPE_SHADER_IR_TGSI) {
921 block_size[0] = 2048;
922 block_size[1] = 2048;
923 block_size[2] = 2048;
924 } else {
925 block_size[0] = 256;
926 block_size[1] = 256;
927 block_size[2] = 256;
928 }
929 }
930 return 3 * sizeof(uint64_t);
931
932 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
933 if (ret) {
934 uint64_t *max_threads_per_block = ret;
935 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
936 ir_type == PIPE_SHADER_IR_TGSI)
937 *max_threads_per_block = 2048;
938 else
939 *max_threads_per_block = 256;
940 }
941 return sizeof(uint64_t);
942 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
943 if (ret) {
944 uint32_t *address_bits = ret;
945 address_bits[0] = 32;
946 if (rscreen->chip_class >= SI)
947 address_bits[0] = 64;
948 }
949 return 1 * sizeof(uint32_t);
950
951 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
952 if (ret) {
953 uint64_t *max_global_size = ret;
954 uint64_t max_mem_alloc_size;
955
956 r600_get_compute_param(screen, ir_type,
957 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
958 &max_mem_alloc_size);
959
960 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
961 * 1/4 of the MAX_GLOBAL_SIZE. Since the
962 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
963 * make sure we never report more than
964 * 4 * MAX_MEM_ALLOC_SIZE.
965 */
966 *max_global_size = MIN2(4 * max_mem_alloc_size,
967 MAX2(rscreen->info.gart_size,
968 rscreen->info.vram_size));
969 }
970 return sizeof(uint64_t);
971
972 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
973 if (ret) {
974 uint64_t *max_local_size = ret;
975 /* Value reported by the closed source driver. */
976 *max_local_size = 32768;
977 }
978 return sizeof(uint64_t);
979
980 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
981 if (ret) {
982 uint64_t *max_input_size = ret;
983 /* Value reported by the closed source driver. */
984 *max_input_size = 1024;
985 }
986 return sizeof(uint64_t);
987
988 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
989 if (ret) {
990 uint64_t *max_mem_alloc_size = ret;
991
992 *max_mem_alloc_size = rscreen->info.max_alloc_size;
993 }
994 return sizeof(uint64_t);
995
996 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
997 if (ret) {
998 uint32_t *max_clock_frequency = ret;
999 *max_clock_frequency = rscreen->info.max_shader_clock;
1000 }
1001 return sizeof(uint32_t);
1002
1003 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1004 if (ret) {
1005 uint32_t *max_compute_units = ret;
1006 *max_compute_units = rscreen->info.num_good_compute_units;
1007 }
1008 return sizeof(uint32_t);
1009
1010 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1011 if (ret) {
1012 uint32_t *images_supported = ret;
1013 *images_supported = 0;
1014 }
1015 return sizeof(uint32_t);
1016 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1017 break; /* unused */
1018 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1019 if (ret) {
1020 uint32_t *subgroup_size = ret;
1021 *subgroup_size = r600_wavefront_size(rscreen->family);
1022 }
1023 return sizeof(uint32_t);
1024 }
1025
1026 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1027 return 0;
1028 }
1029
1030 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1031 {
1032 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1033
1034 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1035 rscreen->info.clock_crystal_freq;
1036 }
1037
1038 static void r600_fence_reference(struct pipe_screen *screen,
1039 struct pipe_fence_handle **dst,
1040 struct pipe_fence_handle *src)
1041 {
1042 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1043 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1044 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1045
1046 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1047 ws->fence_reference(&(*rdst)->gfx, NULL);
1048 ws->fence_reference(&(*rdst)->sdma, NULL);
1049 FREE(*rdst);
1050 }
1051 *rdst = rsrc;
1052 }
1053
1054 static boolean r600_fence_finish(struct pipe_screen *screen,
1055 struct pipe_context *ctx,
1056 struct pipe_fence_handle *fence,
1057 uint64_t timeout)
1058 {
1059 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1060 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1061 struct r600_common_context *rctx =
1062 ctx ? (struct r600_common_context*)ctx : NULL;
1063 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1064
1065 if (rfence->sdma) {
1066 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1067 return false;
1068
1069 /* Recompute the timeout after waiting. */
1070 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1071 int64_t time = os_time_get_nano();
1072 timeout = abs_timeout > time ? abs_timeout - time : 0;
1073 }
1074 }
1075
1076 if (!rfence->gfx)
1077 return true;
1078
1079 /* Flush the gfx IB if it hasn't been flushed yet. */
1080 if (rctx &&
1081 rfence->gfx_unflushed.ctx == rctx &&
1082 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1083 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1084 rfence->gfx_unflushed.ctx = NULL;
1085
1086 if (!timeout)
1087 return false;
1088
1089 /* Recompute the timeout after all that. */
1090 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1091 int64_t time = os_time_get_nano();
1092 timeout = abs_timeout > time ? abs_timeout - time : 0;
1093 }
1094 }
1095
1096 return rws->fence_wait(rws, rfence->gfx, timeout);
1097 }
1098
1099 static void r600_query_memory_info(struct pipe_screen *screen,
1100 struct pipe_memory_info *info)
1101 {
1102 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1103 struct radeon_winsys *ws = rscreen->ws;
1104 unsigned vram_usage, gtt_usage;
1105
1106 info->total_device_memory = rscreen->info.vram_size / 1024;
1107 info->total_staging_memory = rscreen->info.gart_size / 1024;
1108
1109 /* The real TTM memory usage is somewhat random, because:
1110 *
1111 * 1) TTM delays freeing memory, because it can only free it after
1112 * fences expire.
1113 *
1114 * 2) The memory usage can be really low if big VRAM evictions are
1115 * taking place, but the real usage is well above the size of VRAM.
1116 *
1117 * Instead, return statistics of this process.
1118 */
1119 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1120 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1121
1122 info->avail_device_memory =
1123 vram_usage <= info->total_device_memory ?
1124 info->total_device_memory - vram_usage : 0;
1125 info->avail_staging_memory =
1126 gtt_usage <= info->total_staging_memory ?
1127 info->total_staging_memory - gtt_usage : 0;
1128
1129 info->device_memory_evicted =
1130 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1131
1132 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1133 info->nr_device_memory_evictions =
1134 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1135 else
1136 /* Just return the number of evicted 64KB pages. */
1137 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1138 }
1139
1140 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1141 const struct pipe_resource *templ)
1142 {
1143 if (templ->target == PIPE_BUFFER) {
1144 return r600_buffer_create(screen, templ, 256);
1145 } else {
1146 return r600_texture_create(screen, templ);
1147 }
1148 }
1149
1150 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1151 struct radeon_winsys *ws)
1152 {
1153 char llvm_string[32] = {}, kernel_version[128] = {};
1154 struct utsname uname_data;
1155
1156 ws->query_info(ws, &rscreen->info);
1157
1158 if (uname(&uname_data) == 0)
1159 snprintf(kernel_version, sizeof(kernel_version),
1160 " / %s", uname_data.release);
1161
1162 #if HAVE_LLVM
1163 snprintf(llvm_string, sizeof(llvm_string),
1164 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1165 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1166 #endif
1167
1168 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1169 "%s (DRM %i.%i.%i%s%s)",
1170 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1171 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1172 kernel_version, llvm_string);
1173
1174 rscreen->b.get_name = r600_get_name;
1175 rscreen->b.get_vendor = r600_get_vendor;
1176 rscreen->b.get_device_vendor = r600_get_device_vendor;
1177 rscreen->b.get_compute_param = r600_get_compute_param;
1178 rscreen->b.get_paramf = r600_get_paramf;
1179 rscreen->b.get_timestamp = r600_get_timestamp;
1180 rscreen->b.fence_finish = r600_fence_finish;
1181 rscreen->b.fence_reference = r600_fence_reference;
1182 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1183 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1184 rscreen->b.query_memory_info = r600_query_memory_info;
1185
1186 if (rscreen->info.has_uvd) {
1187 rscreen->b.get_video_param = rvid_get_video_param;
1188 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1189 } else {
1190 rscreen->b.get_video_param = r600_get_video_param;
1191 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1192 }
1193
1194 r600_init_screen_texture_functions(rscreen);
1195 r600_init_screen_query_functions(rscreen);
1196
1197 rscreen->ws = ws;
1198 rscreen->family = rscreen->info.family;
1199 rscreen->chip_class = rscreen->info.chip_class;
1200 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1201
1202 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1203 if (rscreen->force_aniso >= 0) {
1204 printf("radeon: Forcing anisotropy filter to %ix\n",
1205 /* round down to a power of two */
1206 1 << util_logbase2(rscreen->force_aniso));
1207 }
1208
1209 util_format_s3tc_init();
1210 pipe_mutex_init(rscreen->aux_context_lock);
1211 pipe_mutex_init(rscreen->gpu_load_mutex);
1212
1213 if (rscreen->debug_flags & DBG_INFO) {
1214 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1215 printf("family = %i (%s)\n", rscreen->info.family,
1216 r600_get_chip_name(rscreen));
1217 printf("chip_class = %i\n", rscreen->info.chip_class);
1218 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1219 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1220 printf("max_alloc_size = %i MB\n",
1221 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1222 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1223 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1224 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1225 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1226 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1227 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1228 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1229 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1230 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1231 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1232 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1233 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1234 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1235
1236 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1237 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1238 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1239 printf("max_se = %i\n", rscreen->info.max_se);
1240 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1241
1242 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1243 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1244 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1245 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1246 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1247 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1248 }
1249 return true;
1250 }
1251
1252 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1253 {
1254 r600_perfcounters_destroy(rscreen);
1255 r600_gpu_load_kill_thread(rscreen);
1256
1257 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1258 pipe_mutex_destroy(rscreen->aux_context_lock);
1259 rscreen->aux_context->destroy(rscreen->aux_context);
1260
1261 rscreen->ws->destroy(rscreen->ws);
1262 FREE(rscreen);
1263 }
1264
1265 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1266 unsigned processor)
1267 {
1268 switch (processor) {
1269 case PIPE_SHADER_VERTEX:
1270 return (rscreen->debug_flags & DBG_VS) != 0;
1271 case PIPE_SHADER_TESS_CTRL:
1272 return (rscreen->debug_flags & DBG_TCS) != 0;
1273 case PIPE_SHADER_TESS_EVAL:
1274 return (rscreen->debug_flags & DBG_TES) != 0;
1275 case PIPE_SHADER_GEOMETRY:
1276 return (rscreen->debug_flags & DBG_GS) != 0;
1277 case PIPE_SHADER_FRAGMENT:
1278 return (rscreen->debug_flags & DBG_PS) != 0;
1279 case PIPE_SHADER_COMPUTE:
1280 return (rscreen->debug_flags & DBG_CS) != 0;
1281 default:
1282 return false;
1283 }
1284 }
1285
1286 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1287 uint64_t offset, uint64_t size, unsigned value,
1288 enum r600_coherency coher)
1289 {
1290 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1291
1292 pipe_mutex_lock(rscreen->aux_context_lock);
1293 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1294 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1295 pipe_mutex_unlock(rscreen->aux_context_lock);
1296 }