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gallium/radeon: print all members of radeon_info with R600_DEBUG=info
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t old_fence, uint32_t new_fence)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112
113 if (ctx->chip_class >= GFX9) {
114 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
115 radeon_emit(cs, op);
116 radeon_emit(cs, EOP_DATA_SEL(data_sel));
117 radeon_emit(cs, va); /* address lo */
118 radeon_emit(cs, va >> 32); /* address hi */
119 radeon_emit(cs, new_fence); /* immediate data lo */
120 radeon_emit(cs, 0); /* immediate data hi */
121 radeon_emit(cs, 0); /* unused */
122 } else {
123 if (ctx->chip_class == CIK ||
124 ctx->chip_class == VI) {
125 /* Two EOP events are required to make all engines go idle
126 * (and optional cache flushes executed) before the timestamp
127 * is written.
128 */
129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
130 radeon_emit(cs, op);
131 radeon_emit(cs, va);
132 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
133 radeon_emit(cs, old_fence); /* immediate data */
134 radeon_emit(cs, 0); /* unused */
135 }
136
137 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
138 radeon_emit(cs, op);
139 radeon_emit(cs, va);
140 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
141 radeon_emit(cs, new_fence); /* immediate data */
142 radeon_emit(cs, 0); /* unused */
143 }
144
145 if (buf)
146 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
147 RADEON_PRIO_QUERY);
148 }
149
150 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
151 {
152 unsigned dwords = 6;
153
154 if (screen->chip_class == CIK ||
155 screen->chip_class == VI)
156 dwords *= 2;
157
158 if (!screen->info.has_virtual_memory)
159 dwords += 2;
160
161 return dwords;
162 }
163
164 void r600_gfx_wait_fence(struct r600_common_context *ctx,
165 uint64_t va, uint32_t ref, uint32_t mask)
166 {
167 struct radeon_winsys_cs *cs = ctx->gfx.cs;
168
169 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
170 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
171 radeon_emit(cs, va);
172 radeon_emit(cs, va >> 32);
173 radeon_emit(cs, ref); /* reference value */
174 radeon_emit(cs, mask); /* mask */
175 radeon_emit(cs, 4); /* poll interval */
176 }
177
178 void r600_draw_rectangle(struct blitter_context *blitter,
179 int x1, int y1, int x2, int y2, float depth,
180 enum blitter_attrib_type type,
181 const union pipe_color_union *attrib)
182 {
183 struct r600_common_context *rctx =
184 (struct r600_common_context*)util_blitter_get_pipe(blitter);
185 struct pipe_viewport_state viewport;
186 struct pipe_resource *buf = NULL;
187 unsigned offset = 0;
188 float *vb;
189
190 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
191 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
192 return;
193 }
194
195 /* Some operations (like color resolve on r6xx) don't work
196 * with the conventional primitive types.
197 * One that works is PT_RECTLIST, which we use here. */
198
199 /* setup viewport */
200 viewport.scale[0] = 1.0f;
201 viewport.scale[1] = 1.0f;
202 viewport.scale[2] = 1.0f;
203 viewport.translate[0] = 0.0f;
204 viewport.translate[1] = 0.0f;
205 viewport.translate[2] = 0.0f;
206 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
207
208 /* Upload vertices. The hw rectangle has only 3 vertices,
209 * I guess the 4th one is derived from the first 3.
210 * The vertex specification should match u_blitter's vertex element state. */
211 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
212 rctx->screen->info.tcc_cache_line_size,
213 &offset, &buf, (void**)&vb);
214 if (!buf)
215 return;
216
217 vb[0] = x1;
218 vb[1] = y1;
219 vb[2] = depth;
220 vb[3] = 1;
221
222 vb[8] = x1;
223 vb[9] = y2;
224 vb[10] = depth;
225 vb[11] = 1;
226
227 vb[16] = x2;
228 vb[17] = y1;
229 vb[18] = depth;
230 vb[19] = 1;
231
232 if (attrib) {
233 memcpy(vb+4, attrib->f, sizeof(float)*4);
234 memcpy(vb+12, attrib->f, sizeof(float)*4);
235 memcpy(vb+20, attrib->f, sizeof(float)*4);
236 }
237
238 /* draw */
239 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
240 R600_PRIM_RECTANGLE_LIST, 3, 2);
241 pipe_resource_reference(&buf, NULL);
242 }
243
244 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
245 {
246 struct radeon_winsys_cs *cs = rctx->dma.cs;
247
248 /* NOP waits for idle on Evergreen and later. */
249 if (rctx->chip_class >= CIK)
250 radeon_emit(cs, 0x00000000); /* NOP */
251 else if (rctx->chip_class >= EVERGREEN)
252 radeon_emit(cs, 0xf0000000); /* NOP */
253 else {
254 /* TODO: R600-R700 should use the FENCE packet.
255 * CS checker support is required. */
256 }
257 }
258
259 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
260 struct r600_resource *dst, struct r600_resource *src)
261 {
262 uint64_t vram = ctx->dma.cs->used_vram;
263 uint64_t gtt = ctx->dma.cs->used_gart;
264
265 if (dst) {
266 vram += dst->vram_usage;
267 gtt += dst->gart_usage;
268 }
269 if (src) {
270 vram += src->vram_usage;
271 gtt += src->gart_usage;
272 }
273
274 /* Flush the GFX IB if DMA depends on it. */
275 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
276 ((dst &&
277 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
278 RADEON_USAGE_READWRITE)) ||
279 (src &&
280 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
281 RADEON_USAGE_WRITE))))
282 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
283
284 /* Flush if there's not enough space, or if the memory usage per IB
285 * is too large.
286 *
287 * IBs using too little memory are limited by the IB submission overhead.
288 * IBs using too much memory are limited by the kernel/TTM overhead.
289 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
290 *
291 * This heuristic makes sure that DMA requests are executed
292 * very soon after the call is made and lowers memory usage.
293 * It improves texture upload performance by keeping the DMA
294 * engine busy while uploads are being submitted.
295 */
296 num_dw++; /* for emit_wait_idle below */
297 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
298 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
299 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
300 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
301 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
302 }
303
304 /* Wait for idle if either buffer has been used in the IB before to
305 * prevent read-after-write hazards.
306 */
307 if ((dst &&
308 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
309 RADEON_USAGE_READWRITE)) ||
310 (src &&
311 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
312 RADEON_USAGE_WRITE)))
313 r600_dma_emit_wait_idle(ctx);
314
315 /* If GPUVM is not supported, the CS checker needs 2 entries
316 * in the buffer list per packet, which has to be done manually.
317 */
318 if (ctx->screen->info.has_virtual_memory) {
319 if (dst)
320 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
321 RADEON_USAGE_WRITE,
322 RADEON_PRIO_SDMA_BUFFER);
323 if (src)
324 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
325 RADEON_USAGE_READ,
326 RADEON_PRIO_SDMA_BUFFER);
327 }
328
329 /* this function is called before all DMA calls, so increment this. */
330 ctx->num_dma_calls++;
331 }
332
333 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
334 {
335 }
336
337 void r600_preflush_suspend_features(struct r600_common_context *ctx)
338 {
339 /* suspend queries */
340 if (!LIST_IS_EMPTY(&ctx->active_queries))
341 r600_suspend_queries(ctx);
342
343 ctx->streamout.suspended = false;
344 if (ctx->streamout.begin_emitted) {
345 r600_emit_streamout_end(ctx);
346 ctx->streamout.suspended = true;
347 }
348 }
349
350 void r600_postflush_resume_features(struct r600_common_context *ctx)
351 {
352 if (ctx->streamout.suspended) {
353 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
354 r600_streamout_buffers_dirty(ctx);
355 }
356
357 /* resume queries */
358 if (!LIST_IS_EMPTY(&ctx->active_queries))
359 r600_resume_queries(ctx);
360 }
361
362 static void r600_flush_from_st(struct pipe_context *ctx,
363 struct pipe_fence_handle **fence,
364 unsigned flags)
365 {
366 struct pipe_screen *screen = ctx->screen;
367 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
368 struct radeon_winsys *ws = rctx->ws;
369 struct pipe_fence_handle *gfx_fence = NULL;
370 struct pipe_fence_handle *sdma_fence = NULL;
371 bool deferred_fence = false;
372 unsigned rflags = RADEON_FLUSH_ASYNC;
373
374 if (flags & PIPE_FLUSH_END_OF_FRAME)
375 rflags |= RADEON_FLUSH_END_OF_FRAME;
376
377 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
378 if (rctx->dma.cs)
379 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
380
381 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
382 if (fence)
383 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
384 if (!(flags & PIPE_FLUSH_DEFERRED))
385 ws->cs_sync_flush(rctx->gfx.cs);
386 } else {
387 /* Instead of flushing, create a deferred fence. Constraints:
388 * - The state tracker must allow a deferred flush.
389 * - The state tracker must request a fence.
390 * Thread safety in fence_finish must be ensured by the state tracker.
391 */
392 if (flags & PIPE_FLUSH_DEFERRED && fence) {
393 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
394 deferred_fence = true;
395 } else {
396 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
397 }
398 }
399
400 /* Both engines can signal out of order, so we need to keep both fences. */
401 if (fence) {
402 struct r600_multi_fence *multi_fence =
403 CALLOC_STRUCT(r600_multi_fence);
404 if (!multi_fence)
405 return;
406
407 multi_fence->reference.count = 1;
408 /* If both fences are NULL, fence_finish will always return true. */
409 multi_fence->gfx = gfx_fence;
410 multi_fence->sdma = sdma_fence;
411
412 if (deferred_fence) {
413 multi_fence->gfx_unflushed.ctx = rctx;
414 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
415 }
416
417 screen->fence_reference(screen, fence, NULL);
418 *fence = (struct pipe_fence_handle*)multi_fence;
419 }
420
421 if (!(flags & PIPE_FLUSH_DEFERRED)) {
422 if (rctx->dma.cs)
423 ws->cs_sync_flush(rctx->dma.cs);
424 ws->cs_sync_flush(rctx->gfx.cs);
425 }
426 }
427
428 static void r600_flush_dma_ring(void *ctx, unsigned flags,
429 struct pipe_fence_handle **fence)
430 {
431 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
432 struct radeon_winsys_cs *cs = rctx->dma.cs;
433 struct radeon_saved_cs saved;
434 bool check_vm =
435 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
436 rctx->check_vm_faults;
437
438 if (!radeon_emitted(cs, 0)) {
439 if (fence)
440 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
441 return;
442 }
443
444 if (check_vm)
445 radeon_save_cs(rctx->ws, cs, &saved, true);
446
447 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
448 if (fence)
449 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
450
451 if (check_vm) {
452 /* Use conservative timeout 800ms, after which we won't wait any
453 * longer and assume the GPU is hung.
454 */
455 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
456
457 rctx->check_vm_faults(rctx, &saved, RING_DMA);
458 radeon_clear_saved_cs(&saved);
459 }
460 }
461
462 /**
463 * Store a linearized copy of all chunks of \p cs together with the buffer
464 * list in \p saved.
465 */
466 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
467 struct radeon_saved_cs *saved, bool get_buffer_list)
468 {
469 void *buf;
470 unsigned i;
471
472 /* Save the IB chunks. */
473 saved->num_dw = cs->prev_dw + cs->current.cdw;
474 saved->ib = MALLOC(4 * saved->num_dw);
475 if (!saved->ib)
476 goto oom;
477
478 buf = saved->ib;
479 for (i = 0; i < cs->num_prev; ++i) {
480 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
481 buf += cs->prev[i].cdw;
482 }
483 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
484
485 if (!get_buffer_list)
486 return;
487
488 /* Save the buffer list. */
489 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
490 saved->bo_list = CALLOC(saved->bo_count,
491 sizeof(saved->bo_list[0]));
492 if (!saved->bo_list) {
493 FREE(saved->ib);
494 goto oom;
495 }
496 ws->cs_get_buffer_list(cs, saved->bo_list);
497
498 return;
499
500 oom:
501 fprintf(stderr, "%s: out of memory\n", __func__);
502 memset(saved, 0, sizeof(*saved));
503 }
504
505 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
506 {
507 FREE(saved->ib);
508 FREE(saved->bo_list);
509
510 memset(saved, 0, sizeof(*saved));
511 }
512
513 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
514 {
515 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
516 unsigned latest = rctx->ws->query_value(rctx->ws,
517 RADEON_GPU_RESET_COUNTER);
518
519 if (rctx->gpu_reset_counter == latest)
520 return PIPE_NO_RESET;
521
522 rctx->gpu_reset_counter = latest;
523 return PIPE_UNKNOWN_CONTEXT_RESET;
524 }
525
526 static void r600_set_debug_callback(struct pipe_context *ctx,
527 const struct pipe_debug_callback *cb)
528 {
529 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
530
531 if (cb)
532 rctx->debug = *cb;
533 else
534 memset(&rctx->debug, 0, sizeof(rctx->debug));
535 }
536
537 static void r600_set_device_reset_callback(struct pipe_context *ctx,
538 const struct pipe_device_reset_callback *cb)
539 {
540 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
541
542 if (cb)
543 rctx->device_reset_callback = *cb;
544 else
545 memset(&rctx->device_reset_callback, 0,
546 sizeof(rctx->device_reset_callback));
547 }
548
549 bool r600_check_device_reset(struct r600_common_context *rctx)
550 {
551 enum pipe_reset_status status;
552
553 if (!rctx->device_reset_callback.reset)
554 return false;
555
556 if (!rctx->b.get_device_reset_status)
557 return false;
558
559 status = rctx->b.get_device_reset_status(&rctx->b);
560 if (status == PIPE_NO_RESET)
561 return false;
562
563 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
564 return true;
565 }
566
567 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
568 struct pipe_resource *dst,
569 uint64_t offset, uint64_t size,
570 unsigned value)
571 {
572 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
573
574 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
575 }
576
577 static bool r600_resource_commit(struct pipe_context *pctx,
578 struct pipe_resource *resource,
579 unsigned level, struct pipe_box *box,
580 bool commit)
581 {
582 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
583 struct r600_resource *res = r600_resource(resource);
584
585 /*
586 * Since buffer commitment changes cannot be pipelined, we need to
587 * (a) flush any pending commands that refer to the buffer we're about
588 * to change, and
589 * (b) wait for threaded submit to finish, including those that were
590 * triggered by some other, earlier operation.
591 */
592 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
593 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
594 res->buf, RADEON_USAGE_READWRITE)) {
595 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
596 }
597 if (radeon_emitted(ctx->dma.cs, 0) &&
598 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
599 res->buf, RADEON_USAGE_READWRITE)) {
600 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
601 }
602
603 ctx->ws->cs_sync_flush(ctx->dma.cs);
604 ctx->ws->cs_sync_flush(ctx->gfx.cs);
605
606 assert(resource->target == PIPE_BUFFER);
607
608 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
609 }
610
611 bool r600_common_context_init(struct r600_common_context *rctx,
612 struct r600_common_screen *rscreen,
613 unsigned context_flags)
614 {
615 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
616 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
617
618 rctx->screen = rscreen;
619 rctx->ws = rscreen->ws;
620 rctx->family = rscreen->family;
621 rctx->chip_class = rscreen->chip_class;
622
623 rctx->b.invalidate_resource = r600_invalidate_resource;
624 rctx->b.resource_commit = r600_resource_commit;
625 rctx->b.transfer_map = u_transfer_map_vtbl;
626 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
627 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
628 rctx->b.texture_subdata = u_default_texture_subdata;
629 rctx->b.memory_barrier = r600_memory_barrier;
630 rctx->b.flush = r600_flush_from_st;
631 rctx->b.set_debug_callback = r600_set_debug_callback;
632 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
633
634 /* evergreen_compute.c has a special codepath for global buffers.
635 * Everything else can use the direct path.
636 */
637 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
638 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
639 rctx->b.buffer_subdata = u_default_buffer_subdata;
640 else
641 rctx->b.buffer_subdata = r600_buffer_subdata;
642
643 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
644 rctx->b.get_device_reset_status = r600_get_reset_status;
645 rctx->gpu_reset_counter =
646 rctx->ws->query_value(rctx->ws,
647 RADEON_GPU_RESET_COUNTER);
648 }
649
650 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
651
652 r600_init_context_texture_functions(rctx);
653 r600_init_viewport_functions(rctx);
654 r600_streamout_init(rctx);
655 r600_query_init(rctx);
656 cayman_init_msaa(&rctx->b);
657
658 rctx->allocator_zeroed_memory =
659 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
660 0, PIPE_USAGE_DEFAULT, 0, true);
661 if (!rctx->allocator_zeroed_memory)
662 return false;
663
664 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
665 0, PIPE_USAGE_STREAM);
666 if (!rctx->b.stream_uploader)
667 return false;
668
669 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
670 0, PIPE_USAGE_DEFAULT);
671 if (!rctx->b.const_uploader)
672 return false;
673
674 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
675 if (!rctx->ctx)
676 return false;
677
678 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
679 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
680 r600_flush_dma_ring,
681 rctx);
682 rctx->dma.flush = r600_flush_dma_ring;
683 }
684
685 return true;
686 }
687
688 void r600_common_context_cleanup(struct r600_common_context *rctx)
689 {
690 unsigned i,j;
691
692 /* Release DCC stats. */
693 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
694 assert(!rctx->dcc_stats[i].query_active);
695
696 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
697 if (rctx->dcc_stats[i].ps_stats[j])
698 rctx->b.destroy_query(&rctx->b,
699 rctx->dcc_stats[i].ps_stats[j]);
700
701 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
702 }
703
704 if (rctx->query_result_shader)
705 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
706
707 if (rctx->gfx.cs)
708 rctx->ws->cs_destroy(rctx->gfx.cs);
709 if (rctx->dma.cs)
710 rctx->ws->cs_destroy(rctx->dma.cs);
711 if (rctx->ctx)
712 rctx->ws->ctx_destroy(rctx->ctx);
713
714 if (rctx->b.stream_uploader)
715 u_upload_destroy(rctx->b.stream_uploader);
716 if (rctx->b.const_uploader)
717 u_upload_destroy(rctx->b.const_uploader);
718
719 slab_destroy_child(&rctx->pool_transfers);
720 slab_destroy_child(&rctx->pool_transfers_unsync);
721
722 if (rctx->allocator_zeroed_memory) {
723 u_suballocator_destroy(rctx->allocator_zeroed_memory);
724 }
725 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
726 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
727 }
728
729 /*
730 * pipe_screen
731 */
732
733 static const struct debug_named_value common_debug_options[] = {
734 /* logging */
735 { "tex", DBG_TEX, "Print texture info" },
736 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
737 { "compute", DBG_COMPUTE, "Print compute info" },
738 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
739 { "info", DBG_INFO, "Print driver information" },
740
741 /* shaders */
742 { "fs", DBG_FS, "Print fetch shaders" },
743 { "vs", DBG_VS, "Print vertex shaders" },
744 { "gs", DBG_GS, "Print geometry shaders" },
745 { "ps", DBG_PS, "Print pixel shaders" },
746 { "cs", DBG_CS, "Print compute shaders" },
747 { "tcs", DBG_TCS, "Print tessellation control shaders" },
748 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
749 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
750 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
751 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
752 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
753 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
754 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
755
756 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
757 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
758 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
759 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
760
761 /* features */
762 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
763 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
764 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
765 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
766 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
767 { "notiling", DBG_NO_TILING, "Disable tiling" },
768 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
769 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
770 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
771 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
772 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
773 { "nodcc", DBG_NO_DCC, "Disable DCC." },
774 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
775 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
776 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
777 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
778 { "noce", DBG_NO_CE, "Disable the constant engine"},
779 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
780 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
781
782 DEBUG_NAMED_VALUE_END /* must be last */
783 };
784
785 static const char* r600_get_vendor(struct pipe_screen* pscreen)
786 {
787 return "X.Org";
788 }
789
790 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
791 {
792 return "AMD";
793 }
794
795 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
796 {
797 if (!ws->get_chip_name)
798 return NULL;
799 return ws->get_chip_name(ws);
800 }
801
802 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
803 {
804 switch (rscreen->info.family) {
805 case CHIP_R600: return "AMD R600";
806 case CHIP_RV610: return "AMD RV610";
807 case CHIP_RV630: return "AMD RV630";
808 case CHIP_RV670: return "AMD RV670";
809 case CHIP_RV620: return "AMD RV620";
810 case CHIP_RV635: return "AMD RV635";
811 case CHIP_RS780: return "AMD RS780";
812 case CHIP_RS880: return "AMD RS880";
813 case CHIP_RV770: return "AMD RV770";
814 case CHIP_RV730: return "AMD RV730";
815 case CHIP_RV710: return "AMD RV710";
816 case CHIP_RV740: return "AMD RV740";
817 case CHIP_CEDAR: return "AMD CEDAR";
818 case CHIP_REDWOOD: return "AMD REDWOOD";
819 case CHIP_JUNIPER: return "AMD JUNIPER";
820 case CHIP_CYPRESS: return "AMD CYPRESS";
821 case CHIP_HEMLOCK: return "AMD HEMLOCK";
822 case CHIP_PALM: return "AMD PALM";
823 case CHIP_SUMO: return "AMD SUMO";
824 case CHIP_SUMO2: return "AMD SUMO2";
825 case CHIP_BARTS: return "AMD BARTS";
826 case CHIP_TURKS: return "AMD TURKS";
827 case CHIP_CAICOS: return "AMD CAICOS";
828 case CHIP_CAYMAN: return "AMD CAYMAN";
829 case CHIP_ARUBA: return "AMD ARUBA";
830 case CHIP_TAHITI: return "AMD TAHITI";
831 case CHIP_PITCAIRN: return "AMD PITCAIRN";
832 case CHIP_VERDE: return "AMD CAPE VERDE";
833 case CHIP_OLAND: return "AMD OLAND";
834 case CHIP_HAINAN: return "AMD HAINAN";
835 case CHIP_BONAIRE: return "AMD BONAIRE";
836 case CHIP_KAVERI: return "AMD KAVERI";
837 case CHIP_KABINI: return "AMD KABINI";
838 case CHIP_HAWAII: return "AMD HAWAII";
839 case CHIP_MULLINS: return "AMD MULLINS";
840 case CHIP_TONGA: return "AMD TONGA";
841 case CHIP_ICELAND: return "AMD ICELAND";
842 case CHIP_CARRIZO: return "AMD CARRIZO";
843 case CHIP_FIJI: return "AMD FIJI";
844 case CHIP_POLARIS10: return "AMD POLARIS10";
845 case CHIP_POLARIS11: return "AMD POLARIS11";
846 case CHIP_POLARIS12: return "AMD POLARIS12";
847 case CHIP_STONEY: return "AMD STONEY";
848 case CHIP_VEGA10: return "AMD VEGA10";
849 case CHIP_RAVEN: return "AMD RAVEN";
850 default: return "AMD unknown";
851 }
852 }
853
854 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
855 {
856 /* Don't use the cache if shader dumping is enabled. */
857 if (rscreen->debug_flags &
858 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
859 return;
860
861 uint32_t mesa_timestamp;
862 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
863 &mesa_timestamp)) {
864 char *timestamp_str;
865 int res = -1;
866 if (rscreen->chip_class < SI) {
867 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
868 }
869 #if HAVE_LLVM
870 else {
871 uint32_t llvm_timestamp;
872 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
873 &llvm_timestamp)) {
874 res = asprintf(&timestamp_str, "%u_%u",
875 mesa_timestamp, llvm_timestamp);
876 }
877 }
878 #endif
879 if (res != -1) {
880 rscreen->disk_shader_cache =
881 disk_cache_create(r600_get_family_name(rscreen),
882 timestamp_str,
883 rscreen->debug_flags);
884 free(timestamp_str);
885 }
886 }
887 }
888
889 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
890 {
891 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
892 return rscreen->disk_shader_cache;
893 }
894
895 static const char* r600_get_name(struct pipe_screen* pscreen)
896 {
897 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
898
899 return rscreen->renderer_string;
900 }
901
902 static float r600_get_paramf(struct pipe_screen* pscreen,
903 enum pipe_capf param)
904 {
905 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
906
907 switch (param) {
908 case PIPE_CAPF_MAX_LINE_WIDTH:
909 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
910 case PIPE_CAPF_MAX_POINT_WIDTH:
911 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
912 if (rscreen->family >= CHIP_CEDAR)
913 return 16384.0f;
914 else
915 return 8192.0f;
916 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
917 return 16.0f;
918 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
919 return 16.0f;
920 case PIPE_CAPF_GUARD_BAND_LEFT:
921 case PIPE_CAPF_GUARD_BAND_TOP:
922 case PIPE_CAPF_GUARD_BAND_RIGHT:
923 case PIPE_CAPF_GUARD_BAND_BOTTOM:
924 return 0.0f;
925 }
926 return 0.0f;
927 }
928
929 static int r600_get_video_param(struct pipe_screen *screen,
930 enum pipe_video_profile profile,
931 enum pipe_video_entrypoint entrypoint,
932 enum pipe_video_cap param)
933 {
934 switch (param) {
935 case PIPE_VIDEO_CAP_SUPPORTED:
936 return vl_profile_supported(screen, profile, entrypoint);
937 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
938 return 1;
939 case PIPE_VIDEO_CAP_MAX_WIDTH:
940 case PIPE_VIDEO_CAP_MAX_HEIGHT:
941 return vl_video_buffer_max_size(screen);
942 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
943 return PIPE_FORMAT_NV12;
944 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
945 return false;
946 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
947 return false;
948 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
949 return true;
950 case PIPE_VIDEO_CAP_MAX_LEVEL:
951 return vl_level_supported(screen, profile);
952 default:
953 return 0;
954 }
955 }
956
957 const char *r600_get_llvm_processor_name(enum radeon_family family)
958 {
959 switch (family) {
960 case CHIP_R600:
961 case CHIP_RV630:
962 case CHIP_RV635:
963 case CHIP_RV670:
964 return "r600";
965 case CHIP_RV610:
966 case CHIP_RV620:
967 case CHIP_RS780:
968 case CHIP_RS880:
969 return "rs880";
970 case CHIP_RV710:
971 return "rv710";
972 case CHIP_RV730:
973 return "rv730";
974 case CHIP_RV740:
975 case CHIP_RV770:
976 return "rv770";
977 case CHIP_PALM:
978 case CHIP_CEDAR:
979 return "cedar";
980 case CHIP_SUMO:
981 case CHIP_SUMO2:
982 return "sumo";
983 case CHIP_REDWOOD:
984 return "redwood";
985 case CHIP_JUNIPER:
986 return "juniper";
987 case CHIP_HEMLOCK:
988 case CHIP_CYPRESS:
989 return "cypress";
990 case CHIP_BARTS:
991 return "barts";
992 case CHIP_TURKS:
993 return "turks";
994 case CHIP_CAICOS:
995 return "caicos";
996 case CHIP_CAYMAN:
997 case CHIP_ARUBA:
998 return "cayman";
999
1000 case CHIP_TAHITI: return "tahiti";
1001 case CHIP_PITCAIRN: return "pitcairn";
1002 case CHIP_VERDE: return "verde";
1003 case CHIP_OLAND: return "oland";
1004 case CHIP_HAINAN: return "hainan";
1005 case CHIP_BONAIRE: return "bonaire";
1006 case CHIP_KABINI: return "kabini";
1007 case CHIP_KAVERI: return "kaveri";
1008 case CHIP_HAWAII: return "hawaii";
1009 case CHIP_MULLINS:
1010 return "mullins";
1011 case CHIP_TONGA: return "tonga";
1012 case CHIP_ICELAND: return "iceland";
1013 case CHIP_CARRIZO: return "carrizo";
1014 case CHIP_FIJI:
1015 return "fiji";
1016 case CHIP_STONEY:
1017 return "stoney";
1018 case CHIP_POLARIS10:
1019 return "polaris10";
1020 case CHIP_POLARIS11:
1021 case CHIP_POLARIS12: /* same as polaris11 */
1022 return "polaris11";
1023 case CHIP_VEGA10:
1024 case CHIP_RAVEN:
1025 return "gfx900";
1026 default:
1027 return "";
1028 }
1029 }
1030
1031 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1032 enum pipe_shader_ir ir_type)
1033 {
1034 if (ir_type != PIPE_SHADER_IR_TGSI)
1035 return 256;
1036
1037 /* Only 16 waves per thread-group on gfx9. */
1038 if (screen->chip_class >= GFX9)
1039 return 1024;
1040
1041 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1042 * round number.
1043 */
1044 if (screen->chip_class >= SI)
1045 return 2048;
1046
1047 return 256;
1048 }
1049
1050 static int r600_get_compute_param(struct pipe_screen *screen,
1051 enum pipe_shader_ir ir_type,
1052 enum pipe_compute_cap param,
1053 void *ret)
1054 {
1055 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1056
1057 //TODO: select these params by asic
1058 switch (param) {
1059 case PIPE_COMPUTE_CAP_IR_TARGET: {
1060 const char *gpu;
1061 const char *triple;
1062 if (rscreen->family <= CHIP_ARUBA) {
1063 triple = "r600--";
1064 } else {
1065 if (HAVE_LLVM < 0x0400) {
1066 triple = "amdgcn--";
1067 } else {
1068 triple = "amdgcn-mesa-mesa3d";
1069 }
1070 }
1071 switch(rscreen->family) {
1072 /* Clang < 3.6 is missing Hainan in its list of
1073 * GPUs, so we need to use the name of a similar GPU.
1074 */
1075 default:
1076 gpu = r600_get_llvm_processor_name(rscreen->family);
1077 break;
1078 }
1079 if (ret) {
1080 sprintf(ret, "%s-%s", gpu, triple);
1081 }
1082 /* +2 for dash and terminating NIL byte */
1083 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1084 }
1085 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1086 if (ret) {
1087 uint64_t *grid_dimension = ret;
1088 grid_dimension[0] = 3;
1089 }
1090 return 1 * sizeof(uint64_t);
1091
1092 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1093 if (ret) {
1094 uint64_t *grid_size = ret;
1095 grid_size[0] = 65535;
1096 grid_size[1] = 65535;
1097 grid_size[2] = 65535;
1098 }
1099 return 3 * sizeof(uint64_t) ;
1100
1101 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1102 if (ret) {
1103 uint64_t *block_size = ret;
1104 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1105 block_size[0] = threads_per_block;
1106 block_size[1] = threads_per_block;
1107 block_size[2] = threads_per_block;
1108 }
1109 return 3 * sizeof(uint64_t);
1110
1111 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1112 if (ret) {
1113 uint64_t *max_threads_per_block = ret;
1114 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1115 }
1116 return sizeof(uint64_t);
1117 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1118 if (ret) {
1119 uint32_t *address_bits = ret;
1120 address_bits[0] = 32;
1121 if (rscreen->chip_class >= SI)
1122 address_bits[0] = 64;
1123 }
1124 return 1 * sizeof(uint32_t);
1125
1126 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1127 if (ret) {
1128 uint64_t *max_global_size = ret;
1129 uint64_t max_mem_alloc_size;
1130
1131 r600_get_compute_param(screen, ir_type,
1132 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1133 &max_mem_alloc_size);
1134
1135 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1136 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1137 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1138 * make sure we never report more than
1139 * 4 * MAX_MEM_ALLOC_SIZE.
1140 */
1141 *max_global_size = MIN2(4 * max_mem_alloc_size,
1142 MAX2(rscreen->info.gart_size,
1143 rscreen->info.vram_size));
1144 }
1145 return sizeof(uint64_t);
1146
1147 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1148 if (ret) {
1149 uint64_t *max_local_size = ret;
1150 /* Value reported by the closed source driver. */
1151 *max_local_size = 32768;
1152 }
1153 return sizeof(uint64_t);
1154
1155 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1156 if (ret) {
1157 uint64_t *max_input_size = ret;
1158 /* Value reported by the closed source driver. */
1159 *max_input_size = 1024;
1160 }
1161 return sizeof(uint64_t);
1162
1163 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1164 if (ret) {
1165 uint64_t *max_mem_alloc_size = ret;
1166
1167 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1168 }
1169 return sizeof(uint64_t);
1170
1171 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1172 if (ret) {
1173 uint32_t *max_clock_frequency = ret;
1174 *max_clock_frequency = rscreen->info.max_shader_clock;
1175 }
1176 return sizeof(uint32_t);
1177
1178 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1179 if (ret) {
1180 uint32_t *max_compute_units = ret;
1181 *max_compute_units = rscreen->info.num_good_compute_units;
1182 }
1183 return sizeof(uint32_t);
1184
1185 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1186 if (ret) {
1187 uint32_t *images_supported = ret;
1188 *images_supported = 0;
1189 }
1190 return sizeof(uint32_t);
1191 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1192 break; /* unused */
1193 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1194 if (ret) {
1195 uint32_t *subgroup_size = ret;
1196 *subgroup_size = r600_wavefront_size(rscreen->family);
1197 }
1198 return sizeof(uint32_t);
1199 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1200 if (ret) {
1201 uint64_t *max_variable_threads_per_block = ret;
1202 if (rscreen->chip_class >= SI &&
1203 ir_type == PIPE_SHADER_IR_TGSI)
1204 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1205 else
1206 *max_variable_threads_per_block = 0;
1207 }
1208 return sizeof(uint64_t);
1209 }
1210
1211 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1212 return 0;
1213 }
1214
1215 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1216 {
1217 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1218
1219 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1220 rscreen->info.clock_crystal_freq;
1221 }
1222
1223 static void r600_fence_reference(struct pipe_screen *screen,
1224 struct pipe_fence_handle **dst,
1225 struct pipe_fence_handle *src)
1226 {
1227 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1228 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1229 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1230
1231 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1232 ws->fence_reference(&(*rdst)->gfx, NULL);
1233 ws->fence_reference(&(*rdst)->sdma, NULL);
1234 FREE(*rdst);
1235 }
1236 *rdst = rsrc;
1237 }
1238
1239 static boolean r600_fence_finish(struct pipe_screen *screen,
1240 struct pipe_context *ctx,
1241 struct pipe_fence_handle *fence,
1242 uint64_t timeout)
1243 {
1244 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1245 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1246 struct r600_common_context *rctx;
1247 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1248
1249 ctx = threaded_context_unwrap_sync(ctx);
1250 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1251
1252 if (rfence->sdma) {
1253 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1254 return false;
1255
1256 /* Recompute the timeout after waiting. */
1257 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1258 int64_t time = os_time_get_nano();
1259 timeout = abs_timeout > time ? abs_timeout - time : 0;
1260 }
1261 }
1262
1263 if (!rfence->gfx)
1264 return true;
1265
1266 /* Flush the gfx IB if it hasn't been flushed yet. */
1267 if (rctx &&
1268 rfence->gfx_unflushed.ctx == rctx &&
1269 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1270 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1271 rfence->gfx_unflushed.ctx = NULL;
1272
1273 if (!timeout)
1274 return false;
1275
1276 /* Recompute the timeout after all that. */
1277 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1278 int64_t time = os_time_get_nano();
1279 timeout = abs_timeout > time ? abs_timeout - time : 0;
1280 }
1281 }
1282
1283 return rws->fence_wait(rws, rfence->gfx, timeout);
1284 }
1285
1286 static void r600_query_memory_info(struct pipe_screen *screen,
1287 struct pipe_memory_info *info)
1288 {
1289 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1290 struct radeon_winsys *ws = rscreen->ws;
1291 unsigned vram_usage, gtt_usage;
1292
1293 info->total_device_memory = rscreen->info.vram_size / 1024;
1294 info->total_staging_memory = rscreen->info.gart_size / 1024;
1295
1296 /* The real TTM memory usage is somewhat random, because:
1297 *
1298 * 1) TTM delays freeing memory, because it can only free it after
1299 * fences expire.
1300 *
1301 * 2) The memory usage can be really low if big VRAM evictions are
1302 * taking place, but the real usage is well above the size of VRAM.
1303 *
1304 * Instead, return statistics of this process.
1305 */
1306 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1307 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1308
1309 info->avail_device_memory =
1310 vram_usage <= info->total_device_memory ?
1311 info->total_device_memory - vram_usage : 0;
1312 info->avail_staging_memory =
1313 gtt_usage <= info->total_staging_memory ?
1314 info->total_staging_memory - gtt_usage : 0;
1315
1316 info->device_memory_evicted =
1317 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1318
1319 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1320 info->nr_device_memory_evictions =
1321 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1322 else
1323 /* Just return the number of evicted 64KB pages. */
1324 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1325 }
1326
1327 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1328 const struct pipe_resource *templ)
1329 {
1330 if (templ->target == PIPE_BUFFER) {
1331 return r600_buffer_create(screen, templ, 256);
1332 } else {
1333 return r600_texture_create(screen, templ);
1334 }
1335 }
1336
1337 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1338 struct radeon_winsys *ws)
1339 {
1340 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1341 struct utsname uname_data;
1342 const char *chip_name;
1343
1344 ws->query_info(ws, &rscreen->info);
1345 rscreen->ws = ws;
1346
1347 if ((chip_name = r600_get_marketing_name(ws)))
1348 snprintf(family_name, sizeof(family_name), "%s / ",
1349 r600_get_family_name(rscreen) + 4);
1350 else
1351 chip_name = r600_get_family_name(rscreen);
1352
1353 if (uname(&uname_data) == 0)
1354 snprintf(kernel_version, sizeof(kernel_version),
1355 " / %s", uname_data.release);
1356
1357 if (HAVE_LLVM > 0) {
1358 snprintf(llvm_string, sizeof(llvm_string),
1359 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1360 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1361 }
1362
1363 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1364 "%s (%sDRM %i.%i.%i%s%s)",
1365 chip_name, family_name, rscreen->info.drm_major,
1366 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1367 kernel_version, llvm_string);
1368
1369 rscreen->b.get_name = r600_get_name;
1370 rscreen->b.get_vendor = r600_get_vendor;
1371 rscreen->b.get_device_vendor = r600_get_device_vendor;
1372 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1373 rscreen->b.get_compute_param = r600_get_compute_param;
1374 rscreen->b.get_paramf = r600_get_paramf;
1375 rscreen->b.get_timestamp = r600_get_timestamp;
1376 rscreen->b.fence_finish = r600_fence_finish;
1377 rscreen->b.fence_reference = r600_fence_reference;
1378 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1379 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1380 rscreen->b.query_memory_info = r600_query_memory_info;
1381
1382 if (rscreen->info.has_hw_decode) {
1383 rscreen->b.get_video_param = rvid_get_video_param;
1384 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1385 } else {
1386 rscreen->b.get_video_param = r600_get_video_param;
1387 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1388 }
1389
1390 r600_init_screen_texture_functions(rscreen);
1391 r600_init_screen_query_functions(rscreen);
1392
1393 rscreen->family = rscreen->info.family;
1394 rscreen->chip_class = rscreen->info.chip_class;
1395 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1396 rscreen->has_rbplus = false;
1397 rscreen->rbplus_allowed = false;
1398
1399 r600_disk_cache_create(rscreen);
1400
1401 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1402
1403 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1404 if (rscreen->force_aniso >= 0) {
1405 printf("radeon: Forcing anisotropy filter to %ix\n",
1406 /* round down to a power of two */
1407 1 << util_logbase2(rscreen->force_aniso));
1408 }
1409
1410 util_format_s3tc_init();
1411 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1412 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1413
1414 if (rscreen->debug_flags & DBG_INFO) {
1415 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1416 rscreen->info.pci_domain, rscreen->info.pci_bus,
1417 rscreen->info.pci_dev, rscreen->info.pci_func);
1418 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1419 printf("family = %i (%s)\n", rscreen->info.family,
1420 r600_get_family_name(rscreen));
1421 printf("chip_class = %i\n", rscreen->info.chip_class);
1422 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1423 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1424 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1425 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1426 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1427 printf("max_alloc_size = %i MB\n",
1428 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1429 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1430 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1431 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1432 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1433 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1434 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1435 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1436 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1437 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1438 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1439 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1440 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1441 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1442 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1443 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1444 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1445 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1446 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1447 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1448
1449 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1450 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1451 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1452 printf("max_se = %i\n", rscreen->info.max_se);
1453 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1454
1455 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1456 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1457 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1458 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1459 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1460 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1461 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1462 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1463 }
1464 return true;
1465 }
1466
1467 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1468 {
1469 r600_perfcounters_destroy(rscreen);
1470 r600_gpu_load_kill_thread(rscreen);
1471
1472 mtx_destroy(&rscreen->gpu_load_mutex);
1473 mtx_destroy(&rscreen->aux_context_lock);
1474 rscreen->aux_context->destroy(rscreen->aux_context);
1475
1476 slab_destroy_parent(&rscreen->pool_transfers);
1477
1478 disk_cache_destroy(rscreen->disk_shader_cache);
1479 rscreen->ws->destroy(rscreen->ws);
1480 FREE(rscreen);
1481 }
1482
1483 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1484 unsigned processor)
1485 {
1486 switch (processor) {
1487 case PIPE_SHADER_VERTEX:
1488 return (rscreen->debug_flags & DBG_VS) != 0;
1489 case PIPE_SHADER_TESS_CTRL:
1490 return (rscreen->debug_flags & DBG_TCS) != 0;
1491 case PIPE_SHADER_TESS_EVAL:
1492 return (rscreen->debug_flags & DBG_TES) != 0;
1493 case PIPE_SHADER_GEOMETRY:
1494 return (rscreen->debug_flags & DBG_GS) != 0;
1495 case PIPE_SHADER_FRAGMENT:
1496 return (rscreen->debug_flags & DBG_PS) != 0;
1497 case PIPE_SHADER_COMPUTE:
1498 return (rscreen->debug_flags & DBG_CS) != 0;
1499 default:
1500 return false;
1501 }
1502 }
1503
1504 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1505 {
1506 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1507 r600_can_dump_shader(rscreen, processor);
1508 }
1509
1510 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1511 uint64_t offset, uint64_t size, unsigned value)
1512 {
1513 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1514
1515 mtx_lock(&rscreen->aux_context_lock);
1516 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1517 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1518 mtx_unlock(&rscreen->aux_context_lock);
1519 }