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Merge ../mesa into vulkan
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40
41 #ifndef HAVE_LLVM
42 #define HAVE_LLVM 0
43 #endif
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49 };
50
51 /*
52 * pipe_context
53 */
54
55 void r600_draw_rectangle(struct blitter_context *blitter,
56 int x1, int y1, int x2, int y2, float depth,
57 enum blitter_attrib_type type,
58 const union pipe_color_union *attrib)
59 {
60 struct r600_common_context *rctx =
61 (struct r600_common_context*)util_blitter_get_pipe(blitter);
62 struct pipe_viewport_state viewport;
63 struct pipe_resource *buf = NULL;
64 unsigned offset = 0;
65 float *vb;
66
67 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
68 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
69 return;
70 }
71
72 /* Some operations (like color resolve on r6xx) don't work
73 * with the conventional primitive types.
74 * One that works is PT_RECTLIST, which we use here. */
75
76 /* setup viewport */
77 viewport.scale[0] = 1.0f;
78 viewport.scale[1] = 1.0f;
79 viewport.scale[2] = 1.0f;
80 viewport.translate[0] = 0.0f;
81 viewport.translate[1] = 0.0f;
82 viewport.translate[2] = 0.0f;
83 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
84
85 /* Upload vertices. The hw rectangle has only 3 vertices,
86 * I guess the 4th one is derived from the first 3.
87 * The vertex specification should match u_blitter's vertex element state. */
88 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
89 if (!buf)
90 return;
91
92 vb[0] = x1;
93 vb[1] = y1;
94 vb[2] = depth;
95 vb[3] = 1;
96
97 vb[8] = x1;
98 vb[9] = y2;
99 vb[10] = depth;
100 vb[11] = 1;
101
102 vb[16] = x2;
103 vb[17] = y1;
104 vb[18] = depth;
105 vb[19] = 1;
106
107 if (attrib) {
108 memcpy(vb+4, attrib->f, sizeof(float)*4);
109 memcpy(vb+12, attrib->f, sizeof(float)*4);
110 memcpy(vb+20, attrib->f, sizeof(float)*4);
111 }
112
113 /* draw */
114 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
115 R600_PRIM_RECTANGLE_LIST, 3, 2);
116 pipe_resource_reference(&buf, NULL);
117 }
118
119 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
120 {
121 /* Flush the GFX IB if it's not empty. */
122 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
123 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
124
125 /* Flush if there's not enough space. */
126 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
127 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
128 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
129 }
130 }
131
132 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
133 {
134 }
135
136 void r600_preflush_suspend_features(struct r600_common_context *ctx)
137 {
138 /* suspend queries */
139 if (ctx->num_cs_dw_nontimer_queries_suspend) {
140 /* Since non-timer queries are suspended during blits,
141 * we have to guard against double-suspends. */
142 r600_suspend_nontimer_queries(ctx);
143 ctx->nontimer_queries_suspended_by_flush = true;
144 }
145 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
146 r600_suspend_timer_queries(ctx);
147
148 ctx->streamout.suspended = false;
149 if (ctx->streamout.begin_emitted) {
150 r600_emit_streamout_end(ctx);
151 ctx->streamout.suspended = true;
152 }
153 }
154
155 void r600_postflush_resume_features(struct r600_common_context *ctx)
156 {
157 if (ctx->streamout.suspended) {
158 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
159 r600_streamout_buffers_dirty(ctx);
160 }
161
162 /* resume queries */
163 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
164 r600_resume_timer_queries(ctx);
165 if (ctx->nontimer_queries_suspended_by_flush) {
166 ctx->nontimer_queries_suspended_by_flush = false;
167 r600_resume_nontimer_queries(ctx);
168 }
169 }
170
171 static void r600_flush_from_st(struct pipe_context *ctx,
172 struct pipe_fence_handle **fence,
173 unsigned flags)
174 {
175 struct pipe_screen *screen = ctx->screen;
176 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
177 unsigned rflags = 0;
178 struct pipe_fence_handle *gfx_fence = NULL;
179 struct pipe_fence_handle *sdma_fence = NULL;
180
181 if (flags & PIPE_FLUSH_END_OF_FRAME)
182 rflags |= RADEON_FLUSH_END_OF_FRAME;
183
184 if (rctx->dma.cs) {
185 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
186 }
187 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
188
189 /* Both engines can signal out of order, so we need to keep both fences. */
190 if (gfx_fence || sdma_fence) {
191 struct r600_multi_fence *multi_fence =
192 CALLOC_STRUCT(r600_multi_fence);
193 if (!multi_fence)
194 return;
195
196 multi_fence->reference.count = 1;
197 multi_fence->gfx = gfx_fence;
198 multi_fence->sdma = sdma_fence;
199
200 screen->fence_reference(screen, fence, NULL);
201 *fence = (struct pipe_fence_handle*)multi_fence;
202 }
203 }
204
205 static void r600_flush_dma_ring(void *ctx, unsigned flags,
206 struct pipe_fence_handle **fence)
207 {
208 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
209 struct radeon_winsys_cs *cs = rctx->dma.cs;
210
211 if (cs->cdw)
212 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
213 if (fence)
214 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
215 }
216
217 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
218 {
219 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
220 unsigned latest = rctx->ws->query_value(rctx->ws,
221 RADEON_GPU_RESET_COUNTER);
222
223 if (rctx->gpu_reset_counter == latest)
224 return PIPE_NO_RESET;
225
226 rctx->gpu_reset_counter = latest;
227 return PIPE_UNKNOWN_CONTEXT_RESET;
228 }
229
230 bool r600_common_context_init(struct r600_common_context *rctx,
231 struct r600_common_screen *rscreen)
232 {
233 util_slab_create(&rctx->pool_transfers,
234 sizeof(struct r600_transfer), 64,
235 UTIL_SLAB_SINGLETHREADED);
236
237 rctx->screen = rscreen;
238 rctx->ws = rscreen->ws;
239 rctx->family = rscreen->family;
240 rctx->chip_class = rscreen->chip_class;
241
242 if (rscreen->chip_class >= CIK)
243 rctx->max_db = MAX2(8, rscreen->info.r600_num_backends);
244 else if (rscreen->chip_class >= EVERGREEN)
245 rctx->max_db = 8;
246 else
247 rctx->max_db = 4;
248
249 rctx->b.transfer_map = u_transfer_map_vtbl;
250 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
251 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
252 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
253 rctx->b.memory_barrier = r600_memory_barrier;
254 rctx->b.flush = r600_flush_from_st;
255
256 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
257 rctx->b.get_device_reset_status = r600_get_reset_status;
258 rctx->gpu_reset_counter =
259 rctx->ws->query_value(rctx->ws,
260 RADEON_GPU_RESET_COUNTER);
261 }
262
263 LIST_INITHEAD(&rctx->texture_buffers);
264
265 r600_init_context_texture_functions(rctx);
266 r600_streamout_init(rctx);
267 r600_query_init(rctx);
268 cayman_init_msaa(&rctx->b);
269
270 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
271 0, PIPE_USAGE_DEFAULT, TRUE);
272 if (!rctx->allocator_so_filled_size)
273 return false;
274
275 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
276 PIPE_BIND_INDEX_BUFFER |
277 PIPE_BIND_CONSTANT_BUFFER);
278 if (!rctx->uploader)
279 return false;
280
281 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
282 if (!rctx->ctx)
283 return false;
284
285 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
286 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
287 r600_flush_dma_ring,
288 rctx, NULL);
289 rctx->dma.flush = r600_flush_dma_ring;
290 }
291
292 return true;
293 }
294
295 void r600_common_context_cleanup(struct r600_common_context *rctx)
296 {
297 if (rctx->gfx.cs)
298 rctx->ws->cs_destroy(rctx->gfx.cs);
299 if (rctx->dma.cs)
300 rctx->ws->cs_destroy(rctx->dma.cs);
301 if (rctx->ctx)
302 rctx->ws->ctx_destroy(rctx->ctx);
303
304 if (rctx->uploader) {
305 u_upload_destroy(rctx->uploader);
306 }
307
308 util_slab_destroy(&rctx->pool_transfers);
309
310 if (rctx->allocator_so_filled_size) {
311 u_suballocator_destroy(rctx->allocator_so_filled_size);
312 }
313 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
314 }
315
316 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
317 {
318 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
319 struct r600_resource *rr = (struct r600_resource *)r;
320
321 if (!r) {
322 return;
323 }
324
325 /*
326 * The idea is to compute a gross estimate of memory requirement of
327 * each draw call. After each draw call, memory will be precisely
328 * accounted. So the uncertainty is only on the current draw call.
329 * In practice this gave very good estimate (+/- 10% of the target
330 * memory limit).
331 */
332 if (rr->domains & RADEON_DOMAIN_GTT) {
333 rctx->gtt += rr->buf->size;
334 }
335 if (rr->domains & RADEON_DOMAIN_VRAM) {
336 rctx->vram += rr->buf->size;
337 }
338 }
339
340 /*
341 * pipe_screen
342 */
343
344 static const struct debug_named_value common_debug_options[] = {
345 /* logging */
346 { "tex", DBG_TEX, "Print texture info" },
347 { "compute", DBG_COMPUTE, "Print compute info" },
348 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
349 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
350 { "info", DBG_INFO, "Print driver information" },
351
352 /* shaders */
353 { "fs", DBG_FS, "Print fetch shaders" },
354 { "vs", DBG_VS, "Print vertex shaders" },
355 { "gs", DBG_GS, "Print geometry shaders" },
356 { "ps", DBG_PS, "Print pixel shaders" },
357 { "cs", DBG_CS, "Print compute shaders" },
358 { "tcs", DBG_TCS, "Print tessellation control shaders" },
359 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
360 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
361 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
362 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
363
364 /* features */
365 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
366 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
367 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
368 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
369 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
370 { "notiling", DBG_NO_TILING, "Disable tiling" },
371 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
372 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
373 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
374 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
375 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
376 { "nodcc", DBG_NO_DCC, "Disable DCC." },
377 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
378 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
379
380 DEBUG_NAMED_VALUE_END /* must be last */
381 };
382
383 static const char* r600_get_vendor(struct pipe_screen* pscreen)
384 {
385 return "X.Org";
386 }
387
388 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
389 {
390 return "AMD";
391 }
392
393 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
394 {
395 switch (rscreen->info.family) {
396 case CHIP_R600: return "AMD R600";
397 case CHIP_RV610: return "AMD RV610";
398 case CHIP_RV630: return "AMD RV630";
399 case CHIP_RV670: return "AMD RV670";
400 case CHIP_RV620: return "AMD RV620";
401 case CHIP_RV635: return "AMD RV635";
402 case CHIP_RS780: return "AMD RS780";
403 case CHIP_RS880: return "AMD RS880";
404 case CHIP_RV770: return "AMD RV770";
405 case CHIP_RV730: return "AMD RV730";
406 case CHIP_RV710: return "AMD RV710";
407 case CHIP_RV740: return "AMD RV740";
408 case CHIP_CEDAR: return "AMD CEDAR";
409 case CHIP_REDWOOD: return "AMD REDWOOD";
410 case CHIP_JUNIPER: return "AMD JUNIPER";
411 case CHIP_CYPRESS: return "AMD CYPRESS";
412 case CHIP_HEMLOCK: return "AMD HEMLOCK";
413 case CHIP_PALM: return "AMD PALM";
414 case CHIP_SUMO: return "AMD SUMO";
415 case CHIP_SUMO2: return "AMD SUMO2";
416 case CHIP_BARTS: return "AMD BARTS";
417 case CHIP_TURKS: return "AMD TURKS";
418 case CHIP_CAICOS: return "AMD CAICOS";
419 case CHIP_CAYMAN: return "AMD CAYMAN";
420 case CHIP_ARUBA: return "AMD ARUBA";
421 case CHIP_TAHITI: return "AMD TAHITI";
422 case CHIP_PITCAIRN: return "AMD PITCAIRN";
423 case CHIP_VERDE: return "AMD CAPE VERDE";
424 case CHIP_OLAND: return "AMD OLAND";
425 case CHIP_HAINAN: return "AMD HAINAN";
426 case CHIP_BONAIRE: return "AMD BONAIRE";
427 case CHIP_KAVERI: return "AMD KAVERI";
428 case CHIP_KABINI: return "AMD KABINI";
429 case CHIP_HAWAII: return "AMD HAWAII";
430 case CHIP_MULLINS: return "AMD MULLINS";
431 case CHIP_TONGA: return "AMD TONGA";
432 case CHIP_ICELAND: return "AMD ICELAND";
433 case CHIP_CARRIZO: return "AMD CARRIZO";
434 case CHIP_FIJI: return "AMD FIJI";
435 case CHIP_STONEY: return "AMD STONEY";
436 default: return "AMD unknown";
437 }
438 }
439
440 static const char* r600_get_name(struct pipe_screen* pscreen)
441 {
442 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
443
444 return rscreen->renderer_string;
445 }
446
447 static float r600_get_paramf(struct pipe_screen* pscreen,
448 enum pipe_capf param)
449 {
450 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
451
452 switch (param) {
453 case PIPE_CAPF_MAX_LINE_WIDTH:
454 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
455 case PIPE_CAPF_MAX_POINT_WIDTH:
456 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
457 if (rscreen->family >= CHIP_CEDAR)
458 return 16384.0f;
459 else
460 return 8192.0f;
461 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
462 return 16.0f;
463 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
464 return 16.0f;
465 case PIPE_CAPF_GUARD_BAND_LEFT:
466 case PIPE_CAPF_GUARD_BAND_TOP:
467 case PIPE_CAPF_GUARD_BAND_RIGHT:
468 case PIPE_CAPF_GUARD_BAND_BOTTOM:
469 return 0.0f;
470 }
471 return 0.0f;
472 }
473
474 static int r600_get_video_param(struct pipe_screen *screen,
475 enum pipe_video_profile profile,
476 enum pipe_video_entrypoint entrypoint,
477 enum pipe_video_cap param)
478 {
479 switch (param) {
480 case PIPE_VIDEO_CAP_SUPPORTED:
481 return vl_profile_supported(screen, profile, entrypoint);
482 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
483 return 1;
484 case PIPE_VIDEO_CAP_MAX_WIDTH:
485 case PIPE_VIDEO_CAP_MAX_HEIGHT:
486 return vl_video_buffer_max_size(screen);
487 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
488 return PIPE_FORMAT_NV12;
489 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
490 return false;
491 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
492 return false;
493 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
494 return true;
495 case PIPE_VIDEO_CAP_MAX_LEVEL:
496 return vl_level_supported(screen, profile);
497 default:
498 return 0;
499 }
500 }
501
502 const char *r600_get_llvm_processor_name(enum radeon_family family)
503 {
504 switch (family) {
505 case CHIP_R600:
506 case CHIP_RV630:
507 case CHIP_RV635:
508 case CHIP_RV670:
509 return "r600";
510 case CHIP_RV610:
511 case CHIP_RV620:
512 case CHIP_RS780:
513 case CHIP_RS880:
514 return "rs880";
515 case CHIP_RV710:
516 return "rv710";
517 case CHIP_RV730:
518 return "rv730";
519 case CHIP_RV740:
520 case CHIP_RV770:
521 return "rv770";
522 case CHIP_PALM:
523 case CHIP_CEDAR:
524 return "cedar";
525 case CHIP_SUMO:
526 case CHIP_SUMO2:
527 return "sumo";
528 case CHIP_REDWOOD:
529 return "redwood";
530 case CHIP_JUNIPER:
531 return "juniper";
532 case CHIP_HEMLOCK:
533 case CHIP_CYPRESS:
534 return "cypress";
535 case CHIP_BARTS:
536 return "barts";
537 case CHIP_TURKS:
538 return "turks";
539 case CHIP_CAICOS:
540 return "caicos";
541 case CHIP_CAYMAN:
542 case CHIP_ARUBA:
543 return "cayman";
544
545 case CHIP_TAHITI: return "tahiti";
546 case CHIP_PITCAIRN: return "pitcairn";
547 case CHIP_VERDE: return "verde";
548 case CHIP_OLAND: return "oland";
549 case CHIP_HAINAN: return "hainan";
550 case CHIP_BONAIRE: return "bonaire";
551 case CHIP_KABINI: return "kabini";
552 case CHIP_KAVERI: return "kaveri";
553 case CHIP_HAWAII: return "hawaii";
554 case CHIP_MULLINS:
555 return "mullins";
556 case CHIP_TONGA: return "tonga";
557 case CHIP_ICELAND: return "iceland";
558 case CHIP_CARRIZO: return "carrizo";
559 #if HAVE_LLVM <= 0x0307
560 case CHIP_FIJI: return "tonga";
561 case CHIP_STONEY: return "carrizo";
562 #else
563 case CHIP_FIJI: return "fiji";
564 case CHIP_STONEY: return "stoney";
565 #endif
566 default: return "";
567 }
568 }
569
570 static int r600_get_compute_param(struct pipe_screen *screen,
571 enum pipe_compute_cap param,
572 void *ret)
573 {
574 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
575
576 //TODO: select these params by asic
577 switch (param) {
578 case PIPE_COMPUTE_CAP_IR_TARGET: {
579 const char *gpu;
580 const char *triple;
581 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
582 triple = "r600--";
583 } else {
584 triple = "amdgcn--";
585 }
586 switch(rscreen->family) {
587 /* Clang < 3.6 is missing Hainan in its list of
588 * GPUs, so we need to use the name of a similar GPU.
589 */
590 #if HAVE_LLVM < 0x0306
591 case CHIP_HAINAN:
592 gpu = "oland";
593 break;
594 #endif
595 default:
596 gpu = r600_get_llvm_processor_name(rscreen->family);
597 break;
598 }
599 if (ret) {
600 sprintf(ret, "%s-%s", gpu, triple);
601 }
602 /* +2 for dash and terminating NIL byte */
603 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
604 }
605 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
606 if (ret) {
607 uint64_t *grid_dimension = ret;
608 grid_dimension[0] = 3;
609 }
610 return 1 * sizeof(uint64_t);
611
612 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
613 if (ret) {
614 uint64_t *grid_size = ret;
615 grid_size[0] = 65535;
616 grid_size[1] = 65535;
617 grid_size[2] = 1;
618 }
619 return 3 * sizeof(uint64_t) ;
620
621 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
622 if (ret) {
623 uint64_t *block_size = ret;
624 block_size[0] = 256;
625 block_size[1] = 256;
626 block_size[2] = 256;
627 }
628 return 3 * sizeof(uint64_t);
629
630 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
631 if (ret) {
632 uint64_t *max_threads_per_block = ret;
633 *max_threads_per_block = 256;
634 }
635 return sizeof(uint64_t);
636
637 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
638 if (ret) {
639 uint64_t *max_global_size = ret;
640 uint64_t max_mem_alloc_size;
641
642 r600_get_compute_param(screen,
643 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
644 &max_mem_alloc_size);
645
646 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
647 * 1/4 of the MAX_GLOBAL_SIZE. Since the
648 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
649 * make sure we never report more than
650 * 4 * MAX_MEM_ALLOC_SIZE.
651 */
652 *max_global_size = MIN2(4 * max_mem_alloc_size,
653 rscreen->info.gart_size +
654 rscreen->info.vram_size);
655 }
656 return sizeof(uint64_t);
657
658 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
659 if (ret) {
660 uint64_t *max_local_size = ret;
661 /* Value reported by the closed source driver. */
662 *max_local_size = 32768;
663 }
664 return sizeof(uint64_t);
665
666 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
667 if (ret) {
668 uint64_t *max_input_size = ret;
669 /* Value reported by the closed source driver. */
670 *max_input_size = 1024;
671 }
672 return sizeof(uint64_t);
673
674 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
675 if (ret) {
676 uint64_t *max_mem_alloc_size = ret;
677
678 /* XXX: The limit in older kernels is 256 MB. We
679 * should add a query here for newer kernels.
680 */
681 *max_mem_alloc_size = 256 * 1024 * 1024;
682 }
683 return sizeof(uint64_t);
684
685 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
686 if (ret) {
687 uint32_t *max_clock_frequency = ret;
688 *max_clock_frequency = rscreen->info.max_sclk;
689 }
690 return sizeof(uint32_t);
691
692 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
693 if (ret) {
694 uint32_t *max_compute_units = ret;
695 *max_compute_units = rscreen->info.max_compute_units;
696 }
697 return sizeof(uint32_t);
698
699 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
700 if (ret) {
701 uint32_t *images_supported = ret;
702 *images_supported = 0;
703 }
704 return sizeof(uint32_t);
705 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
706 break; /* unused */
707 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
708 if (ret) {
709 uint32_t *subgroup_size = ret;
710 *subgroup_size = r600_wavefront_size(rscreen->family);
711 }
712 return sizeof(uint32_t);
713 }
714
715 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
716 return 0;
717 }
718
719 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
720 {
721 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
722
723 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
724 rscreen->info.r600_clock_crystal_freq;
725 }
726
727 static void r600_fence_reference(struct pipe_screen *screen,
728 struct pipe_fence_handle **dst,
729 struct pipe_fence_handle *src)
730 {
731 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
732 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
733 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
734
735 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
736 ws->fence_reference(&(*rdst)->gfx, NULL);
737 ws->fence_reference(&(*rdst)->sdma, NULL);
738 FREE(*rdst);
739 }
740 *rdst = rsrc;
741 }
742
743 static boolean r600_fence_finish(struct pipe_screen *screen,
744 struct pipe_fence_handle *fence,
745 uint64_t timeout)
746 {
747 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
748 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
749 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
750
751 if (rfence->sdma) {
752 if (!rws->fence_wait(rws, rfence->sdma, timeout))
753 return false;
754
755 /* Recompute the timeout after waiting. */
756 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
757 int64_t time = os_time_get_nano();
758 timeout = abs_timeout > time ? abs_timeout - time : 0;
759 }
760 }
761
762 if (!rfence->gfx)
763 return true;
764
765 return rws->fence_wait(rws, rfence->gfx, timeout);
766 }
767
768 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
769 uint32_t tiling_config)
770 {
771 switch ((tiling_config & 0xe) >> 1) {
772 case 0:
773 rscreen->tiling_info.num_channels = 1;
774 break;
775 case 1:
776 rscreen->tiling_info.num_channels = 2;
777 break;
778 case 2:
779 rscreen->tiling_info.num_channels = 4;
780 break;
781 case 3:
782 rscreen->tiling_info.num_channels = 8;
783 break;
784 default:
785 return false;
786 }
787
788 switch ((tiling_config & 0x30) >> 4) {
789 case 0:
790 rscreen->tiling_info.num_banks = 4;
791 break;
792 case 1:
793 rscreen->tiling_info.num_banks = 8;
794 break;
795 default:
796 return false;
797
798 }
799 switch ((tiling_config & 0xc0) >> 6) {
800 case 0:
801 rscreen->tiling_info.group_bytes = 256;
802 break;
803 case 1:
804 rscreen->tiling_info.group_bytes = 512;
805 break;
806 default:
807 return false;
808 }
809 return true;
810 }
811
812 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
813 uint32_t tiling_config)
814 {
815 switch (tiling_config & 0xf) {
816 case 0:
817 rscreen->tiling_info.num_channels = 1;
818 break;
819 case 1:
820 rscreen->tiling_info.num_channels = 2;
821 break;
822 case 2:
823 rscreen->tiling_info.num_channels = 4;
824 break;
825 case 3:
826 rscreen->tiling_info.num_channels = 8;
827 break;
828 default:
829 return false;
830 }
831
832 switch ((tiling_config & 0xf0) >> 4) {
833 case 0:
834 rscreen->tiling_info.num_banks = 4;
835 break;
836 case 1:
837 rscreen->tiling_info.num_banks = 8;
838 break;
839 case 2:
840 rscreen->tiling_info.num_banks = 16;
841 break;
842 default:
843 return false;
844 }
845
846 switch ((tiling_config & 0xf00) >> 8) {
847 case 0:
848 rscreen->tiling_info.group_bytes = 256;
849 break;
850 case 1:
851 rscreen->tiling_info.group_bytes = 512;
852 break;
853 default:
854 return false;
855 }
856 return true;
857 }
858
859 static bool r600_init_tiling(struct r600_common_screen *rscreen)
860 {
861 uint32_t tiling_config = rscreen->info.r600_tiling_config;
862
863 /* set default group bytes, overridden by tiling info ioctl */
864 if (rscreen->chip_class <= R700) {
865 rscreen->tiling_info.group_bytes = 256;
866 } else {
867 rscreen->tiling_info.group_bytes = 512;
868 }
869
870 if (!tiling_config)
871 return true;
872
873 if (rscreen->chip_class <= R700) {
874 return r600_interpret_tiling(rscreen, tiling_config);
875 } else {
876 return evergreen_interpret_tiling(rscreen, tiling_config);
877 }
878 }
879
880 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
881 const struct pipe_resource *templ)
882 {
883 if (templ->target == PIPE_BUFFER) {
884 return r600_buffer_create(screen, templ, 4096);
885 } else {
886 return r600_texture_create(screen, templ);
887 }
888 }
889
890 bool r600_common_screen_init(struct r600_common_screen *rscreen,
891 struct radeon_winsys *ws)
892 {
893 char llvm_string[32] = {};
894
895 ws->query_info(ws, &rscreen->info);
896
897 #if HAVE_LLVM
898 snprintf(llvm_string, sizeof(llvm_string),
899 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
900 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
901 #endif
902
903 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
904 "%s (DRM %i.%i.%i%s)",
905 r600_get_chip_name(rscreen), rscreen->info.drm_major,
906 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
907 llvm_string);
908
909 rscreen->b.get_name = r600_get_name;
910 rscreen->b.get_vendor = r600_get_vendor;
911 rscreen->b.get_device_vendor = r600_get_device_vendor;
912 rscreen->b.get_compute_param = r600_get_compute_param;
913 rscreen->b.get_paramf = r600_get_paramf;
914 rscreen->b.get_timestamp = r600_get_timestamp;
915 rscreen->b.fence_finish = r600_fence_finish;
916 rscreen->b.fence_reference = r600_fence_reference;
917 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
918 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
919
920 if (rscreen->info.has_uvd) {
921 rscreen->b.get_video_param = rvid_get_video_param;
922 rscreen->b.is_video_format_supported = rvid_is_format_supported;
923 } else {
924 rscreen->b.get_video_param = r600_get_video_param;
925 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
926 }
927
928 r600_init_screen_texture_functions(rscreen);
929 r600_init_screen_query_functions(rscreen);
930
931 rscreen->ws = ws;
932 rscreen->family = rscreen->info.family;
933 rscreen->chip_class = rscreen->info.chip_class;
934 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
935
936 if (!r600_init_tiling(rscreen)) {
937 return false;
938 }
939 util_format_s3tc_init();
940 pipe_mutex_init(rscreen->aux_context_lock);
941 pipe_mutex_init(rscreen->gpu_load_mutex);
942
943 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
944 rscreen->info.drm_major == 3) &&
945 (rscreen->debug_flags & DBG_TRACE_CS)) {
946 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
947 PIPE_BIND_CUSTOM,
948 PIPE_USAGE_STAGING,
949 4096);
950 if (rscreen->trace_bo) {
951 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->buf, NULL,
952 PIPE_TRANSFER_UNSYNCHRONIZED);
953 }
954 }
955
956 if (rscreen->debug_flags & DBG_INFO) {
957 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
958 printf("family = %i\n", rscreen->info.family);
959 printf("chip_class = %i\n", rscreen->info.chip_class);
960 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
961 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
962 printf("max_sclk = %i\n", rscreen->info.max_sclk);
963 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
964 printf("max_se = %i\n", rscreen->info.max_se);
965 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
966 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
967 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
968 printf("has_uvd = %i\n", rscreen->info.has_uvd);
969 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
970 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
971 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
972 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
973 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
974 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
975 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
976 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
977 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
978 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
979 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
980 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
981 }
982 return true;
983 }
984
985 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
986 {
987 r600_perfcounters_destroy(rscreen);
988 r600_gpu_load_kill_thread(rscreen);
989
990 pipe_mutex_destroy(rscreen->gpu_load_mutex);
991 pipe_mutex_destroy(rscreen->aux_context_lock);
992 rscreen->aux_context->destroy(rscreen->aux_context);
993
994 if (rscreen->trace_bo)
995 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
996
997 rscreen->ws->destroy(rscreen->ws);
998 FREE(rscreen);
999 }
1000
1001 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1002 const struct tgsi_token *tokens)
1003 {
1004 /* Compute shader don't have tgsi_tokens */
1005 if (!tokens)
1006 return (rscreen->debug_flags & DBG_CS) != 0;
1007
1008 switch (tgsi_get_processor_type(tokens)) {
1009 case TGSI_PROCESSOR_VERTEX:
1010 return (rscreen->debug_flags & DBG_VS) != 0;
1011 case TGSI_PROCESSOR_TESS_CTRL:
1012 return (rscreen->debug_flags & DBG_TCS) != 0;
1013 case TGSI_PROCESSOR_TESS_EVAL:
1014 return (rscreen->debug_flags & DBG_TES) != 0;
1015 case TGSI_PROCESSOR_GEOMETRY:
1016 return (rscreen->debug_flags & DBG_GS) != 0;
1017 case TGSI_PROCESSOR_FRAGMENT:
1018 return (rscreen->debug_flags & DBG_PS) != 0;
1019 case TGSI_PROCESSOR_COMPUTE:
1020 return (rscreen->debug_flags & DBG_CS) != 0;
1021 default:
1022 return false;
1023 }
1024 }
1025
1026 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1027 unsigned offset, unsigned size, unsigned value,
1028 bool is_framebuffer)
1029 {
1030 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1031
1032 pipe_mutex_lock(rscreen->aux_context_lock);
1033 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1034 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1035 pipe_mutex_unlock(rscreen->aux_context_lock);
1036 }