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gallium/radeon: remove the internal u_upload_mgr pointer
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #ifndef MESA_LLVM_VERSION_PATCH
47 #define MESA_LLVM_VERSION_PATCH 0
48 #endif
49
50 struct r600_multi_fence {
51 struct pipe_reference reference;
52 struct pipe_fence_handle *gfx;
53 struct pipe_fence_handle *sdma;
54
55 /* If the context wasn't flushed at fence creation, this is non-NULL. */
56 struct {
57 struct r600_common_context *ctx;
58 unsigned ib_index;
59 } gfx_unflushed;
60 };
61
62 /*
63 * shader binary helpers.
64 */
65 void radeon_shader_binary_init(struct radeon_shader_binary *b)
66 {
67 memset(b, 0, sizeof(*b));
68 }
69
70 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
71 {
72 if (!b)
73 return;
74 FREE(b->code);
75 FREE(b->config);
76 FREE(b->rodata);
77 FREE(b->global_symbol_offsets);
78 FREE(b->relocs);
79 FREE(b->disasm_string);
80 FREE(b->llvm_ir_string);
81 }
82
83 /*
84 * pipe_context
85 */
86
87 /**
88 * Write an EOP event.
89 *
90 * \param event EVENT_TYPE_*
91 * \param event_flags Optional cache flush flags (TC)
92 * \param data_sel 1 = fence, 3 = timestamp
93 * \param buf Buffer
94 * \param va GPU address
95 * \param old_value Previous fence value (for a bug workaround)
96 * \param new_value Fence value to write for this event.
97 */
98 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
99 unsigned event, unsigned event_flags,
100 unsigned data_sel,
101 struct r600_resource *buf, uint64_t va,
102 uint32_t old_fence, uint32_t new_fence)
103 {
104 struct radeon_winsys_cs *cs = ctx->gfx.cs;
105 unsigned op = EVENT_TYPE(event) |
106 EVENT_INDEX(5) |
107 event_flags;
108
109 if (ctx->chip_class == CIK ||
110 ctx->chip_class == VI) {
111 /* Two EOP events are required to make all engines go idle
112 * (and optional cache flushes executed) before the timestamp
113 * is written.
114 */
115 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
116 radeon_emit(cs, op);
117 radeon_emit(cs, va);
118 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
119 radeon_emit(cs, old_fence); /* immediate data */
120 radeon_emit(cs, 0); /* unused */
121 }
122
123 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
124 radeon_emit(cs, op);
125 radeon_emit(cs, va);
126 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
127 radeon_emit(cs, new_fence); /* immediate data */
128 radeon_emit(cs, 0); /* unused */
129
130 if (buf)
131 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
132 RADEON_PRIO_QUERY);
133 }
134
135 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
136 {
137 unsigned dwords = 6;
138
139 if (screen->chip_class == CIK ||
140 screen->chip_class == VI)
141 dwords *= 2;
142
143 if (!screen->info.has_virtual_memory)
144 dwords += 2;
145
146 return dwords;
147 }
148
149 void r600_gfx_wait_fence(struct r600_common_context *ctx,
150 uint64_t va, uint32_t ref, uint32_t mask)
151 {
152 struct radeon_winsys_cs *cs = ctx->gfx.cs;
153
154 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
155 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
156 radeon_emit(cs, va);
157 radeon_emit(cs, va >> 32);
158 radeon_emit(cs, ref); /* reference value */
159 radeon_emit(cs, mask); /* mask */
160 radeon_emit(cs, 4); /* poll interval */
161 }
162
163 void r600_draw_rectangle(struct blitter_context *blitter,
164 int x1, int y1, int x2, int y2, float depth,
165 enum blitter_attrib_type type,
166 const union pipe_color_union *attrib)
167 {
168 struct r600_common_context *rctx =
169 (struct r600_common_context*)util_blitter_get_pipe(blitter);
170 struct pipe_viewport_state viewport;
171 struct pipe_resource *buf = NULL;
172 unsigned offset = 0;
173 float *vb;
174
175 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
176 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
177 return;
178 }
179
180 /* Some operations (like color resolve on r6xx) don't work
181 * with the conventional primitive types.
182 * One that works is PT_RECTLIST, which we use here. */
183
184 /* setup viewport */
185 viewport.scale[0] = 1.0f;
186 viewport.scale[1] = 1.0f;
187 viewport.scale[2] = 1.0f;
188 viewport.translate[0] = 0.0f;
189 viewport.translate[1] = 0.0f;
190 viewport.translate[2] = 0.0f;
191 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
192
193 /* Upload vertices. The hw rectangle has only 3 vertices,
194 * I guess the 4th one is derived from the first 3.
195 * The vertex specification should match u_blitter's vertex element state. */
196 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24, 256,
197 &offset, &buf, (void**)&vb);
198 if (!buf)
199 return;
200
201 vb[0] = x1;
202 vb[1] = y1;
203 vb[2] = depth;
204 vb[3] = 1;
205
206 vb[8] = x1;
207 vb[9] = y2;
208 vb[10] = depth;
209 vb[11] = 1;
210
211 vb[16] = x2;
212 vb[17] = y1;
213 vb[18] = depth;
214 vb[19] = 1;
215
216 if (attrib) {
217 memcpy(vb+4, attrib->f, sizeof(float)*4);
218 memcpy(vb+12, attrib->f, sizeof(float)*4);
219 memcpy(vb+20, attrib->f, sizeof(float)*4);
220 }
221
222 /* draw */
223 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
224 R600_PRIM_RECTANGLE_LIST, 3, 2);
225 pipe_resource_reference(&buf, NULL);
226 }
227
228 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
229 {
230 struct radeon_winsys_cs *cs = rctx->dma.cs;
231
232 /* NOP waits for idle on Evergreen and later. */
233 if (rctx->chip_class >= CIK)
234 radeon_emit(cs, 0x00000000); /* NOP */
235 else if (rctx->chip_class >= EVERGREEN)
236 radeon_emit(cs, 0xf0000000); /* NOP */
237 else {
238 /* TODO: R600-R700 should use the FENCE packet.
239 * CS checker support is required. */
240 }
241 }
242
243 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
244 struct r600_resource *dst, struct r600_resource *src)
245 {
246 uint64_t vram = ctx->dma.cs->used_vram;
247 uint64_t gtt = ctx->dma.cs->used_gart;
248
249 if (dst) {
250 vram += dst->vram_usage;
251 gtt += dst->gart_usage;
252 }
253 if (src) {
254 vram += src->vram_usage;
255 gtt += src->gart_usage;
256 }
257
258 /* Flush the GFX IB if DMA depends on it. */
259 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
260 ((dst &&
261 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
262 RADEON_USAGE_READWRITE)) ||
263 (src &&
264 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
265 RADEON_USAGE_WRITE))))
266 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
267
268 /* Flush if there's not enough space, or if the memory usage per IB
269 * is too large.
270 *
271 * IBs using too little memory are limited by the IB submission overhead.
272 * IBs using too much memory are limited by the kernel/TTM overhead.
273 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
274 *
275 * This heuristic makes sure that DMA requests are executed
276 * very soon after the call is made and lowers memory usage.
277 * It improves texture upload performance by keeping the DMA
278 * engine busy while uploads are being submitted.
279 */
280 num_dw++; /* for emit_wait_idle below */
281 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
282 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
283 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
284 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
285 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
286 }
287
288 /* Wait for idle if either buffer has been used in the IB before to
289 * prevent read-after-write hazards.
290 */
291 if ((dst &&
292 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
293 RADEON_USAGE_READWRITE)) ||
294 (src &&
295 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
296 RADEON_USAGE_WRITE)))
297 r600_dma_emit_wait_idle(ctx);
298
299 /* If GPUVM is not supported, the CS checker needs 2 entries
300 * in the buffer list per packet, which has to be done manually.
301 */
302 if (ctx->screen->info.has_virtual_memory) {
303 if (dst)
304 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
305 RADEON_USAGE_WRITE,
306 RADEON_PRIO_SDMA_BUFFER);
307 if (src)
308 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
309 RADEON_USAGE_READ,
310 RADEON_PRIO_SDMA_BUFFER);
311 }
312
313 /* this function is called before all DMA calls, so increment this. */
314 ctx->num_dma_calls++;
315 }
316
317 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
318 {
319 }
320
321 void r600_preflush_suspend_features(struct r600_common_context *ctx)
322 {
323 /* suspend queries */
324 if (!LIST_IS_EMPTY(&ctx->active_queries))
325 r600_suspend_queries(ctx);
326
327 ctx->streamout.suspended = false;
328 if (ctx->streamout.begin_emitted) {
329 r600_emit_streamout_end(ctx);
330 ctx->streamout.suspended = true;
331 }
332 }
333
334 void r600_postflush_resume_features(struct r600_common_context *ctx)
335 {
336 if (ctx->streamout.suspended) {
337 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
338 r600_streamout_buffers_dirty(ctx);
339 }
340
341 /* resume queries */
342 if (!LIST_IS_EMPTY(&ctx->active_queries))
343 r600_resume_queries(ctx);
344 }
345
346 static void r600_flush_from_st(struct pipe_context *ctx,
347 struct pipe_fence_handle **fence,
348 unsigned flags)
349 {
350 struct pipe_screen *screen = ctx->screen;
351 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
352 struct radeon_winsys *ws = rctx->ws;
353 unsigned rflags = 0;
354 struct pipe_fence_handle *gfx_fence = NULL;
355 struct pipe_fence_handle *sdma_fence = NULL;
356 bool deferred_fence = false;
357
358 if (flags & PIPE_FLUSH_END_OF_FRAME)
359 rflags |= RADEON_FLUSH_END_OF_FRAME;
360 if (flags & PIPE_FLUSH_DEFERRED)
361 rflags |= RADEON_FLUSH_ASYNC;
362
363 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
364 if (rctx->dma.cs)
365 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
366
367 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
368 if (fence)
369 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
370 if (!(rflags & RADEON_FLUSH_ASYNC))
371 ws->cs_sync_flush(rctx->gfx.cs);
372 } else {
373 /* Instead of flushing, create a deferred fence. Constraints:
374 * - The state tracker must allow a deferred flush.
375 * - The state tracker must request a fence.
376 * Thread safety in fence_finish must be ensured by the state tracker.
377 */
378 if (flags & PIPE_FLUSH_DEFERRED && fence) {
379 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
380 deferred_fence = true;
381 } else {
382 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
383 }
384 }
385
386 /* Both engines can signal out of order, so we need to keep both fences. */
387 if (fence) {
388 struct r600_multi_fence *multi_fence =
389 CALLOC_STRUCT(r600_multi_fence);
390 if (!multi_fence)
391 return;
392
393 multi_fence->reference.count = 1;
394 /* If both fences are NULL, fence_finish will always return true. */
395 multi_fence->gfx = gfx_fence;
396 multi_fence->sdma = sdma_fence;
397
398 if (deferred_fence) {
399 multi_fence->gfx_unflushed.ctx = rctx;
400 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
401 }
402
403 screen->fence_reference(screen, fence, NULL);
404 *fence = (struct pipe_fence_handle*)multi_fence;
405 }
406 }
407
408 static void r600_flush_dma_ring(void *ctx, unsigned flags,
409 struct pipe_fence_handle **fence)
410 {
411 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
412 struct radeon_winsys_cs *cs = rctx->dma.cs;
413 struct radeon_saved_cs saved;
414 bool check_vm =
415 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
416 rctx->check_vm_faults;
417
418 if (!radeon_emitted(cs, 0)) {
419 if (fence)
420 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
421 return;
422 }
423
424 if (check_vm)
425 radeon_save_cs(rctx->ws, cs, &saved);
426
427 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
428 if (fence)
429 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
430
431 if (check_vm) {
432 /* Use conservative timeout 800ms, after which we won't wait any
433 * longer and assume the GPU is hung.
434 */
435 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
436
437 rctx->check_vm_faults(rctx, &saved, RING_DMA);
438 radeon_clear_saved_cs(&saved);
439 }
440 }
441
442 /**
443 * Store a linearized copy of all chunks of \p cs together with the buffer
444 * list in \p saved.
445 */
446 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
447 struct radeon_saved_cs *saved)
448 {
449 void *buf;
450 unsigned i;
451
452 /* Save the IB chunks. */
453 saved->num_dw = cs->prev_dw + cs->current.cdw;
454 saved->ib = MALLOC(4 * saved->num_dw);
455 if (!saved->ib)
456 goto oom;
457
458 buf = saved->ib;
459 for (i = 0; i < cs->num_prev; ++i) {
460 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
461 buf += cs->prev[i].cdw;
462 }
463 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
464
465 /* Save the buffer list. */
466 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
467 saved->bo_list = CALLOC(saved->bo_count,
468 sizeof(saved->bo_list[0]));
469 if (!saved->bo_list) {
470 FREE(saved->ib);
471 goto oom;
472 }
473 ws->cs_get_buffer_list(cs, saved->bo_list);
474
475 return;
476
477 oom:
478 fprintf(stderr, "%s: out of memory\n", __func__);
479 memset(saved, 0, sizeof(*saved));
480 }
481
482 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
483 {
484 FREE(saved->ib);
485 FREE(saved->bo_list);
486
487 memset(saved, 0, sizeof(*saved));
488 }
489
490 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
491 {
492 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
493 unsigned latest = rctx->ws->query_value(rctx->ws,
494 RADEON_GPU_RESET_COUNTER);
495
496 if (rctx->gpu_reset_counter == latest)
497 return PIPE_NO_RESET;
498
499 rctx->gpu_reset_counter = latest;
500 return PIPE_UNKNOWN_CONTEXT_RESET;
501 }
502
503 static void r600_set_debug_callback(struct pipe_context *ctx,
504 const struct pipe_debug_callback *cb)
505 {
506 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
507
508 if (cb)
509 rctx->debug = *cb;
510 else
511 memset(&rctx->debug, 0, sizeof(rctx->debug));
512 }
513
514 static void r600_set_device_reset_callback(struct pipe_context *ctx,
515 const struct pipe_device_reset_callback *cb)
516 {
517 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
518
519 if (cb)
520 rctx->device_reset_callback = *cb;
521 else
522 memset(&rctx->device_reset_callback, 0,
523 sizeof(rctx->device_reset_callback));
524 }
525
526 bool r600_check_device_reset(struct r600_common_context *rctx)
527 {
528 enum pipe_reset_status status;
529
530 if (!rctx->device_reset_callback.reset)
531 return false;
532
533 if (!rctx->b.get_device_reset_status)
534 return false;
535
536 status = rctx->b.get_device_reset_status(&rctx->b);
537 if (status == PIPE_NO_RESET)
538 return false;
539
540 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
541 return true;
542 }
543
544 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
545 struct pipe_resource *dst,
546 uint64_t offset, uint64_t size,
547 unsigned value)
548 {
549 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
550
551 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
552 }
553
554 bool r600_common_context_init(struct r600_common_context *rctx,
555 struct r600_common_screen *rscreen,
556 unsigned context_flags)
557 {
558 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
559
560 rctx->screen = rscreen;
561 rctx->ws = rscreen->ws;
562 rctx->family = rscreen->family;
563 rctx->chip_class = rscreen->chip_class;
564
565 rctx->b.invalidate_resource = r600_invalidate_resource;
566 rctx->b.transfer_map = u_transfer_map_vtbl;
567 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
568 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
569 rctx->b.texture_subdata = u_default_texture_subdata;
570 rctx->b.memory_barrier = r600_memory_barrier;
571 rctx->b.flush = r600_flush_from_st;
572 rctx->b.set_debug_callback = r600_set_debug_callback;
573 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
574
575 /* evergreen_compute.c has a special codepath for global buffers.
576 * Everything else can use the direct path.
577 */
578 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
579 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
580 rctx->b.buffer_subdata = u_default_buffer_subdata;
581 else
582 rctx->b.buffer_subdata = r600_buffer_subdata;
583
584 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
585 rctx->b.get_device_reset_status = r600_get_reset_status;
586 rctx->gpu_reset_counter =
587 rctx->ws->query_value(rctx->ws,
588 RADEON_GPU_RESET_COUNTER);
589 }
590
591 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
592
593 r600_init_context_texture_functions(rctx);
594 r600_init_viewport_functions(rctx);
595 r600_streamout_init(rctx);
596 r600_query_init(rctx);
597 cayman_init_msaa(&rctx->b);
598
599 rctx->allocator_zeroed_memory =
600 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
601 0, PIPE_USAGE_DEFAULT, true);
602 if (!rctx->allocator_zeroed_memory)
603 return false;
604
605 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
606 0, PIPE_USAGE_STREAM);
607 if (!rctx->b.stream_uploader)
608 return false;
609 rctx->b.const_uploader = rctx->b.stream_uploader;
610
611 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
612 if (!rctx->ctx)
613 return false;
614
615 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
616 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
617 r600_flush_dma_ring,
618 rctx);
619 rctx->dma.flush = r600_flush_dma_ring;
620 }
621
622 return true;
623 }
624
625 void r600_common_context_cleanup(struct r600_common_context *rctx)
626 {
627 unsigned i,j;
628
629 /* Release DCC stats. */
630 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
631 assert(!rctx->dcc_stats[i].query_active);
632
633 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
634 if (rctx->dcc_stats[i].ps_stats[j])
635 rctx->b.destroy_query(&rctx->b,
636 rctx->dcc_stats[i].ps_stats[j]);
637
638 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
639 }
640
641 if (rctx->query_result_shader)
642 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
643
644 if (rctx->gfx.cs)
645 rctx->ws->cs_destroy(rctx->gfx.cs);
646 if (rctx->dma.cs)
647 rctx->ws->cs_destroy(rctx->dma.cs);
648 if (rctx->ctx)
649 rctx->ws->ctx_destroy(rctx->ctx);
650
651 if (rctx->b.stream_uploader) {
652 u_upload_destroy(rctx->b.stream_uploader);
653 }
654
655 slab_destroy_child(&rctx->pool_transfers);
656
657 if (rctx->allocator_zeroed_memory) {
658 u_suballocator_destroy(rctx->allocator_zeroed_memory);
659 }
660 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
661 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
662 }
663
664 /*
665 * pipe_screen
666 */
667
668 static const struct debug_named_value common_debug_options[] = {
669 /* logging */
670 { "tex", DBG_TEX, "Print texture info" },
671 { "compute", DBG_COMPUTE, "Print compute info" },
672 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
673 { "info", DBG_INFO, "Print driver information" },
674
675 /* shaders */
676 { "fs", DBG_FS, "Print fetch shaders" },
677 { "vs", DBG_VS, "Print vertex shaders" },
678 { "gs", DBG_GS, "Print geometry shaders" },
679 { "ps", DBG_PS, "Print pixel shaders" },
680 { "cs", DBG_CS, "Print compute shaders" },
681 { "tcs", DBG_TCS, "Print tessellation control shaders" },
682 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
683 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
684 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
685 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
686 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
687 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
688 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
689
690 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
691
692 /* features */
693 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
694 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
695 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
696 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
697 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
698 { "notiling", DBG_NO_TILING, "Disable tiling" },
699 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
700 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
701 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
702 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
703 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
704 { "nodcc", DBG_NO_DCC, "Disable DCC." },
705 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
706 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
707 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
708 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
709 { "noce", DBG_NO_CE, "Disable the constant engine"},
710 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
711 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
712
713 DEBUG_NAMED_VALUE_END /* must be last */
714 };
715
716 static const char* r600_get_vendor(struct pipe_screen* pscreen)
717 {
718 return "X.Org";
719 }
720
721 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
722 {
723 return "AMD";
724 }
725
726 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
727 {
728 switch (rscreen->info.family) {
729 case CHIP_R600: return "AMD R600";
730 case CHIP_RV610: return "AMD RV610";
731 case CHIP_RV630: return "AMD RV630";
732 case CHIP_RV670: return "AMD RV670";
733 case CHIP_RV620: return "AMD RV620";
734 case CHIP_RV635: return "AMD RV635";
735 case CHIP_RS780: return "AMD RS780";
736 case CHIP_RS880: return "AMD RS880";
737 case CHIP_RV770: return "AMD RV770";
738 case CHIP_RV730: return "AMD RV730";
739 case CHIP_RV710: return "AMD RV710";
740 case CHIP_RV740: return "AMD RV740";
741 case CHIP_CEDAR: return "AMD CEDAR";
742 case CHIP_REDWOOD: return "AMD REDWOOD";
743 case CHIP_JUNIPER: return "AMD JUNIPER";
744 case CHIP_CYPRESS: return "AMD CYPRESS";
745 case CHIP_HEMLOCK: return "AMD HEMLOCK";
746 case CHIP_PALM: return "AMD PALM";
747 case CHIP_SUMO: return "AMD SUMO";
748 case CHIP_SUMO2: return "AMD SUMO2";
749 case CHIP_BARTS: return "AMD BARTS";
750 case CHIP_TURKS: return "AMD TURKS";
751 case CHIP_CAICOS: return "AMD CAICOS";
752 case CHIP_CAYMAN: return "AMD CAYMAN";
753 case CHIP_ARUBA: return "AMD ARUBA";
754 case CHIP_TAHITI: return "AMD TAHITI";
755 case CHIP_PITCAIRN: return "AMD PITCAIRN";
756 case CHIP_VERDE: return "AMD CAPE VERDE";
757 case CHIP_OLAND: return "AMD OLAND";
758 case CHIP_HAINAN: return "AMD HAINAN";
759 case CHIP_BONAIRE: return "AMD BONAIRE";
760 case CHIP_KAVERI: return "AMD KAVERI";
761 case CHIP_KABINI: return "AMD KABINI";
762 case CHIP_HAWAII: return "AMD HAWAII";
763 case CHIP_MULLINS: return "AMD MULLINS";
764 case CHIP_TONGA: return "AMD TONGA";
765 case CHIP_ICELAND: return "AMD ICELAND";
766 case CHIP_CARRIZO: return "AMD CARRIZO";
767 case CHIP_FIJI: return "AMD FIJI";
768 case CHIP_POLARIS10: return "AMD POLARIS10";
769 case CHIP_POLARIS11: return "AMD POLARIS11";
770 case CHIP_POLARIS12: return "AMD POLARIS12";
771 case CHIP_STONEY: return "AMD STONEY";
772 default: return "AMD unknown";
773 }
774 }
775
776 static const char* r600_get_name(struct pipe_screen* pscreen)
777 {
778 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
779
780 return rscreen->renderer_string;
781 }
782
783 static float r600_get_paramf(struct pipe_screen* pscreen,
784 enum pipe_capf param)
785 {
786 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
787
788 switch (param) {
789 case PIPE_CAPF_MAX_LINE_WIDTH:
790 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
791 case PIPE_CAPF_MAX_POINT_WIDTH:
792 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
793 if (rscreen->family >= CHIP_CEDAR)
794 return 16384.0f;
795 else
796 return 8192.0f;
797 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
798 return 16.0f;
799 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
800 return 16.0f;
801 case PIPE_CAPF_GUARD_BAND_LEFT:
802 case PIPE_CAPF_GUARD_BAND_TOP:
803 case PIPE_CAPF_GUARD_BAND_RIGHT:
804 case PIPE_CAPF_GUARD_BAND_BOTTOM:
805 return 0.0f;
806 }
807 return 0.0f;
808 }
809
810 static int r600_get_video_param(struct pipe_screen *screen,
811 enum pipe_video_profile profile,
812 enum pipe_video_entrypoint entrypoint,
813 enum pipe_video_cap param)
814 {
815 switch (param) {
816 case PIPE_VIDEO_CAP_SUPPORTED:
817 return vl_profile_supported(screen, profile, entrypoint);
818 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
819 return 1;
820 case PIPE_VIDEO_CAP_MAX_WIDTH:
821 case PIPE_VIDEO_CAP_MAX_HEIGHT:
822 return vl_video_buffer_max_size(screen);
823 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
824 return PIPE_FORMAT_NV12;
825 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
826 return false;
827 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
828 return false;
829 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
830 return true;
831 case PIPE_VIDEO_CAP_MAX_LEVEL:
832 return vl_level_supported(screen, profile);
833 default:
834 return 0;
835 }
836 }
837
838 const char *r600_get_llvm_processor_name(enum radeon_family family)
839 {
840 switch (family) {
841 case CHIP_R600:
842 case CHIP_RV630:
843 case CHIP_RV635:
844 case CHIP_RV670:
845 return "r600";
846 case CHIP_RV610:
847 case CHIP_RV620:
848 case CHIP_RS780:
849 case CHIP_RS880:
850 return "rs880";
851 case CHIP_RV710:
852 return "rv710";
853 case CHIP_RV730:
854 return "rv730";
855 case CHIP_RV740:
856 case CHIP_RV770:
857 return "rv770";
858 case CHIP_PALM:
859 case CHIP_CEDAR:
860 return "cedar";
861 case CHIP_SUMO:
862 case CHIP_SUMO2:
863 return "sumo";
864 case CHIP_REDWOOD:
865 return "redwood";
866 case CHIP_JUNIPER:
867 return "juniper";
868 case CHIP_HEMLOCK:
869 case CHIP_CYPRESS:
870 return "cypress";
871 case CHIP_BARTS:
872 return "barts";
873 case CHIP_TURKS:
874 return "turks";
875 case CHIP_CAICOS:
876 return "caicos";
877 case CHIP_CAYMAN:
878 case CHIP_ARUBA:
879 return "cayman";
880
881 case CHIP_TAHITI: return "tahiti";
882 case CHIP_PITCAIRN: return "pitcairn";
883 case CHIP_VERDE: return "verde";
884 case CHIP_OLAND: return "oland";
885 case CHIP_HAINAN: return "hainan";
886 case CHIP_BONAIRE: return "bonaire";
887 case CHIP_KABINI: return "kabini";
888 case CHIP_KAVERI: return "kaveri";
889 case CHIP_HAWAII: return "hawaii";
890 case CHIP_MULLINS:
891 return "mullins";
892 case CHIP_TONGA: return "tonga";
893 case CHIP_ICELAND: return "iceland";
894 case CHIP_CARRIZO: return "carrizo";
895 case CHIP_FIJI:
896 return HAVE_LLVM >= 0x0308 ? "fiji" : "carrizo";
897 case CHIP_STONEY:
898 return HAVE_LLVM >= 0x0308 ? "stoney" : "carrizo";
899 case CHIP_POLARIS10:
900 return HAVE_LLVM >= 0x0309 ? "polaris10" : "carrizo";
901 case CHIP_POLARIS11:
902 case CHIP_POLARIS12: /* same as polaris11 */
903 return HAVE_LLVM >= 0x0309 ? "polaris11" : "carrizo";
904 default:
905 return "";
906 }
907 }
908
909 static int r600_get_compute_param(struct pipe_screen *screen,
910 enum pipe_shader_ir ir_type,
911 enum pipe_compute_cap param,
912 void *ret)
913 {
914 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
915
916 //TODO: select these params by asic
917 switch (param) {
918 case PIPE_COMPUTE_CAP_IR_TARGET: {
919 const char *gpu;
920 const char *triple;
921 if (rscreen->family <= CHIP_ARUBA) {
922 triple = "r600--";
923 } else {
924 if (HAVE_LLVM < 0x0400) {
925 triple = "amdgcn--";
926 } else {
927 triple = "amdgcn-mesa-mesa3d";
928 }
929 }
930 switch(rscreen->family) {
931 /* Clang < 3.6 is missing Hainan in its list of
932 * GPUs, so we need to use the name of a similar GPU.
933 */
934 default:
935 gpu = r600_get_llvm_processor_name(rscreen->family);
936 break;
937 }
938 if (ret) {
939 sprintf(ret, "%s-%s", gpu, triple);
940 }
941 /* +2 for dash and terminating NIL byte */
942 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
943 }
944 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
945 if (ret) {
946 uint64_t *grid_dimension = ret;
947 grid_dimension[0] = 3;
948 }
949 return 1 * sizeof(uint64_t);
950
951 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
952 if (ret) {
953 uint64_t *grid_size = ret;
954 grid_size[0] = 65535;
955 grid_size[1] = 65535;
956 grid_size[2] = 65535;
957 }
958 return 3 * sizeof(uint64_t) ;
959
960 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
961 if (ret) {
962 uint64_t *block_size = ret;
963 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
964 ir_type == PIPE_SHADER_IR_TGSI) {
965 block_size[0] = 2048;
966 block_size[1] = 2048;
967 block_size[2] = 2048;
968 } else {
969 block_size[0] = 256;
970 block_size[1] = 256;
971 block_size[2] = 256;
972 }
973 }
974 return 3 * sizeof(uint64_t);
975
976 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
977 if (ret) {
978 uint64_t *max_threads_per_block = ret;
979 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
980 ir_type == PIPE_SHADER_IR_TGSI)
981 *max_threads_per_block = 2048;
982 else
983 *max_threads_per_block = 256;
984 }
985 return sizeof(uint64_t);
986 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
987 if (ret) {
988 uint32_t *address_bits = ret;
989 address_bits[0] = 32;
990 if (rscreen->chip_class >= SI)
991 address_bits[0] = 64;
992 }
993 return 1 * sizeof(uint32_t);
994
995 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
996 if (ret) {
997 uint64_t *max_global_size = ret;
998 uint64_t max_mem_alloc_size;
999
1000 r600_get_compute_param(screen, ir_type,
1001 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1002 &max_mem_alloc_size);
1003
1004 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1005 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1006 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1007 * make sure we never report more than
1008 * 4 * MAX_MEM_ALLOC_SIZE.
1009 */
1010 *max_global_size = MIN2(4 * max_mem_alloc_size,
1011 MAX2(rscreen->info.gart_size,
1012 rscreen->info.vram_size));
1013 }
1014 return sizeof(uint64_t);
1015
1016 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1017 if (ret) {
1018 uint64_t *max_local_size = ret;
1019 /* Value reported by the closed source driver. */
1020 *max_local_size = 32768;
1021 }
1022 return sizeof(uint64_t);
1023
1024 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1025 if (ret) {
1026 uint64_t *max_input_size = ret;
1027 /* Value reported by the closed source driver. */
1028 *max_input_size = 1024;
1029 }
1030 return sizeof(uint64_t);
1031
1032 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1033 if (ret) {
1034 uint64_t *max_mem_alloc_size = ret;
1035
1036 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1037 }
1038 return sizeof(uint64_t);
1039
1040 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1041 if (ret) {
1042 uint32_t *max_clock_frequency = ret;
1043 *max_clock_frequency = rscreen->info.max_shader_clock;
1044 }
1045 return sizeof(uint32_t);
1046
1047 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1048 if (ret) {
1049 uint32_t *max_compute_units = ret;
1050 *max_compute_units = rscreen->info.num_good_compute_units;
1051 }
1052 return sizeof(uint32_t);
1053
1054 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1055 if (ret) {
1056 uint32_t *images_supported = ret;
1057 *images_supported = 0;
1058 }
1059 return sizeof(uint32_t);
1060 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1061 break; /* unused */
1062 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1063 if (ret) {
1064 uint32_t *subgroup_size = ret;
1065 *subgroup_size = r600_wavefront_size(rscreen->family);
1066 }
1067 return sizeof(uint32_t);
1068 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1069 if (ret) {
1070 uint64_t *max_variable_threads_per_block = ret;
1071 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1072 ir_type == PIPE_SHADER_IR_TGSI)
1073 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1074 else
1075 *max_variable_threads_per_block = 0;
1076 }
1077 return sizeof(uint64_t);
1078 }
1079
1080 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1081 return 0;
1082 }
1083
1084 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1085 {
1086 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1087
1088 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1089 rscreen->info.clock_crystal_freq;
1090 }
1091
1092 static void r600_fence_reference(struct pipe_screen *screen,
1093 struct pipe_fence_handle **dst,
1094 struct pipe_fence_handle *src)
1095 {
1096 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1097 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1098 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1099
1100 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1101 ws->fence_reference(&(*rdst)->gfx, NULL);
1102 ws->fence_reference(&(*rdst)->sdma, NULL);
1103 FREE(*rdst);
1104 }
1105 *rdst = rsrc;
1106 }
1107
1108 static boolean r600_fence_finish(struct pipe_screen *screen,
1109 struct pipe_context *ctx,
1110 struct pipe_fence_handle *fence,
1111 uint64_t timeout)
1112 {
1113 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1114 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1115 struct r600_common_context *rctx =
1116 ctx ? (struct r600_common_context*)ctx : NULL;
1117 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1118
1119 if (rfence->sdma) {
1120 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1121 return false;
1122
1123 /* Recompute the timeout after waiting. */
1124 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1125 int64_t time = os_time_get_nano();
1126 timeout = abs_timeout > time ? abs_timeout - time : 0;
1127 }
1128 }
1129
1130 if (!rfence->gfx)
1131 return true;
1132
1133 /* Flush the gfx IB if it hasn't been flushed yet. */
1134 if (rctx &&
1135 rfence->gfx_unflushed.ctx == rctx &&
1136 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1137 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1138 rfence->gfx_unflushed.ctx = NULL;
1139
1140 if (!timeout)
1141 return false;
1142
1143 /* Recompute the timeout after all that. */
1144 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1145 int64_t time = os_time_get_nano();
1146 timeout = abs_timeout > time ? abs_timeout - time : 0;
1147 }
1148 }
1149
1150 return rws->fence_wait(rws, rfence->gfx, timeout);
1151 }
1152
1153 static void r600_query_memory_info(struct pipe_screen *screen,
1154 struct pipe_memory_info *info)
1155 {
1156 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1157 struct radeon_winsys *ws = rscreen->ws;
1158 unsigned vram_usage, gtt_usage;
1159
1160 info->total_device_memory = rscreen->info.vram_size / 1024;
1161 info->total_staging_memory = rscreen->info.gart_size / 1024;
1162
1163 /* The real TTM memory usage is somewhat random, because:
1164 *
1165 * 1) TTM delays freeing memory, because it can only free it after
1166 * fences expire.
1167 *
1168 * 2) The memory usage can be really low if big VRAM evictions are
1169 * taking place, but the real usage is well above the size of VRAM.
1170 *
1171 * Instead, return statistics of this process.
1172 */
1173 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1174 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1175
1176 info->avail_device_memory =
1177 vram_usage <= info->total_device_memory ?
1178 info->total_device_memory - vram_usage : 0;
1179 info->avail_staging_memory =
1180 gtt_usage <= info->total_staging_memory ?
1181 info->total_staging_memory - gtt_usage : 0;
1182
1183 info->device_memory_evicted =
1184 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1185
1186 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1187 info->nr_device_memory_evictions =
1188 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1189 else
1190 /* Just return the number of evicted 64KB pages. */
1191 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1192 }
1193
1194 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1195 const struct pipe_resource *templ)
1196 {
1197 if (templ->target == PIPE_BUFFER) {
1198 return r600_buffer_create(screen, templ, 256);
1199 } else {
1200 return r600_texture_create(screen, templ);
1201 }
1202 }
1203
1204 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1205 struct radeon_winsys *ws)
1206 {
1207 char llvm_string[32] = {}, kernel_version[128] = {};
1208 struct utsname uname_data;
1209
1210 ws->query_info(ws, &rscreen->info);
1211
1212 if (uname(&uname_data) == 0)
1213 snprintf(kernel_version, sizeof(kernel_version),
1214 " / %s", uname_data.release);
1215
1216 if (HAVE_LLVM > 0) {
1217 snprintf(llvm_string, sizeof(llvm_string),
1218 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1219 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1220 }
1221
1222 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1223 "%s (DRM %i.%i.%i%s%s)",
1224 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1225 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1226 kernel_version, llvm_string);
1227
1228 rscreen->b.get_name = r600_get_name;
1229 rscreen->b.get_vendor = r600_get_vendor;
1230 rscreen->b.get_device_vendor = r600_get_device_vendor;
1231 rscreen->b.get_compute_param = r600_get_compute_param;
1232 rscreen->b.get_paramf = r600_get_paramf;
1233 rscreen->b.get_timestamp = r600_get_timestamp;
1234 rscreen->b.fence_finish = r600_fence_finish;
1235 rscreen->b.fence_reference = r600_fence_reference;
1236 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1237 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1238 rscreen->b.query_memory_info = r600_query_memory_info;
1239
1240 if (rscreen->info.has_uvd) {
1241 rscreen->b.get_video_param = rvid_get_video_param;
1242 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1243 } else {
1244 rscreen->b.get_video_param = r600_get_video_param;
1245 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1246 }
1247
1248 r600_init_screen_texture_functions(rscreen);
1249 r600_init_screen_query_functions(rscreen);
1250
1251 rscreen->ws = ws;
1252 rscreen->family = rscreen->info.family;
1253 rscreen->chip_class = rscreen->info.chip_class;
1254 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1255
1256 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1257
1258 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1259 if (rscreen->force_aniso >= 0) {
1260 printf("radeon: Forcing anisotropy filter to %ix\n",
1261 /* round down to a power of two */
1262 1 << util_logbase2(rscreen->force_aniso));
1263 }
1264
1265 util_format_s3tc_init();
1266 pipe_mutex_init(rscreen->aux_context_lock);
1267 pipe_mutex_init(rscreen->gpu_load_mutex);
1268
1269 if (rscreen->debug_flags & DBG_INFO) {
1270 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1271 printf("family = %i (%s)\n", rscreen->info.family,
1272 r600_get_chip_name(rscreen));
1273 printf("chip_class = %i\n", rscreen->info.chip_class);
1274 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1275 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1276 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1277 printf("max_alloc_size = %i MB\n",
1278 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1279 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1280 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1281 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1282 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1283 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1284 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1285 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1286 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1287 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1288 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1289 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1290 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1291 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1292
1293 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1294 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1295 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1296 printf("max_se = %i\n", rscreen->info.max_se);
1297 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1298
1299 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1300 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1301 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1302 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1303 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1304 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1305 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1306 }
1307 return true;
1308 }
1309
1310 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1311 {
1312 r600_perfcounters_destroy(rscreen);
1313 r600_gpu_load_kill_thread(rscreen);
1314
1315 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1316 pipe_mutex_destroy(rscreen->aux_context_lock);
1317 rscreen->aux_context->destroy(rscreen->aux_context);
1318
1319 slab_destroy_parent(&rscreen->pool_transfers);
1320
1321 rscreen->ws->destroy(rscreen->ws);
1322 FREE(rscreen);
1323 }
1324
1325 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1326 unsigned processor)
1327 {
1328 switch (processor) {
1329 case PIPE_SHADER_VERTEX:
1330 return (rscreen->debug_flags & DBG_VS) != 0;
1331 case PIPE_SHADER_TESS_CTRL:
1332 return (rscreen->debug_flags & DBG_TCS) != 0;
1333 case PIPE_SHADER_TESS_EVAL:
1334 return (rscreen->debug_flags & DBG_TES) != 0;
1335 case PIPE_SHADER_GEOMETRY:
1336 return (rscreen->debug_flags & DBG_GS) != 0;
1337 case PIPE_SHADER_FRAGMENT:
1338 return (rscreen->debug_flags & DBG_PS) != 0;
1339 case PIPE_SHADER_COMPUTE:
1340 return (rscreen->debug_flags & DBG_CS) != 0;
1341 default:
1342 return false;
1343 }
1344 }
1345
1346 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1347 {
1348 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1349 r600_can_dump_shader(rscreen, processor);
1350 }
1351
1352 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1353 uint64_t offset, uint64_t size, unsigned value)
1354 {
1355 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1356
1357 pipe_mutex_lock(rscreen->aux_context_lock);
1358 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1359 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1360 pipe_mutex_unlock(rscreen->aux_context_lock);
1361 }