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gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40
41 #ifndef HAVE_LLVM
42 #define HAVE_LLVM 0
43 #endif
44
45 struct r600_multi_fence {
46 struct pipe_reference reference;
47 struct pipe_fence_handle *gfx;
48 struct pipe_fence_handle *sdma;
49 };
50
51 /*
52 * pipe_context
53 */
54
55 void r600_draw_rectangle(struct blitter_context *blitter,
56 int x1, int y1, int x2, int y2, float depth,
57 enum blitter_attrib_type type,
58 const union pipe_color_union *attrib)
59 {
60 struct r600_common_context *rctx =
61 (struct r600_common_context*)util_blitter_get_pipe(blitter);
62 struct pipe_viewport_state viewport;
63 struct pipe_resource *buf = NULL;
64 unsigned offset = 0;
65 float *vb;
66
67 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
68 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
69 return;
70 }
71
72 /* Some operations (like color resolve on r6xx) don't work
73 * with the conventional primitive types.
74 * One that works is PT_RECTLIST, which we use here. */
75
76 /* setup viewport */
77 viewport.scale[0] = 1.0f;
78 viewport.scale[1] = 1.0f;
79 viewport.scale[2] = 1.0f;
80 viewport.translate[0] = 0.0f;
81 viewport.translate[1] = 0.0f;
82 viewport.translate[2] = 0.0f;
83 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
84
85 /* Upload vertices. The hw rectangle has only 3 vertices,
86 * I guess the 4th one is derived from the first 3.
87 * The vertex specification should match u_blitter's vertex element state. */
88 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
89 if (!buf)
90 return;
91
92 vb[0] = x1;
93 vb[1] = y1;
94 vb[2] = depth;
95 vb[3] = 1;
96
97 vb[8] = x1;
98 vb[9] = y2;
99 vb[10] = depth;
100 vb[11] = 1;
101
102 vb[16] = x2;
103 vb[17] = y1;
104 vb[18] = depth;
105 vb[19] = 1;
106
107 if (attrib) {
108 memcpy(vb+4, attrib->f, sizeof(float)*4);
109 memcpy(vb+12, attrib->f, sizeof(float)*4);
110 memcpy(vb+20, attrib->f, sizeof(float)*4);
111 }
112
113 /* draw */
114 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
115 R600_PRIM_RECTANGLE_LIST, 3, 2);
116 pipe_resource_reference(&buf, NULL);
117 }
118
119 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
120 {
121 /* Flush the GFX IB if it's not empty. */
122 if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
123 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
124
125 /* Flush if there's not enough space. */
126 if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
127 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
128 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
129 }
130 }
131
132 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
133 {
134 }
135
136 void r600_preflush_suspend_features(struct r600_common_context *ctx)
137 {
138 /* suspend queries */
139 if (ctx->num_cs_dw_nontimer_queries_suspend) {
140 /* Since non-timer queries are suspended during blits,
141 * we have to guard against double-suspends. */
142 r600_suspend_nontimer_queries(ctx);
143 ctx->nontimer_queries_suspended_by_flush = true;
144 }
145 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
146 r600_suspend_timer_queries(ctx);
147
148 ctx->streamout.suspended = false;
149 if (ctx->streamout.begin_emitted) {
150 r600_emit_streamout_end(ctx);
151 ctx->streamout.suspended = true;
152 }
153 }
154
155 void r600_postflush_resume_features(struct r600_common_context *ctx)
156 {
157 if (ctx->streamout.suspended) {
158 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
159 r600_streamout_buffers_dirty(ctx);
160 }
161
162 /* resume queries */
163 if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
164 r600_resume_timer_queries(ctx);
165 if (ctx->nontimer_queries_suspended_by_flush) {
166 ctx->nontimer_queries_suspended_by_flush = false;
167 r600_resume_nontimer_queries(ctx);
168 }
169 }
170
171 static void r600_flush_from_st(struct pipe_context *ctx,
172 struct pipe_fence_handle **fence,
173 unsigned flags)
174 {
175 struct pipe_screen *screen = ctx->screen;
176 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
177 unsigned rflags = 0;
178 struct pipe_fence_handle *gfx_fence = NULL;
179 struct pipe_fence_handle *sdma_fence = NULL;
180
181 if (flags & PIPE_FLUSH_END_OF_FRAME)
182 rflags |= RADEON_FLUSH_END_OF_FRAME;
183
184 if (rctx->dma.cs) {
185 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
186 }
187 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
188
189 /* Both engines can signal out of order, so we need to keep both fences. */
190 if (gfx_fence || sdma_fence) {
191 struct r600_multi_fence *multi_fence =
192 CALLOC_STRUCT(r600_multi_fence);
193 if (!multi_fence)
194 return;
195
196 multi_fence->reference.count = 1;
197 multi_fence->gfx = gfx_fence;
198 multi_fence->sdma = sdma_fence;
199
200 screen->fence_reference(screen, fence, NULL);
201 *fence = (struct pipe_fence_handle*)multi_fence;
202 }
203 }
204
205 static void r600_flush_dma_ring(void *ctx, unsigned flags,
206 struct pipe_fence_handle **fence)
207 {
208 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
209 struct radeon_winsys_cs *cs = rctx->dma.cs;
210
211 if (cs->cdw)
212 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
213 if (fence)
214 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
215 }
216
217 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
218 {
219 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
220 unsigned latest = rctx->ws->query_value(rctx->ws,
221 RADEON_GPU_RESET_COUNTER);
222
223 if (rctx->gpu_reset_counter == latest)
224 return PIPE_NO_RESET;
225
226 rctx->gpu_reset_counter = latest;
227 return PIPE_UNKNOWN_CONTEXT_RESET;
228 }
229
230 static void r600_set_debug_callback(struct pipe_context *ctx,
231 const struct pipe_debug_callback *cb)
232 {
233 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
234
235 if (cb)
236 rctx->debug = *cb;
237 else
238 memset(&rctx->debug, 0, sizeof(rctx->debug));
239 }
240
241 bool r600_common_context_init(struct r600_common_context *rctx,
242 struct r600_common_screen *rscreen)
243 {
244 util_slab_create(&rctx->pool_transfers,
245 sizeof(struct r600_transfer), 64,
246 UTIL_SLAB_SINGLETHREADED);
247
248 rctx->screen = rscreen;
249 rctx->ws = rscreen->ws;
250 rctx->family = rscreen->family;
251 rctx->chip_class = rscreen->chip_class;
252
253 if (rscreen->chip_class >= CIK)
254 rctx->max_db = MAX2(8, rscreen->info.r600_num_backends);
255 else if (rscreen->chip_class >= EVERGREEN)
256 rctx->max_db = 8;
257 else
258 rctx->max_db = 4;
259
260 rctx->b.invalidate_resource = r600_invalidate_resource;
261 rctx->b.transfer_map = u_transfer_map_vtbl;
262 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
263 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
264 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
265 rctx->b.memory_barrier = r600_memory_barrier;
266 rctx->b.flush = r600_flush_from_st;
267 rctx->b.set_debug_callback = r600_set_debug_callback;
268
269 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
270 rctx->b.get_device_reset_status = r600_get_reset_status;
271 rctx->gpu_reset_counter =
272 rctx->ws->query_value(rctx->ws,
273 RADEON_GPU_RESET_COUNTER);
274 }
275
276 LIST_INITHEAD(&rctx->texture_buffers);
277
278 r600_init_context_texture_functions(rctx);
279 r600_streamout_init(rctx);
280 r600_query_init(rctx);
281 cayman_init_msaa(&rctx->b);
282
283 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
284 0, PIPE_USAGE_DEFAULT, TRUE);
285 if (!rctx->allocator_so_filled_size)
286 return false;
287
288 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
289 PIPE_BIND_INDEX_BUFFER |
290 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
291 if (!rctx->uploader)
292 return false;
293
294 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
295 if (!rctx->ctx)
296 return false;
297
298 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
299 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
300 r600_flush_dma_ring,
301 rctx, NULL);
302 rctx->dma.flush = r600_flush_dma_ring;
303 }
304
305 return true;
306 }
307
308 void r600_common_context_cleanup(struct r600_common_context *rctx)
309 {
310 if (rctx->gfx.cs)
311 rctx->ws->cs_destroy(rctx->gfx.cs);
312 if (rctx->dma.cs)
313 rctx->ws->cs_destroy(rctx->dma.cs);
314 if (rctx->ctx)
315 rctx->ws->ctx_destroy(rctx->ctx);
316
317 if (rctx->uploader) {
318 u_upload_destroy(rctx->uploader);
319 }
320
321 util_slab_destroy(&rctx->pool_transfers);
322
323 if (rctx->allocator_so_filled_size) {
324 u_suballocator_destroy(rctx->allocator_so_filled_size);
325 }
326 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
327 }
328
329 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
330 {
331 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
332 struct r600_resource *rr = (struct r600_resource *)r;
333
334 if (!r) {
335 return;
336 }
337
338 /*
339 * The idea is to compute a gross estimate of memory requirement of
340 * each draw call. After each draw call, memory will be precisely
341 * accounted. So the uncertainty is only on the current draw call.
342 * In practice this gave very good estimate (+/- 10% of the target
343 * memory limit).
344 */
345 if (rr->domains & RADEON_DOMAIN_GTT) {
346 rctx->gtt += rr->buf->size;
347 }
348 if (rr->domains & RADEON_DOMAIN_VRAM) {
349 rctx->vram += rr->buf->size;
350 }
351 }
352
353 /*
354 * pipe_screen
355 */
356
357 static const struct debug_named_value common_debug_options[] = {
358 /* logging */
359 { "tex", DBG_TEX, "Print texture info" },
360 { "compute", DBG_COMPUTE, "Print compute info" },
361 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
362 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
363 { "info", DBG_INFO, "Print driver information" },
364
365 /* shaders */
366 { "fs", DBG_FS, "Print fetch shaders" },
367 { "vs", DBG_VS, "Print vertex shaders" },
368 { "gs", DBG_GS, "Print geometry shaders" },
369 { "ps", DBG_PS, "Print pixel shaders" },
370 { "cs", DBG_CS, "Print compute shaders" },
371 { "tcs", DBG_TCS, "Print tessellation control shaders" },
372 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
373 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
374 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
375 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
376
377 /* features */
378 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
379 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
380 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
381 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
382 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
383 { "notiling", DBG_NO_TILING, "Disable tiling" },
384 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
385 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
386 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
387 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
388 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
389 { "nodcc", DBG_NO_DCC, "Disable DCC." },
390 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
391 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
392
393 DEBUG_NAMED_VALUE_END /* must be last */
394 };
395
396 static const char* r600_get_vendor(struct pipe_screen* pscreen)
397 {
398 return "X.Org";
399 }
400
401 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
402 {
403 return "AMD";
404 }
405
406 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
407 {
408 switch (rscreen->info.family) {
409 case CHIP_R600: return "AMD R600";
410 case CHIP_RV610: return "AMD RV610";
411 case CHIP_RV630: return "AMD RV630";
412 case CHIP_RV670: return "AMD RV670";
413 case CHIP_RV620: return "AMD RV620";
414 case CHIP_RV635: return "AMD RV635";
415 case CHIP_RS780: return "AMD RS780";
416 case CHIP_RS880: return "AMD RS880";
417 case CHIP_RV770: return "AMD RV770";
418 case CHIP_RV730: return "AMD RV730";
419 case CHIP_RV710: return "AMD RV710";
420 case CHIP_RV740: return "AMD RV740";
421 case CHIP_CEDAR: return "AMD CEDAR";
422 case CHIP_REDWOOD: return "AMD REDWOOD";
423 case CHIP_JUNIPER: return "AMD JUNIPER";
424 case CHIP_CYPRESS: return "AMD CYPRESS";
425 case CHIP_HEMLOCK: return "AMD HEMLOCK";
426 case CHIP_PALM: return "AMD PALM";
427 case CHIP_SUMO: return "AMD SUMO";
428 case CHIP_SUMO2: return "AMD SUMO2";
429 case CHIP_BARTS: return "AMD BARTS";
430 case CHIP_TURKS: return "AMD TURKS";
431 case CHIP_CAICOS: return "AMD CAICOS";
432 case CHIP_CAYMAN: return "AMD CAYMAN";
433 case CHIP_ARUBA: return "AMD ARUBA";
434 case CHIP_TAHITI: return "AMD TAHITI";
435 case CHIP_PITCAIRN: return "AMD PITCAIRN";
436 case CHIP_VERDE: return "AMD CAPE VERDE";
437 case CHIP_OLAND: return "AMD OLAND";
438 case CHIP_HAINAN: return "AMD HAINAN";
439 case CHIP_BONAIRE: return "AMD BONAIRE";
440 case CHIP_KAVERI: return "AMD KAVERI";
441 case CHIP_KABINI: return "AMD KABINI";
442 case CHIP_HAWAII: return "AMD HAWAII";
443 case CHIP_MULLINS: return "AMD MULLINS";
444 case CHIP_TONGA: return "AMD TONGA";
445 case CHIP_ICELAND: return "AMD ICELAND";
446 case CHIP_CARRIZO: return "AMD CARRIZO";
447 case CHIP_FIJI: return "AMD FIJI";
448 case CHIP_STONEY: return "AMD STONEY";
449 default: return "AMD unknown";
450 }
451 }
452
453 static const char* r600_get_name(struct pipe_screen* pscreen)
454 {
455 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
456
457 return rscreen->renderer_string;
458 }
459
460 static float r600_get_paramf(struct pipe_screen* pscreen,
461 enum pipe_capf param)
462 {
463 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
464
465 switch (param) {
466 case PIPE_CAPF_MAX_LINE_WIDTH:
467 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
468 case PIPE_CAPF_MAX_POINT_WIDTH:
469 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
470 if (rscreen->family >= CHIP_CEDAR)
471 return 16384.0f;
472 else
473 return 8192.0f;
474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
475 return 16.0f;
476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
477 return 16.0f;
478 case PIPE_CAPF_GUARD_BAND_LEFT:
479 case PIPE_CAPF_GUARD_BAND_TOP:
480 case PIPE_CAPF_GUARD_BAND_RIGHT:
481 case PIPE_CAPF_GUARD_BAND_BOTTOM:
482 return 0.0f;
483 }
484 return 0.0f;
485 }
486
487 static int r600_get_video_param(struct pipe_screen *screen,
488 enum pipe_video_profile profile,
489 enum pipe_video_entrypoint entrypoint,
490 enum pipe_video_cap param)
491 {
492 switch (param) {
493 case PIPE_VIDEO_CAP_SUPPORTED:
494 return vl_profile_supported(screen, profile, entrypoint);
495 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
496 return 1;
497 case PIPE_VIDEO_CAP_MAX_WIDTH:
498 case PIPE_VIDEO_CAP_MAX_HEIGHT:
499 return vl_video_buffer_max_size(screen);
500 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
501 return PIPE_FORMAT_NV12;
502 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
503 return false;
504 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
505 return false;
506 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
507 return true;
508 case PIPE_VIDEO_CAP_MAX_LEVEL:
509 return vl_level_supported(screen, profile);
510 default:
511 return 0;
512 }
513 }
514
515 const char *r600_get_llvm_processor_name(enum radeon_family family)
516 {
517 switch (family) {
518 case CHIP_R600:
519 case CHIP_RV630:
520 case CHIP_RV635:
521 case CHIP_RV670:
522 return "r600";
523 case CHIP_RV610:
524 case CHIP_RV620:
525 case CHIP_RS780:
526 case CHIP_RS880:
527 return "rs880";
528 case CHIP_RV710:
529 return "rv710";
530 case CHIP_RV730:
531 return "rv730";
532 case CHIP_RV740:
533 case CHIP_RV770:
534 return "rv770";
535 case CHIP_PALM:
536 case CHIP_CEDAR:
537 return "cedar";
538 case CHIP_SUMO:
539 case CHIP_SUMO2:
540 return "sumo";
541 case CHIP_REDWOOD:
542 return "redwood";
543 case CHIP_JUNIPER:
544 return "juniper";
545 case CHIP_HEMLOCK:
546 case CHIP_CYPRESS:
547 return "cypress";
548 case CHIP_BARTS:
549 return "barts";
550 case CHIP_TURKS:
551 return "turks";
552 case CHIP_CAICOS:
553 return "caicos";
554 case CHIP_CAYMAN:
555 case CHIP_ARUBA:
556 return "cayman";
557
558 case CHIP_TAHITI: return "tahiti";
559 case CHIP_PITCAIRN: return "pitcairn";
560 case CHIP_VERDE: return "verde";
561 case CHIP_OLAND: return "oland";
562 case CHIP_HAINAN: return "hainan";
563 case CHIP_BONAIRE: return "bonaire";
564 case CHIP_KABINI: return "kabini";
565 case CHIP_KAVERI: return "kaveri";
566 case CHIP_HAWAII: return "hawaii";
567 case CHIP_MULLINS:
568 return "mullins";
569 case CHIP_TONGA: return "tonga";
570 case CHIP_ICELAND: return "iceland";
571 case CHIP_CARRIZO: return "carrizo";
572 #if HAVE_LLVM <= 0x0307
573 case CHIP_FIJI: return "tonga";
574 case CHIP_STONEY: return "carrizo";
575 #else
576 case CHIP_FIJI: return "fiji";
577 case CHIP_STONEY: return "stoney";
578 #endif
579 default: return "";
580 }
581 }
582
583 static int r600_get_compute_param(struct pipe_screen *screen,
584 enum pipe_compute_cap param,
585 void *ret)
586 {
587 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
588
589 //TODO: select these params by asic
590 switch (param) {
591 case PIPE_COMPUTE_CAP_IR_TARGET: {
592 const char *gpu;
593 const char *triple;
594 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
595 triple = "r600--";
596 } else {
597 triple = "amdgcn--";
598 }
599 switch(rscreen->family) {
600 /* Clang < 3.6 is missing Hainan in its list of
601 * GPUs, so we need to use the name of a similar GPU.
602 */
603 #if HAVE_LLVM < 0x0306
604 case CHIP_HAINAN:
605 gpu = "oland";
606 break;
607 #endif
608 default:
609 gpu = r600_get_llvm_processor_name(rscreen->family);
610 break;
611 }
612 if (ret) {
613 sprintf(ret, "%s-%s", gpu, triple);
614 }
615 /* +2 for dash and terminating NIL byte */
616 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
617 }
618 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
619 if (ret) {
620 uint64_t *grid_dimension = ret;
621 grid_dimension[0] = 3;
622 }
623 return 1 * sizeof(uint64_t);
624
625 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
626 if (ret) {
627 uint64_t *grid_size = ret;
628 grid_size[0] = 65535;
629 grid_size[1] = 65535;
630 grid_size[2] = 1;
631 }
632 return 3 * sizeof(uint64_t) ;
633
634 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
635 if (ret) {
636 uint64_t *block_size = ret;
637 block_size[0] = 256;
638 block_size[1] = 256;
639 block_size[2] = 256;
640 }
641 return 3 * sizeof(uint64_t);
642
643 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
644 if (ret) {
645 uint64_t *max_threads_per_block = ret;
646 *max_threads_per_block = 256;
647 }
648 return sizeof(uint64_t);
649
650 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
651 if (ret) {
652 uint64_t *max_global_size = ret;
653 uint64_t max_mem_alloc_size;
654
655 r600_get_compute_param(screen,
656 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
657 &max_mem_alloc_size);
658
659 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
660 * 1/4 of the MAX_GLOBAL_SIZE. Since the
661 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
662 * make sure we never report more than
663 * 4 * MAX_MEM_ALLOC_SIZE.
664 */
665 *max_global_size = MIN2(4 * max_mem_alloc_size,
666 rscreen->info.gart_size +
667 rscreen->info.vram_size);
668 }
669 return sizeof(uint64_t);
670
671 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
672 if (ret) {
673 uint64_t *max_local_size = ret;
674 /* Value reported by the closed source driver. */
675 *max_local_size = 32768;
676 }
677 return sizeof(uint64_t);
678
679 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
680 if (ret) {
681 uint64_t *max_input_size = ret;
682 /* Value reported by the closed source driver. */
683 *max_input_size = 1024;
684 }
685 return sizeof(uint64_t);
686
687 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
688 if (ret) {
689 uint64_t *max_mem_alloc_size = ret;
690
691 /* XXX: The limit in older kernels is 256 MB. We
692 * should add a query here for newer kernels.
693 */
694 *max_mem_alloc_size = 256 * 1024 * 1024;
695 }
696 return sizeof(uint64_t);
697
698 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
699 if (ret) {
700 uint32_t *max_clock_frequency = ret;
701 *max_clock_frequency = rscreen->info.max_sclk;
702 }
703 return sizeof(uint32_t);
704
705 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
706 if (ret) {
707 uint32_t *max_compute_units = ret;
708 *max_compute_units = rscreen->info.max_compute_units;
709 }
710 return sizeof(uint32_t);
711
712 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
713 if (ret) {
714 uint32_t *images_supported = ret;
715 *images_supported = 0;
716 }
717 return sizeof(uint32_t);
718 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
719 break; /* unused */
720 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
721 if (ret) {
722 uint32_t *subgroup_size = ret;
723 *subgroup_size = r600_wavefront_size(rscreen->family);
724 }
725 return sizeof(uint32_t);
726 }
727
728 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
729 return 0;
730 }
731
732 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
733 {
734 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
735
736 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
737 rscreen->info.r600_clock_crystal_freq;
738 }
739
740 static void r600_fence_reference(struct pipe_screen *screen,
741 struct pipe_fence_handle **dst,
742 struct pipe_fence_handle *src)
743 {
744 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
745 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
746 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
747
748 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
749 ws->fence_reference(&(*rdst)->gfx, NULL);
750 ws->fence_reference(&(*rdst)->sdma, NULL);
751 FREE(*rdst);
752 }
753 *rdst = rsrc;
754 }
755
756 static boolean r600_fence_finish(struct pipe_screen *screen,
757 struct pipe_fence_handle *fence,
758 uint64_t timeout)
759 {
760 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
761 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
762 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
763
764 if (rfence->sdma) {
765 if (!rws->fence_wait(rws, rfence->sdma, timeout))
766 return false;
767
768 /* Recompute the timeout after waiting. */
769 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
770 int64_t time = os_time_get_nano();
771 timeout = abs_timeout > time ? abs_timeout - time : 0;
772 }
773 }
774
775 if (!rfence->gfx)
776 return true;
777
778 return rws->fence_wait(rws, rfence->gfx, timeout);
779 }
780
781 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
782 uint32_t tiling_config)
783 {
784 switch ((tiling_config & 0xe) >> 1) {
785 case 0:
786 rscreen->tiling_info.num_channels = 1;
787 break;
788 case 1:
789 rscreen->tiling_info.num_channels = 2;
790 break;
791 case 2:
792 rscreen->tiling_info.num_channels = 4;
793 break;
794 case 3:
795 rscreen->tiling_info.num_channels = 8;
796 break;
797 default:
798 return false;
799 }
800
801 switch ((tiling_config & 0x30) >> 4) {
802 case 0:
803 rscreen->tiling_info.num_banks = 4;
804 break;
805 case 1:
806 rscreen->tiling_info.num_banks = 8;
807 break;
808 default:
809 return false;
810
811 }
812 switch ((tiling_config & 0xc0) >> 6) {
813 case 0:
814 rscreen->tiling_info.group_bytes = 256;
815 break;
816 case 1:
817 rscreen->tiling_info.group_bytes = 512;
818 break;
819 default:
820 return false;
821 }
822 return true;
823 }
824
825 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
826 uint32_t tiling_config)
827 {
828 switch (tiling_config & 0xf) {
829 case 0:
830 rscreen->tiling_info.num_channels = 1;
831 break;
832 case 1:
833 rscreen->tiling_info.num_channels = 2;
834 break;
835 case 2:
836 rscreen->tiling_info.num_channels = 4;
837 break;
838 case 3:
839 rscreen->tiling_info.num_channels = 8;
840 break;
841 default:
842 return false;
843 }
844
845 switch ((tiling_config & 0xf0) >> 4) {
846 case 0:
847 rscreen->tiling_info.num_banks = 4;
848 break;
849 case 1:
850 rscreen->tiling_info.num_banks = 8;
851 break;
852 case 2:
853 rscreen->tiling_info.num_banks = 16;
854 break;
855 default:
856 return false;
857 }
858
859 switch ((tiling_config & 0xf00) >> 8) {
860 case 0:
861 rscreen->tiling_info.group_bytes = 256;
862 break;
863 case 1:
864 rscreen->tiling_info.group_bytes = 512;
865 break;
866 default:
867 return false;
868 }
869 return true;
870 }
871
872 static bool r600_init_tiling(struct r600_common_screen *rscreen)
873 {
874 uint32_t tiling_config = rscreen->info.r600_tiling_config;
875
876 /* set default group bytes, overridden by tiling info ioctl */
877 if (rscreen->chip_class <= R700) {
878 rscreen->tiling_info.group_bytes = 256;
879 } else {
880 rscreen->tiling_info.group_bytes = 512;
881 }
882
883 if (!tiling_config)
884 return true;
885
886 if (rscreen->chip_class <= R700) {
887 return r600_interpret_tiling(rscreen, tiling_config);
888 } else {
889 return evergreen_interpret_tiling(rscreen, tiling_config);
890 }
891 }
892
893 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
894 const struct pipe_resource *templ)
895 {
896 if (templ->target == PIPE_BUFFER) {
897 return r600_buffer_create(screen, templ, 4096);
898 } else {
899 return r600_texture_create(screen, templ);
900 }
901 }
902
903 bool r600_common_screen_init(struct r600_common_screen *rscreen,
904 struct radeon_winsys *ws)
905 {
906 char llvm_string[32] = {};
907
908 ws->query_info(ws, &rscreen->info);
909
910 #if HAVE_LLVM
911 snprintf(llvm_string, sizeof(llvm_string),
912 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
913 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
914 #endif
915
916 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
917 "%s (DRM %i.%i.%i%s)",
918 r600_get_chip_name(rscreen), rscreen->info.drm_major,
919 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
920 llvm_string);
921
922 rscreen->b.get_name = r600_get_name;
923 rscreen->b.get_vendor = r600_get_vendor;
924 rscreen->b.get_device_vendor = r600_get_device_vendor;
925 rscreen->b.get_compute_param = r600_get_compute_param;
926 rscreen->b.get_paramf = r600_get_paramf;
927 rscreen->b.get_timestamp = r600_get_timestamp;
928 rscreen->b.fence_finish = r600_fence_finish;
929 rscreen->b.fence_reference = r600_fence_reference;
930 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
931 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
932
933 if (rscreen->info.has_uvd) {
934 rscreen->b.get_video_param = rvid_get_video_param;
935 rscreen->b.is_video_format_supported = rvid_is_format_supported;
936 } else {
937 rscreen->b.get_video_param = r600_get_video_param;
938 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
939 }
940
941 r600_init_screen_texture_functions(rscreen);
942 r600_init_screen_query_functions(rscreen);
943
944 rscreen->ws = ws;
945 rscreen->family = rscreen->info.family;
946 rscreen->chip_class = rscreen->info.chip_class;
947 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
948
949 if (!r600_init_tiling(rscreen)) {
950 return false;
951 }
952 util_format_s3tc_init();
953 pipe_mutex_init(rscreen->aux_context_lock);
954 pipe_mutex_init(rscreen->gpu_load_mutex);
955
956 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
957 rscreen->info.drm_major == 3) &&
958 (rscreen->debug_flags & DBG_TRACE_CS)) {
959 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
960 PIPE_BIND_CUSTOM,
961 PIPE_USAGE_STAGING,
962 4096);
963 if (rscreen->trace_bo) {
964 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->buf, NULL,
965 PIPE_TRANSFER_UNSYNCHRONIZED);
966 }
967 }
968
969 if (rscreen->debug_flags & DBG_INFO) {
970 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
971 printf("family = %i\n", rscreen->info.family);
972 printf("chip_class = %i\n", rscreen->info.chip_class);
973 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
974 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
975 printf("max_sclk = %i\n", rscreen->info.max_sclk);
976 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
977 printf("max_se = %i\n", rscreen->info.max_se);
978 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
979 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
980 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
981 printf("has_uvd = %i\n", rscreen->info.has_uvd);
982 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
983 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
984 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
985 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
986 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
987 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
988 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
989 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
990 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
991 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
992 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
993 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
994 }
995 return true;
996 }
997
998 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
999 {
1000 r600_perfcounters_destroy(rscreen);
1001 r600_gpu_load_kill_thread(rscreen);
1002
1003 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1004 pipe_mutex_destroy(rscreen->aux_context_lock);
1005 rscreen->aux_context->destroy(rscreen->aux_context);
1006
1007 if (rscreen->trace_bo)
1008 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
1009
1010 rscreen->ws->destroy(rscreen->ws);
1011 FREE(rscreen);
1012 }
1013
1014 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1015 unsigned processor)
1016 {
1017 switch (processor) {
1018 case TGSI_PROCESSOR_VERTEX:
1019 return (rscreen->debug_flags & DBG_VS) != 0;
1020 case TGSI_PROCESSOR_TESS_CTRL:
1021 return (rscreen->debug_flags & DBG_TCS) != 0;
1022 case TGSI_PROCESSOR_TESS_EVAL:
1023 return (rscreen->debug_flags & DBG_TES) != 0;
1024 case TGSI_PROCESSOR_GEOMETRY:
1025 return (rscreen->debug_flags & DBG_GS) != 0;
1026 case TGSI_PROCESSOR_FRAGMENT:
1027 return (rscreen->debug_flags & DBG_PS) != 0;
1028 case TGSI_PROCESSOR_COMPUTE:
1029 return (rscreen->debug_flags & DBG_CS) != 0;
1030 default:
1031 return false;
1032 }
1033 }
1034
1035 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1036 unsigned offset, unsigned size, unsigned value,
1037 bool is_framebuffer)
1038 {
1039 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1040
1041 pipe_mutex_lock(rscreen->aux_context_lock);
1042 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1043 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1044 pipe_mutex_unlock(rscreen->aux_context_lock);
1045 }