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gallium/radeon: move unrelated code from dma_emit_wait_idle to need_dma_space
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 /**
84 * Write an EOP event.
85 *
86 * \param event EVENT_TYPE_*
87 * \param event_flags Optional cache flush flags (TC)
88 * \param data_sel 1 = fence, 3 = timestamp
89 * \param buf Buffer
90 * \param va GPU address
91 * \param old_value Previous fence value (for a bug workaround)
92 * \param new_value Fence value to write for this event.
93 */
94 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
95 unsigned event, unsigned event_flags,
96 unsigned data_sel,
97 struct r600_resource *buf, uint64_t va,
98 uint32_t old_fence, uint32_t new_fence)
99 {
100 struct radeon_winsys_cs *cs = ctx->gfx.cs;
101 unsigned op = EVENT_TYPE(event) |
102 EVENT_INDEX(5) |
103 event_flags;
104
105 if (ctx->chip_class == CIK ||
106 ctx->chip_class == VI) {
107 /* Two EOP events are required to make all engines go idle
108 * (and optional cache flushes executed) before the timestamp
109 * is written.
110 */
111 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
112 radeon_emit(cs, op);
113 radeon_emit(cs, va);
114 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
115 radeon_emit(cs, old_fence); /* immediate data */
116 radeon_emit(cs, 0); /* unused */
117 }
118
119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
120 radeon_emit(cs, op);
121 radeon_emit(cs, va);
122 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
123 radeon_emit(cs, new_fence); /* immediate data */
124 radeon_emit(cs, 0); /* unused */
125
126 if (buf)
127 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
128 RADEON_PRIO_QUERY);
129 }
130
131 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
132 {
133 unsigned dwords = 6;
134
135 if (screen->chip_class == CIK ||
136 screen->chip_class == VI)
137 dwords *= 2;
138
139 if (!screen->info.has_virtual_memory)
140 dwords += 2;
141
142 return dwords;
143 }
144
145 void r600_gfx_wait_fence(struct r600_common_context *ctx,
146 uint64_t va, uint32_t ref, uint32_t mask)
147 {
148 struct radeon_winsys_cs *cs = ctx->gfx.cs;
149
150 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
151 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
152 radeon_emit(cs, va);
153 radeon_emit(cs, va >> 32);
154 radeon_emit(cs, ref); /* reference value */
155 radeon_emit(cs, mask); /* mask */
156 radeon_emit(cs, 4); /* poll interval */
157 }
158
159 void r600_draw_rectangle(struct blitter_context *blitter,
160 int x1, int y1, int x2, int y2, float depth,
161 enum blitter_attrib_type type,
162 const union pipe_color_union *attrib)
163 {
164 struct r600_common_context *rctx =
165 (struct r600_common_context*)util_blitter_get_pipe(blitter);
166 struct pipe_viewport_state viewport;
167 struct pipe_resource *buf = NULL;
168 unsigned offset = 0;
169 float *vb;
170
171 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
172 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
173 return;
174 }
175
176 /* Some operations (like color resolve on r6xx) don't work
177 * with the conventional primitive types.
178 * One that works is PT_RECTLIST, which we use here. */
179
180 /* setup viewport */
181 viewport.scale[0] = 1.0f;
182 viewport.scale[1] = 1.0f;
183 viewport.scale[2] = 1.0f;
184 viewport.translate[0] = 0.0f;
185 viewport.translate[1] = 0.0f;
186 viewport.translate[2] = 0.0f;
187 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
188
189 /* Upload vertices. The hw rectangle has only 3 vertices,
190 * I guess the 4th one is derived from the first 3.
191 * The vertex specification should match u_blitter's vertex element state. */
192 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
193 if (!buf)
194 return;
195
196 vb[0] = x1;
197 vb[1] = y1;
198 vb[2] = depth;
199 vb[3] = 1;
200
201 vb[8] = x1;
202 vb[9] = y2;
203 vb[10] = depth;
204 vb[11] = 1;
205
206 vb[16] = x2;
207 vb[17] = y1;
208 vb[18] = depth;
209 vb[19] = 1;
210
211 if (attrib) {
212 memcpy(vb+4, attrib->f, sizeof(float)*4);
213 memcpy(vb+12, attrib->f, sizeof(float)*4);
214 memcpy(vb+20, attrib->f, sizeof(float)*4);
215 }
216
217 /* draw */
218 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
219 R600_PRIM_RECTANGLE_LIST, 3, 2);
220 pipe_resource_reference(&buf, NULL);
221 }
222
223 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
224 struct r600_resource *dst, struct r600_resource *src)
225 {
226 uint64_t vram = ctx->dma.cs->used_vram;
227 uint64_t gtt = ctx->dma.cs->used_gart;
228
229 if (dst) {
230 vram += dst->vram_usage;
231 gtt += dst->gart_usage;
232 }
233 if (src) {
234 vram += src->vram_usage;
235 gtt += src->gart_usage;
236 }
237
238 /* Flush the GFX IB if DMA depends on it. */
239 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
240 ((dst &&
241 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
242 RADEON_USAGE_READWRITE)) ||
243 (src &&
244 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
245 RADEON_USAGE_WRITE))))
246 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
247
248 /* Flush if there's not enough space, or if the memory usage per IB
249 * is too large.
250 *
251 * IBs using too little memory are limited by the IB submission overhead.
252 * IBs using too much memory are limited by the kernel/TTM overhead.
253 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
254 *
255 * This heuristic makes sure that DMA requests are executed
256 * very soon after the call is made and lowers memory usage.
257 * It improves texture upload performance by keeping the DMA
258 * engine busy while uploads are being submitted.
259 */
260 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
261 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
262 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
263 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
264 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
265 }
266
267 /* If GPUVM is not supported, the CS checker needs 2 entries
268 * in the buffer list per packet, which has to be done manually.
269 */
270 if (ctx->screen->info.has_virtual_memory) {
271 if (dst)
272 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
273 RADEON_USAGE_WRITE,
274 RADEON_PRIO_SDMA_BUFFER);
275 if (src)
276 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
277 RADEON_USAGE_READ,
278 RADEON_PRIO_SDMA_BUFFER);
279 }
280
281 /* this function is called before all DMA calls, so increment this. */
282 ctx->num_dma_calls++;
283 }
284
285 /* This is required to prevent read-after-write hazards. */
286 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
287 {
288 struct radeon_winsys_cs *cs = rctx->dma.cs;
289
290 r600_need_dma_space(rctx, 1, NULL, NULL);
291
292 if (!radeon_emitted(cs, 0)) /* empty queue */
293 return;
294
295 /* NOP waits for idle on Evergreen and later. */
296 if (rctx->chip_class >= CIK)
297 radeon_emit(cs, 0x00000000); /* NOP */
298 else if (rctx->chip_class >= EVERGREEN)
299 radeon_emit(cs, 0xf0000000); /* NOP */
300 else {
301 /* TODO: R600-R700 should use the FENCE packet.
302 * CS checker support is required. */
303 }
304 }
305
306 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
307 {
308 }
309
310 void r600_preflush_suspend_features(struct r600_common_context *ctx)
311 {
312 /* suspend queries */
313 if (!LIST_IS_EMPTY(&ctx->active_queries))
314 r600_suspend_queries(ctx);
315
316 ctx->streamout.suspended = false;
317 if (ctx->streamout.begin_emitted) {
318 r600_emit_streamout_end(ctx);
319 ctx->streamout.suspended = true;
320 }
321 }
322
323 void r600_postflush_resume_features(struct r600_common_context *ctx)
324 {
325 if (ctx->streamout.suspended) {
326 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
327 r600_streamout_buffers_dirty(ctx);
328 }
329
330 /* resume queries */
331 if (!LIST_IS_EMPTY(&ctx->active_queries))
332 r600_resume_queries(ctx);
333 }
334
335 static void r600_flush_from_st(struct pipe_context *ctx,
336 struct pipe_fence_handle **fence,
337 unsigned flags)
338 {
339 struct pipe_screen *screen = ctx->screen;
340 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
341 struct radeon_winsys *ws = rctx->ws;
342 unsigned rflags = 0;
343 struct pipe_fence_handle *gfx_fence = NULL;
344 struct pipe_fence_handle *sdma_fence = NULL;
345 bool deferred_fence = false;
346
347 if (flags & PIPE_FLUSH_END_OF_FRAME)
348 rflags |= RADEON_FLUSH_END_OF_FRAME;
349 if (flags & PIPE_FLUSH_DEFERRED)
350 rflags |= RADEON_FLUSH_ASYNC;
351
352 if (rctx->dma.cs) {
353 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
354 }
355
356 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
357 if (fence)
358 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
359 if (!(rflags & RADEON_FLUSH_ASYNC))
360 ws->cs_sync_flush(rctx->gfx.cs);
361 } else {
362 /* Instead of flushing, create a deferred fence. Constraints:
363 * - The state tracker must allow a deferred flush.
364 * - The state tracker must request a fence.
365 * Thread safety in fence_finish must be ensured by the state tracker.
366 */
367 if (flags & PIPE_FLUSH_DEFERRED && fence) {
368 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
369 deferred_fence = true;
370 } else {
371 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
372 }
373 }
374
375 /* Both engines can signal out of order, so we need to keep both fences. */
376 if (fence) {
377 struct r600_multi_fence *multi_fence =
378 CALLOC_STRUCT(r600_multi_fence);
379 if (!multi_fence)
380 return;
381
382 multi_fence->reference.count = 1;
383 /* If both fences are NULL, fence_finish will always return true. */
384 multi_fence->gfx = gfx_fence;
385 multi_fence->sdma = sdma_fence;
386
387 if (deferred_fence) {
388 multi_fence->gfx_unflushed.ctx = rctx;
389 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
390 }
391
392 screen->fence_reference(screen, fence, NULL);
393 *fence = (struct pipe_fence_handle*)multi_fence;
394 }
395 }
396
397 static void r600_flush_dma_ring(void *ctx, unsigned flags,
398 struct pipe_fence_handle **fence)
399 {
400 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
401 struct radeon_winsys_cs *cs = rctx->dma.cs;
402 struct radeon_saved_cs saved;
403 bool check_vm =
404 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
405 rctx->check_vm_faults;
406
407 if (!radeon_emitted(cs, 0)) {
408 if (fence)
409 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
410 return;
411 }
412
413 if (check_vm)
414 radeon_save_cs(rctx->ws, cs, &saved);
415
416 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
417 if (fence)
418 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
419
420 if (check_vm) {
421 /* Use conservative timeout 800ms, after which we won't wait any
422 * longer and assume the GPU is hung.
423 */
424 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
425
426 rctx->check_vm_faults(rctx, &saved, RING_DMA);
427 radeon_clear_saved_cs(&saved);
428 }
429 }
430
431 /**
432 * Store a linearized copy of all chunks of \p cs together with the buffer
433 * list in \p saved.
434 */
435 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
436 struct radeon_saved_cs *saved)
437 {
438 void *buf;
439 unsigned i;
440
441 /* Save the IB chunks. */
442 saved->num_dw = cs->prev_dw + cs->current.cdw;
443 saved->ib = MALLOC(4 * saved->num_dw);
444 if (!saved->ib)
445 goto oom;
446
447 buf = saved->ib;
448 for (i = 0; i < cs->num_prev; ++i) {
449 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
450 buf += cs->prev[i].cdw;
451 }
452 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
453
454 /* Save the buffer list. */
455 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
456 saved->bo_list = CALLOC(saved->bo_count,
457 sizeof(saved->bo_list[0]));
458 if (!saved->bo_list) {
459 FREE(saved->ib);
460 goto oom;
461 }
462 ws->cs_get_buffer_list(cs, saved->bo_list);
463
464 return;
465
466 oom:
467 fprintf(stderr, "%s: out of memory\n", __func__);
468 memset(saved, 0, sizeof(*saved));
469 }
470
471 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
472 {
473 FREE(saved->ib);
474 FREE(saved->bo_list);
475
476 memset(saved, 0, sizeof(*saved));
477 }
478
479 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
480 {
481 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
482 unsigned latest = rctx->ws->query_value(rctx->ws,
483 RADEON_GPU_RESET_COUNTER);
484
485 if (rctx->gpu_reset_counter == latest)
486 return PIPE_NO_RESET;
487
488 rctx->gpu_reset_counter = latest;
489 return PIPE_UNKNOWN_CONTEXT_RESET;
490 }
491
492 static void r600_set_debug_callback(struct pipe_context *ctx,
493 const struct pipe_debug_callback *cb)
494 {
495 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
496
497 if (cb)
498 rctx->debug = *cb;
499 else
500 memset(&rctx->debug, 0, sizeof(rctx->debug));
501 }
502
503 static void r600_set_device_reset_callback(struct pipe_context *ctx,
504 const struct pipe_device_reset_callback *cb)
505 {
506 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
507
508 if (cb)
509 rctx->device_reset_callback = *cb;
510 else
511 memset(&rctx->device_reset_callback, 0,
512 sizeof(rctx->device_reset_callback));
513 }
514
515 bool r600_check_device_reset(struct r600_common_context *rctx)
516 {
517 enum pipe_reset_status status;
518
519 if (!rctx->device_reset_callback.reset)
520 return false;
521
522 if (!rctx->b.get_device_reset_status)
523 return false;
524
525 status = rctx->b.get_device_reset_status(&rctx->b);
526 if (status == PIPE_NO_RESET)
527 return false;
528
529 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
530 return true;
531 }
532
533 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
534 struct pipe_resource *dst,
535 uint64_t offset, uint64_t size,
536 unsigned value)
537 {
538 ctx->clear_buffer(ctx, dst, offset, size, &value, 4);
539 }
540
541 bool r600_common_context_init(struct r600_common_context *rctx,
542 struct r600_common_screen *rscreen,
543 unsigned context_flags)
544 {
545 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
546
547 rctx->screen = rscreen;
548 rctx->ws = rscreen->ws;
549 rctx->family = rscreen->family;
550 rctx->chip_class = rscreen->chip_class;
551
552 if (rscreen->chip_class >= CIK)
553 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
554 else if (rscreen->chip_class >= EVERGREEN)
555 rctx->max_db = 8;
556 else
557 rctx->max_db = 4;
558
559 rctx->b.invalidate_resource = r600_invalidate_resource;
560 rctx->b.transfer_map = u_transfer_map_vtbl;
561 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
562 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
563 rctx->b.texture_subdata = u_default_texture_subdata;
564 rctx->b.memory_barrier = r600_memory_barrier;
565 rctx->b.flush = r600_flush_from_st;
566 rctx->b.set_debug_callback = r600_set_debug_callback;
567 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
568
569 /* evergreen_compute.c has a special codepath for global buffers.
570 * Everything else can use the direct path.
571 */
572 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
573 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
574 rctx->b.buffer_subdata = u_default_buffer_subdata;
575 else
576 rctx->b.buffer_subdata = r600_buffer_subdata;
577
578 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
579 rctx->b.get_device_reset_status = r600_get_reset_status;
580 rctx->gpu_reset_counter =
581 rctx->ws->query_value(rctx->ws,
582 RADEON_GPU_RESET_COUNTER);
583 }
584
585 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
586
587 r600_init_context_texture_functions(rctx);
588 r600_init_viewport_functions(rctx);
589 r600_streamout_init(rctx);
590 r600_query_init(rctx);
591 cayman_init_msaa(&rctx->b);
592
593 rctx->allocator_zeroed_memory =
594 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
595 0, PIPE_USAGE_DEFAULT, true);
596 if (!rctx->allocator_zeroed_memory)
597 return false;
598
599 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
600 PIPE_BIND_INDEX_BUFFER |
601 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
602 if (!rctx->uploader)
603 return false;
604
605 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
606 if (!rctx->ctx)
607 return false;
608
609 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
610 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
611 r600_flush_dma_ring,
612 rctx);
613 rctx->dma.flush = r600_flush_dma_ring;
614 }
615
616 return true;
617 }
618
619 void r600_common_context_cleanup(struct r600_common_context *rctx)
620 {
621 unsigned i,j;
622
623 /* Release DCC stats. */
624 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
625 assert(!rctx->dcc_stats[i].query_active);
626
627 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
628 if (rctx->dcc_stats[i].ps_stats[j])
629 rctx->b.destroy_query(&rctx->b,
630 rctx->dcc_stats[i].ps_stats[j]);
631
632 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
633 }
634
635 if (rctx->query_result_shader)
636 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
637
638 if (rctx->gfx.cs)
639 rctx->ws->cs_destroy(rctx->gfx.cs);
640 if (rctx->dma.cs)
641 rctx->ws->cs_destroy(rctx->dma.cs);
642 if (rctx->ctx)
643 rctx->ws->ctx_destroy(rctx->ctx);
644
645 if (rctx->uploader) {
646 u_upload_destroy(rctx->uploader);
647 }
648
649 slab_destroy_child(&rctx->pool_transfers);
650
651 if (rctx->allocator_zeroed_memory) {
652 u_suballocator_destroy(rctx->allocator_zeroed_memory);
653 }
654 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
655 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
656 }
657
658 /*
659 * pipe_screen
660 */
661
662 static const struct debug_named_value common_debug_options[] = {
663 /* logging */
664 { "tex", DBG_TEX, "Print texture info" },
665 { "compute", DBG_COMPUTE, "Print compute info" },
666 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
667 { "info", DBG_INFO, "Print driver information" },
668
669 /* shaders */
670 { "fs", DBG_FS, "Print fetch shaders" },
671 { "vs", DBG_VS, "Print vertex shaders" },
672 { "gs", DBG_GS, "Print geometry shaders" },
673 { "ps", DBG_PS, "Print pixel shaders" },
674 { "cs", DBG_CS, "Print compute shaders" },
675 { "tcs", DBG_TCS, "Print tessellation control shaders" },
676 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
677 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
678 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
679 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
680 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
681 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
682 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
683
684 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
685
686 /* features */
687 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
688 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
689 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
690 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
691 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
692 { "notiling", DBG_NO_TILING, "Disable tiling" },
693 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
694 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
695 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
696 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
697 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
698 { "nodcc", DBG_NO_DCC, "Disable DCC." },
699 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
700 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
701 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
702 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
703 { "noce", DBG_NO_CE, "Disable the constant engine"},
704 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
705 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
706
707 DEBUG_NAMED_VALUE_END /* must be last */
708 };
709
710 static const char* r600_get_vendor(struct pipe_screen* pscreen)
711 {
712 return "X.Org";
713 }
714
715 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
716 {
717 return "AMD";
718 }
719
720 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
721 {
722 switch (rscreen->info.family) {
723 case CHIP_R600: return "AMD R600";
724 case CHIP_RV610: return "AMD RV610";
725 case CHIP_RV630: return "AMD RV630";
726 case CHIP_RV670: return "AMD RV670";
727 case CHIP_RV620: return "AMD RV620";
728 case CHIP_RV635: return "AMD RV635";
729 case CHIP_RS780: return "AMD RS780";
730 case CHIP_RS880: return "AMD RS880";
731 case CHIP_RV770: return "AMD RV770";
732 case CHIP_RV730: return "AMD RV730";
733 case CHIP_RV710: return "AMD RV710";
734 case CHIP_RV740: return "AMD RV740";
735 case CHIP_CEDAR: return "AMD CEDAR";
736 case CHIP_REDWOOD: return "AMD REDWOOD";
737 case CHIP_JUNIPER: return "AMD JUNIPER";
738 case CHIP_CYPRESS: return "AMD CYPRESS";
739 case CHIP_HEMLOCK: return "AMD HEMLOCK";
740 case CHIP_PALM: return "AMD PALM";
741 case CHIP_SUMO: return "AMD SUMO";
742 case CHIP_SUMO2: return "AMD SUMO2";
743 case CHIP_BARTS: return "AMD BARTS";
744 case CHIP_TURKS: return "AMD TURKS";
745 case CHIP_CAICOS: return "AMD CAICOS";
746 case CHIP_CAYMAN: return "AMD CAYMAN";
747 case CHIP_ARUBA: return "AMD ARUBA";
748 case CHIP_TAHITI: return "AMD TAHITI";
749 case CHIP_PITCAIRN: return "AMD PITCAIRN";
750 case CHIP_VERDE: return "AMD CAPE VERDE";
751 case CHIP_OLAND: return "AMD OLAND";
752 case CHIP_HAINAN: return "AMD HAINAN";
753 case CHIP_BONAIRE: return "AMD BONAIRE";
754 case CHIP_KAVERI: return "AMD KAVERI";
755 case CHIP_KABINI: return "AMD KABINI";
756 case CHIP_HAWAII: return "AMD HAWAII";
757 case CHIP_MULLINS: return "AMD MULLINS";
758 case CHIP_TONGA: return "AMD TONGA";
759 case CHIP_ICELAND: return "AMD ICELAND";
760 case CHIP_CARRIZO: return "AMD CARRIZO";
761 case CHIP_FIJI: return "AMD FIJI";
762 case CHIP_POLARIS10: return "AMD POLARIS10";
763 case CHIP_POLARIS11: return "AMD POLARIS11";
764 case CHIP_POLARIS12: return "AMD POLARIS12";
765 case CHIP_STONEY: return "AMD STONEY";
766 default: return "AMD unknown";
767 }
768 }
769
770 static const char* r600_get_name(struct pipe_screen* pscreen)
771 {
772 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
773
774 return rscreen->renderer_string;
775 }
776
777 static float r600_get_paramf(struct pipe_screen* pscreen,
778 enum pipe_capf param)
779 {
780 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
781
782 switch (param) {
783 case PIPE_CAPF_MAX_LINE_WIDTH:
784 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
785 case PIPE_CAPF_MAX_POINT_WIDTH:
786 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
787 if (rscreen->family >= CHIP_CEDAR)
788 return 16384.0f;
789 else
790 return 8192.0f;
791 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
792 return 16.0f;
793 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
794 return 16.0f;
795 case PIPE_CAPF_GUARD_BAND_LEFT:
796 case PIPE_CAPF_GUARD_BAND_TOP:
797 case PIPE_CAPF_GUARD_BAND_RIGHT:
798 case PIPE_CAPF_GUARD_BAND_BOTTOM:
799 return 0.0f;
800 }
801 return 0.0f;
802 }
803
804 static int r600_get_video_param(struct pipe_screen *screen,
805 enum pipe_video_profile profile,
806 enum pipe_video_entrypoint entrypoint,
807 enum pipe_video_cap param)
808 {
809 switch (param) {
810 case PIPE_VIDEO_CAP_SUPPORTED:
811 return vl_profile_supported(screen, profile, entrypoint);
812 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
813 return 1;
814 case PIPE_VIDEO_CAP_MAX_WIDTH:
815 case PIPE_VIDEO_CAP_MAX_HEIGHT:
816 return vl_video_buffer_max_size(screen);
817 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
818 return PIPE_FORMAT_NV12;
819 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
820 return false;
821 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
822 return false;
823 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
824 return true;
825 case PIPE_VIDEO_CAP_MAX_LEVEL:
826 return vl_level_supported(screen, profile);
827 default:
828 return 0;
829 }
830 }
831
832 const char *r600_get_llvm_processor_name(enum radeon_family family)
833 {
834 switch (family) {
835 case CHIP_R600:
836 case CHIP_RV630:
837 case CHIP_RV635:
838 case CHIP_RV670:
839 return "r600";
840 case CHIP_RV610:
841 case CHIP_RV620:
842 case CHIP_RS780:
843 case CHIP_RS880:
844 return "rs880";
845 case CHIP_RV710:
846 return "rv710";
847 case CHIP_RV730:
848 return "rv730";
849 case CHIP_RV740:
850 case CHIP_RV770:
851 return "rv770";
852 case CHIP_PALM:
853 case CHIP_CEDAR:
854 return "cedar";
855 case CHIP_SUMO:
856 case CHIP_SUMO2:
857 return "sumo";
858 case CHIP_REDWOOD:
859 return "redwood";
860 case CHIP_JUNIPER:
861 return "juniper";
862 case CHIP_HEMLOCK:
863 case CHIP_CYPRESS:
864 return "cypress";
865 case CHIP_BARTS:
866 return "barts";
867 case CHIP_TURKS:
868 return "turks";
869 case CHIP_CAICOS:
870 return "caicos";
871 case CHIP_CAYMAN:
872 case CHIP_ARUBA:
873 return "cayman";
874
875 case CHIP_TAHITI: return "tahiti";
876 case CHIP_PITCAIRN: return "pitcairn";
877 case CHIP_VERDE: return "verde";
878 case CHIP_OLAND: return "oland";
879 case CHIP_HAINAN: return "hainan";
880 case CHIP_BONAIRE: return "bonaire";
881 case CHIP_KABINI: return "kabini";
882 case CHIP_KAVERI: return "kaveri";
883 case CHIP_HAWAII: return "hawaii";
884 case CHIP_MULLINS:
885 return "mullins";
886 case CHIP_TONGA: return "tonga";
887 case CHIP_ICELAND: return "iceland";
888 case CHIP_CARRIZO: return "carrizo";
889 #if HAVE_LLVM <= 0x0307
890 case CHIP_FIJI: return "tonga";
891 case CHIP_STONEY: return "carrizo";
892 #else
893 case CHIP_FIJI: return "fiji";
894 case CHIP_STONEY: return "stoney";
895 #endif
896 #if HAVE_LLVM <= 0x0308
897 case CHIP_POLARIS10: return "tonga";
898 case CHIP_POLARIS11: return "tonga";
899 case CHIP_POLARIS12: return "tonga";
900 #else
901 case CHIP_POLARIS10: return "polaris10";
902 case CHIP_POLARIS11: return "polaris11";
903 case CHIP_POLARIS12: return "polaris11";
904 #endif
905 default: return "";
906 }
907 }
908
909 static int r600_get_compute_param(struct pipe_screen *screen,
910 enum pipe_shader_ir ir_type,
911 enum pipe_compute_cap param,
912 void *ret)
913 {
914 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
915
916 //TODO: select these params by asic
917 switch (param) {
918 case PIPE_COMPUTE_CAP_IR_TARGET: {
919 const char *gpu;
920 const char *triple;
921 if (rscreen->family <= CHIP_ARUBA) {
922 triple = "r600--";
923 } else {
924 if (HAVE_LLVM < 0x0400) {
925 triple = "amdgcn--";
926 } else {
927 triple = "amdgcn-mesa-mesa3d";
928 }
929 }
930 switch(rscreen->family) {
931 /* Clang < 3.6 is missing Hainan in its list of
932 * GPUs, so we need to use the name of a similar GPU.
933 */
934 default:
935 gpu = r600_get_llvm_processor_name(rscreen->family);
936 break;
937 }
938 if (ret) {
939 sprintf(ret, "%s-%s", gpu, triple);
940 }
941 /* +2 for dash and terminating NIL byte */
942 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
943 }
944 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
945 if (ret) {
946 uint64_t *grid_dimension = ret;
947 grid_dimension[0] = 3;
948 }
949 return 1 * sizeof(uint64_t);
950
951 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
952 if (ret) {
953 uint64_t *grid_size = ret;
954 grid_size[0] = 65535;
955 grid_size[1] = 65535;
956 grid_size[2] = 65535;
957 }
958 return 3 * sizeof(uint64_t) ;
959
960 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
961 if (ret) {
962 uint64_t *block_size = ret;
963 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
964 ir_type == PIPE_SHADER_IR_TGSI) {
965 block_size[0] = 2048;
966 block_size[1] = 2048;
967 block_size[2] = 2048;
968 } else {
969 block_size[0] = 256;
970 block_size[1] = 256;
971 block_size[2] = 256;
972 }
973 }
974 return 3 * sizeof(uint64_t);
975
976 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
977 if (ret) {
978 uint64_t *max_threads_per_block = ret;
979 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
980 ir_type == PIPE_SHADER_IR_TGSI)
981 *max_threads_per_block = 2048;
982 else
983 *max_threads_per_block = 256;
984 }
985 return sizeof(uint64_t);
986 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
987 if (ret) {
988 uint32_t *address_bits = ret;
989 address_bits[0] = 32;
990 if (rscreen->chip_class >= SI)
991 address_bits[0] = 64;
992 }
993 return 1 * sizeof(uint32_t);
994
995 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
996 if (ret) {
997 uint64_t *max_global_size = ret;
998 uint64_t max_mem_alloc_size;
999
1000 r600_get_compute_param(screen, ir_type,
1001 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1002 &max_mem_alloc_size);
1003
1004 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1005 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1006 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1007 * make sure we never report more than
1008 * 4 * MAX_MEM_ALLOC_SIZE.
1009 */
1010 *max_global_size = MIN2(4 * max_mem_alloc_size,
1011 MAX2(rscreen->info.gart_size,
1012 rscreen->info.vram_size));
1013 }
1014 return sizeof(uint64_t);
1015
1016 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1017 if (ret) {
1018 uint64_t *max_local_size = ret;
1019 /* Value reported by the closed source driver. */
1020 *max_local_size = 32768;
1021 }
1022 return sizeof(uint64_t);
1023
1024 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1025 if (ret) {
1026 uint64_t *max_input_size = ret;
1027 /* Value reported by the closed source driver. */
1028 *max_input_size = 1024;
1029 }
1030 return sizeof(uint64_t);
1031
1032 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1033 if (ret) {
1034 uint64_t *max_mem_alloc_size = ret;
1035
1036 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1037 }
1038 return sizeof(uint64_t);
1039
1040 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1041 if (ret) {
1042 uint32_t *max_clock_frequency = ret;
1043 *max_clock_frequency = rscreen->info.max_shader_clock;
1044 }
1045 return sizeof(uint32_t);
1046
1047 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1048 if (ret) {
1049 uint32_t *max_compute_units = ret;
1050 *max_compute_units = rscreen->info.num_good_compute_units;
1051 }
1052 return sizeof(uint32_t);
1053
1054 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1055 if (ret) {
1056 uint32_t *images_supported = ret;
1057 *images_supported = 0;
1058 }
1059 return sizeof(uint32_t);
1060 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1061 break; /* unused */
1062 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1063 if (ret) {
1064 uint32_t *subgroup_size = ret;
1065 *subgroup_size = r600_wavefront_size(rscreen->family);
1066 }
1067 return sizeof(uint32_t);
1068 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1069 if (ret) {
1070 uint64_t *max_variable_threads_per_block = ret;
1071 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1072 ir_type == PIPE_SHADER_IR_TGSI)
1073 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1074 else
1075 *max_variable_threads_per_block = 0;
1076 }
1077 return sizeof(uint64_t);
1078 }
1079
1080 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1081 return 0;
1082 }
1083
1084 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1085 {
1086 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1087
1088 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1089 rscreen->info.clock_crystal_freq;
1090 }
1091
1092 static void r600_fence_reference(struct pipe_screen *screen,
1093 struct pipe_fence_handle **dst,
1094 struct pipe_fence_handle *src)
1095 {
1096 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1097 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1098 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1099
1100 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1101 ws->fence_reference(&(*rdst)->gfx, NULL);
1102 ws->fence_reference(&(*rdst)->sdma, NULL);
1103 FREE(*rdst);
1104 }
1105 *rdst = rsrc;
1106 }
1107
1108 static boolean r600_fence_finish(struct pipe_screen *screen,
1109 struct pipe_context *ctx,
1110 struct pipe_fence_handle *fence,
1111 uint64_t timeout)
1112 {
1113 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1114 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1115 struct r600_common_context *rctx =
1116 ctx ? (struct r600_common_context*)ctx : NULL;
1117 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1118
1119 if (rfence->sdma) {
1120 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1121 return false;
1122
1123 /* Recompute the timeout after waiting. */
1124 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1125 int64_t time = os_time_get_nano();
1126 timeout = abs_timeout > time ? abs_timeout - time : 0;
1127 }
1128 }
1129
1130 if (!rfence->gfx)
1131 return true;
1132
1133 /* Flush the gfx IB if it hasn't been flushed yet. */
1134 if (rctx &&
1135 rfence->gfx_unflushed.ctx == rctx &&
1136 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1137 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1138 rfence->gfx_unflushed.ctx = NULL;
1139
1140 if (!timeout)
1141 return false;
1142
1143 /* Recompute the timeout after all that. */
1144 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1145 int64_t time = os_time_get_nano();
1146 timeout = abs_timeout > time ? abs_timeout - time : 0;
1147 }
1148 }
1149
1150 return rws->fence_wait(rws, rfence->gfx, timeout);
1151 }
1152
1153 static void r600_query_memory_info(struct pipe_screen *screen,
1154 struct pipe_memory_info *info)
1155 {
1156 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1157 struct radeon_winsys *ws = rscreen->ws;
1158 unsigned vram_usage, gtt_usage;
1159
1160 info->total_device_memory = rscreen->info.vram_size / 1024;
1161 info->total_staging_memory = rscreen->info.gart_size / 1024;
1162
1163 /* The real TTM memory usage is somewhat random, because:
1164 *
1165 * 1) TTM delays freeing memory, because it can only free it after
1166 * fences expire.
1167 *
1168 * 2) The memory usage can be really low if big VRAM evictions are
1169 * taking place, but the real usage is well above the size of VRAM.
1170 *
1171 * Instead, return statistics of this process.
1172 */
1173 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1174 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1175
1176 info->avail_device_memory =
1177 vram_usage <= info->total_device_memory ?
1178 info->total_device_memory - vram_usage : 0;
1179 info->avail_staging_memory =
1180 gtt_usage <= info->total_staging_memory ?
1181 info->total_staging_memory - gtt_usage : 0;
1182
1183 info->device_memory_evicted =
1184 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1185
1186 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1187 info->nr_device_memory_evictions =
1188 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1189 else
1190 /* Just return the number of evicted 64KB pages. */
1191 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1192 }
1193
1194 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1195 const struct pipe_resource *templ)
1196 {
1197 if (templ->target == PIPE_BUFFER) {
1198 return r600_buffer_create(screen, templ, 256);
1199 } else {
1200 return r600_texture_create(screen, templ);
1201 }
1202 }
1203
1204 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1205 struct radeon_winsys *ws)
1206 {
1207 char llvm_string[32] = {}, kernel_version[128] = {};
1208 struct utsname uname_data;
1209
1210 ws->query_info(ws, &rscreen->info);
1211
1212 if (uname(&uname_data) == 0)
1213 snprintf(kernel_version, sizeof(kernel_version),
1214 " / %s", uname_data.release);
1215
1216 #if HAVE_LLVM
1217 snprintf(llvm_string, sizeof(llvm_string),
1218 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1219 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1220 #endif
1221
1222 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1223 "%s (DRM %i.%i.%i%s%s)",
1224 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1225 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1226 kernel_version, llvm_string);
1227
1228 rscreen->b.get_name = r600_get_name;
1229 rscreen->b.get_vendor = r600_get_vendor;
1230 rscreen->b.get_device_vendor = r600_get_device_vendor;
1231 rscreen->b.get_compute_param = r600_get_compute_param;
1232 rscreen->b.get_paramf = r600_get_paramf;
1233 rscreen->b.get_timestamp = r600_get_timestamp;
1234 rscreen->b.fence_finish = r600_fence_finish;
1235 rscreen->b.fence_reference = r600_fence_reference;
1236 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1237 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1238 rscreen->b.query_memory_info = r600_query_memory_info;
1239
1240 if (rscreen->info.has_uvd) {
1241 rscreen->b.get_video_param = rvid_get_video_param;
1242 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1243 } else {
1244 rscreen->b.get_video_param = r600_get_video_param;
1245 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1246 }
1247
1248 r600_init_screen_texture_functions(rscreen);
1249 r600_init_screen_query_functions(rscreen);
1250
1251 rscreen->ws = ws;
1252 rscreen->family = rscreen->info.family;
1253 rscreen->chip_class = rscreen->info.chip_class;
1254 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1255
1256 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1257
1258 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1259 if (rscreen->force_aniso >= 0) {
1260 printf("radeon: Forcing anisotropy filter to %ix\n",
1261 /* round down to a power of two */
1262 1 << util_logbase2(rscreen->force_aniso));
1263 }
1264
1265 util_format_s3tc_init();
1266 pipe_mutex_init(rscreen->aux_context_lock);
1267 pipe_mutex_init(rscreen->gpu_load_mutex);
1268
1269 if (rscreen->debug_flags & DBG_INFO) {
1270 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1271 printf("family = %i (%s)\n", rscreen->info.family,
1272 r600_get_chip_name(rscreen));
1273 printf("chip_class = %i\n", rscreen->info.chip_class);
1274 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1275 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1276 printf("max_alloc_size = %i MB\n",
1277 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1278 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1279 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1280 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1281 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1282 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1283 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1284 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1285 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1286 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1287 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1288 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1289 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1290 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1291
1292 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1293 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1294 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1295 printf("max_se = %i\n", rscreen->info.max_se);
1296 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1297
1298 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1299 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1300 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1301 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1302 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1303 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1304 }
1305 return true;
1306 }
1307
1308 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1309 {
1310 r600_perfcounters_destroy(rscreen);
1311 r600_gpu_load_kill_thread(rscreen);
1312
1313 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1314 pipe_mutex_destroy(rscreen->aux_context_lock);
1315 rscreen->aux_context->destroy(rscreen->aux_context);
1316
1317 slab_destroy_parent(&rscreen->pool_transfers);
1318
1319 rscreen->ws->destroy(rscreen->ws);
1320 FREE(rscreen);
1321 }
1322
1323 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1324 unsigned processor)
1325 {
1326 switch (processor) {
1327 case PIPE_SHADER_VERTEX:
1328 return (rscreen->debug_flags & DBG_VS) != 0;
1329 case PIPE_SHADER_TESS_CTRL:
1330 return (rscreen->debug_flags & DBG_TCS) != 0;
1331 case PIPE_SHADER_TESS_EVAL:
1332 return (rscreen->debug_flags & DBG_TES) != 0;
1333 case PIPE_SHADER_GEOMETRY:
1334 return (rscreen->debug_flags & DBG_GS) != 0;
1335 case PIPE_SHADER_FRAGMENT:
1336 return (rscreen->debug_flags & DBG_PS) != 0;
1337 case PIPE_SHADER_COMPUTE:
1338 return (rscreen->debug_flags & DBG_CS) != 0;
1339 default:
1340 return false;
1341 }
1342 }
1343
1344 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1345 {
1346 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1347 r600_can_dump_shader(rscreen, processor);
1348 }
1349
1350 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1351 uint64_t offset, uint64_t size, unsigned value)
1352 {
1353 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1354
1355 pipe_mutex_lock(rscreen->aux_context_lock);
1356 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1357 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1358 pipe_mutex_unlock(rscreen->aux_context_lock);
1359 }