src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
  43 {
  44         /* The number of dwords we already used in the DMA so far. */
  45         num_dw += ctx->rings.dma.cs->cdw;
  46         /* Flush if there's not enough space. */
  47         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  48                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  49         }
  50 }
  51
  52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  53 {
  54 }
  55
  56 static void r600_flush_dma_ring(void *ctx, unsigned flags)
  57 {
  58         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  59         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
  60
  61         if (!cs->cdw) {
  62                 return;
  63         }
  64
  65         rctx->rings.dma.flushing = true;
  66         rctx->ws->cs_flush(cs, flags, 0);
  67         rctx->rings.dma.flushing = false;
  68 }
  69
  70 bool r600_common_context_init(struct r600_common_context *rctx,
  71                               struct r600_common_screen *rscreen)
  72 {
  73         util_slab_create(&rctx->pool_transfers,
  74                          sizeof(struct r600_transfer), 64,
  75                          UTIL_SLAB_SINGLETHREADED);
  76
  77         rctx->screen = rscreen;
  78         rctx->ws = rscreen->ws;
  79         rctx->family = rscreen->family;
  80         rctx->chip_class = rscreen->chip_class;
  81         rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
  82
  83         rctx->b.transfer_map = u_transfer_map_vtbl;
  84         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
  85         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
  86         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
  87         rctx->b.memory_barrier = r600_memory_barrier;
  88
  89         r600_init_context_texture_functions(rctx);
  90         r600_streamout_init(rctx);
  91         r600_query_init(rctx);
  92
  93         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
  94                                                                0, PIPE_USAGE_DEFAULT, TRUE);
  95         if (!rctx->allocator_so_filled_size)
  96                 return false;
  97
  98         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
  99                                         PIPE_BIND_INDEX_BUFFER |
 100                                         PIPE_BIND_CONSTANT_BUFFER);
 101         if (!rctx->uploader)
 102                 return false;
 103
 104         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 105                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 106                                                          r600_flush_dma_ring,
 107                                                          rctx, NULL);
 108                 rctx->rings.dma.flush = r600_flush_dma_ring;
 109         }
 110
 111         return true;
 112 }
 113
 114 void r600_common_context_cleanup(struct r600_common_context *rctx)
 115 {
 116         if (rctx->rings.gfx.cs) {
 117                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 118         }
 119         if (rctx->rings.dma.cs) {
 120                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 121         }
 122
 123         if (rctx->uploader) {
 124                 u_upload_destroy(rctx->uploader);
 125         }
 126
 127         util_slab_destroy(&rctx->pool_transfers);
 128
 129         if (rctx->allocator_so_filled_size) {
 130                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 131         }
 132 }
 133
 134 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 135 {
 136         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 137         struct r600_resource *rr = (struct r600_resource *)r;
 138
 139         if (r == NULL) {
 140                 return;
 141         }
 142
 143         /*
 144          * The idea is to compute a gross estimate of memory requirement of
 145          * each draw call. After each draw call, memory will be precisely
 146          * accounted. So the uncertainty is only on the current draw call.
 147          * In practice this gave very good estimate (+/- 10% of the target
 148          * memory limit).
 149          */
 150         if (rr->domains & RADEON_DOMAIN_GTT) {
 151                 rctx->gtt += rr->buf->size;
 152         }
 153         if (rr->domains & RADEON_DOMAIN_VRAM) {
 154                 rctx->vram += rr->buf->size;
 155         }
 156 }
 157
 158 /*
 159  * pipe_screen
 160  */
 161
 162 static const struct debug_named_value common_debug_options[] = {
 163         /* logging */
 164         { "tex", DBG_TEX, "Print texture info" },
 165         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 166         { "compute", DBG_COMPUTE, "Print compute info" },
 167         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 168         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 169
 170         /* features */
 171         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 172
 173         /* shaders */
 174         { "fs", DBG_FS, "Print fetch shaders" },
 175         { "vs", DBG_VS, "Print vertex shaders" },
 176         { "gs", DBG_GS, "Print geometry shaders" },
 177         { "ps", DBG_PS, "Print pixel shaders" },
 178         { "cs", DBG_CS, "Print compute shaders" },
 179
 180         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 181         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 182         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 183
 184         DEBUG_NAMED_VALUE_END /* must be last */
 185 };
 186
 187 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 188 {
 189         return "X.Org";
 190 }
 191
 192 static const char* r600_get_name(struct pipe_screen* pscreen)
 193 {
 194         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 195
 196         switch (rscreen->family) {
 197         case CHIP_R600: return "AMD R600";
 198         case CHIP_RV610: return "AMD RV610";
 199         case CHIP_RV630: return "AMD RV630";
 200         case CHIP_RV670: return "AMD RV670";
 201         case CHIP_RV620: return "AMD RV620";
 202         case CHIP_RV635: return "AMD RV635";
 203         case CHIP_RS780: return "AMD RS780";
 204         case CHIP_RS880: return "AMD RS880";
 205         case CHIP_RV770: return "AMD RV770";
 206         case CHIP_RV730: return "AMD RV730";
 207         case CHIP_RV710: return "AMD RV710";
 208         case CHIP_RV740: return "AMD RV740";
 209         case CHIP_CEDAR: return "AMD CEDAR";
 210         case CHIP_REDWOOD: return "AMD REDWOOD";
 211         case CHIP_JUNIPER: return "AMD JUNIPER";
 212         case CHIP_CYPRESS: return "AMD CYPRESS";
 213         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 214         case CHIP_PALM: return "AMD PALM";
 215         case CHIP_SUMO: return "AMD SUMO";
 216         case CHIP_SUMO2: return "AMD SUMO2";
 217         case CHIP_BARTS: return "AMD BARTS";
 218         case CHIP_TURKS: return "AMD TURKS";
 219         case CHIP_CAICOS: return "AMD CAICOS";
 220         case CHIP_CAYMAN: return "AMD CAYMAN";
 221         case CHIP_ARUBA: return "AMD ARUBA";
 222         case CHIP_TAHITI: return "AMD TAHITI";
 223         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 224         case CHIP_VERDE: return "AMD CAPE VERDE";
 225         case CHIP_OLAND: return "AMD OLAND";
 226         case CHIP_HAINAN: return "AMD HAINAN";
 227         case CHIP_BONAIRE: return "AMD BONAIRE";
 228         case CHIP_KAVERI: return "AMD KAVERI";
 229         case CHIP_KABINI: return "AMD KABINI";
 230         case CHIP_HAWAII: return "AMD HAWAII";
 231         default: return "AMD unknown";
 232         }
 233 }
 234
 235 static float r600_get_paramf(struct pipe_screen* pscreen,
 236                              enum pipe_capf param)
 237 {
 238         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 239
 240         switch (param) {
 241         case PIPE_CAPF_MAX_LINE_WIDTH:
 242         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 243         case PIPE_CAPF_MAX_POINT_WIDTH:
 244         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 245                 if (rscreen->family >= CHIP_CEDAR)
 246                         return 16384.0f;
 247                 else
 248                         return 8192.0f;
 249         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 250                 return 16.0f;
 251         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 252                 return 16.0f;
 253         case PIPE_CAPF_GUARD_BAND_LEFT:
 254         case PIPE_CAPF_GUARD_BAND_TOP:
 255         case PIPE_CAPF_GUARD_BAND_RIGHT:
 256         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 257                 return 0.0f;
 258         }
 259         return 0.0f;
 260 }
 261
 262 static int r600_get_video_param(struct pipe_screen *screen,
 263                                 enum pipe_video_profile profile,
 264                                 enum pipe_video_entrypoint entrypoint,
 265                                 enum pipe_video_cap param)
 266 {
 267         switch (param) {
 268         case PIPE_VIDEO_CAP_SUPPORTED:
 269                 return vl_profile_supported(screen, profile, entrypoint);
 270         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 271                 return 1;
 272         case PIPE_VIDEO_CAP_MAX_WIDTH:
 273         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 274                 return vl_video_buffer_max_size(screen);
 275         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 276                 return PIPE_FORMAT_NV12;
 277         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 278                 return false;
 279         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 280                 return false;
 281         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 282                 return true;
 283         case PIPE_VIDEO_CAP_MAX_LEVEL:
 284                 return vl_level_supported(screen, profile);
 285         default:
 286                 return 0;
 287         }
 288 }
 289
 290 const char *r600_get_llvm_processor_name(enum radeon_family family)
 291 {
 292         switch (family) {
 293         case CHIP_R600:
 294         case CHIP_RV630:
 295         case CHIP_RV635:
 296         case CHIP_RV670:
 297                 return "r600";
 298         case CHIP_RV610:
 299         case CHIP_RV620:
 300         case CHIP_RS780:
 301         case CHIP_RS880:
 302                 return "rs880";
 303         case CHIP_RV710:
 304                 return "rv710";
 305         case CHIP_RV730:
 306                 return "rv730";
 307         case CHIP_RV740:
 308         case CHIP_RV770:
 309                 return "rv770";
 310         case CHIP_PALM:
 311         case CHIP_CEDAR:
 312                 return "cedar";
 313         case CHIP_SUMO:
 314         case CHIP_SUMO2:
 315                 return "sumo";
 316         case CHIP_REDWOOD:
 317                 return "redwood";
 318         case CHIP_JUNIPER:
 319                 return "juniper";
 320         case CHIP_HEMLOCK:
 321         case CHIP_CYPRESS:
 322                 return "cypress";
 323         case CHIP_BARTS:
 324                 return "barts";
 325         case CHIP_TURKS:
 326                 return "turks";
 327         case CHIP_CAICOS:
 328                 return "caicos";
 329         case CHIP_CAYMAN:
 330         case CHIP_ARUBA:
 331                 return "cayman";
 332
 333         case CHIP_TAHITI: return "tahiti";
 334         case CHIP_PITCAIRN: return "pitcairn";
 335         case CHIP_VERDE: return "verde";
 336         case CHIP_OLAND: return "oland";
 337 #if HAVE_LLVM <= 0x0303
 338         default:
 339                 fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
 340                         __func__, family);
 341                 return "SI";
 342 #else
 343         case CHIP_HAINAN: return "hainan";
 344         case CHIP_BONAIRE: return "bonaire";
 345         case CHIP_KABINI: return "kabini";
 346         case CHIP_KAVERI: return "kaveri";
 347         case CHIP_HAWAII: return "hawaii";
 348         default: return "";
 349 #endif
 350         }
 351 }
 352
 353 static int r600_get_compute_param(struct pipe_screen *screen,
 354         enum pipe_compute_cap param,
 355         void *ret)
 356 {
 357         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 358
 359         //TODO: select these params by asic
 360         switch (param) {
 361         case PIPE_COMPUTE_CAP_IR_TARGET: {
 362                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 363                 if (ret) {
 364                         sprintf(ret, "%s-r600--", gpu);
 365                 }
 366                 return (8 + strlen(gpu)) * sizeof(char);
 367         }
 368         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 369                 if (ret) {
 370                         uint64_t *grid_dimension = ret;
 371                         grid_dimension[0] = 3;
 372                 }
 373                 return 1 * sizeof(uint64_t);
 374
 375         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 376                 if (ret) {
 377                         uint64_t *grid_size = ret;
 378                         grid_size[0] = 65535;
 379                         grid_size[1] = 65535;
 380                         grid_size[2] = 1;
 381                 }
 382                 return 3 * sizeof(uint64_t) ;
 383
 384         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 385                 if (ret) {
 386                         uint64_t *block_size = ret;
 387                         block_size[0] = 256;
 388                         block_size[1] = 256;
 389                         block_size[2] = 256;
 390                 }
 391                 return 3 * sizeof(uint64_t);
 392
 393         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 394                 if (ret) {
 395                         uint64_t *max_threads_per_block = ret;
 396                         *max_threads_per_block = 256;
 397                 }
 398                 return sizeof(uint64_t);
 399
 400         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 401                 if (ret) {
 402                         uint64_t *max_global_size = ret;
 403                         /* XXX: This is what the proprietary driver reports, we
 404                          * may want to use a different value. */
 405                         /* XXX: Not sure what to put here for SI. */
 406                         if (rscreen->chip_class >= SI)
 407                                 *max_global_size = 2000000000;
 408                         else
 409                                 *max_global_size = 201326592;
 410                 }
 411                 return sizeof(uint64_t);
 412
 413         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 414                 if (ret) {
 415                         uint64_t *max_local_size = ret;
 416                         /* Value reported by the closed source driver. */
 417                         *max_local_size = 32768;
 418                 }
 419                 return sizeof(uint64_t);
 420
 421         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 422                 if (ret) {
 423                         uint64_t *max_input_size = ret;
 424                         /* Value reported by the closed source driver. */
 425                         *max_input_size = 1024;
 426                 }
 427                 return sizeof(uint64_t);
 428
 429         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 430                 if (ret) {
 431                         uint64_t max_global_size;
 432                         uint64_t *max_mem_alloc_size = ret;
 433                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 434                         /* OpenCL requres this value be at least
 435                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 436                          * I'm really not sure what value to report here, but
 437                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 438                          */
 439                         *max_mem_alloc_size = max_global_size / 4;
 440                 }
 441                 return sizeof(uint64_t);
 442
 443         default:
 444                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 445                 return 0;
 446         }
 447 }
 448
 449 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 450 {
 451         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 452
 453         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 454                         rscreen->info.r600_clock_crystal_freq;
 455 }
 456
 457 static int r600_get_driver_query_info(struct pipe_screen *screen,
 458                                       unsigned index,
 459                                       struct pipe_driver_query_info *info)
 460 {
 461         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 462         struct pipe_driver_query_info list[] = {
 463                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 464                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 465                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 466                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 467                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 468                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 469                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 470                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 471         };
 472
 473         if (!info)
 474                 return Elements(list);
 475
 476         if (index >= Elements(list))
 477                 return 0;
 478
 479         *info = list[index];
 480         return 1;
 481 }
 482
 483 static void r600_fence_reference(struct pipe_screen *screen,
 484                                  struct pipe_fence_handle **ptr,
 485                                  struct pipe_fence_handle *fence)
 486 {
 487         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 488
 489         rws->fence_reference(ptr, fence);
 490 }
 491
 492 static boolean r600_fence_signalled(struct pipe_screen *screen,
 493                                     struct pipe_fence_handle *fence)
 494 {
 495         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 496
 497         return rws->fence_wait(rws, fence, 0);
 498 }
 499
 500 static boolean r600_fence_finish(struct pipe_screen *screen,
 501                                  struct pipe_fence_handle *fence,
 502                                  uint64_t timeout)
 503 {
 504         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 505
 506         return rws->fence_wait(rws, fence, timeout);
 507 }
 508
 509 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 510                                   uint32_t tiling_config)
 511 {
 512         switch ((tiling_config & 0xe) >> 1) {
 513         case 0:
 514                 rscreen->tiling_info.num_channels = 1;
 515                 break;
 516         case 1:
 517                 rscreen->tiling_info.num_channels = 2;
 518                 break;
 519         case 2:
 520                 rscreen->tiling_info.num_channels = 4;
 521                 break;
 522         case 3:
 523                 rscreen->tiling_info.num_channels = 8;
 524                 break;
 525         default:
 526                 return false;
 527         }
 528
 529         switch ((tiling_config & 0x30) >> 4) {
 530         case 0:
 531                 rscreen->tiling_info.num_banks = 4;
 532                 break;
 533         case 1:
 534                 rscreen->tiling_info.num_banks = 8;
 535                 break;
 536         default:
 537                 return false;
 538
 539         }
 540         switch ((tiling_config & 0xc0) >> 6) {
 541         case 0:
 542                 rscreen->tiling_info.group_bytes = 256;
 543                 break;
 544         case 1:
 545                 rscreen->tiling_info.group_bytes = 512;
 546                 break;
 547         default:
 548                 return false;
 549         }
 550         return true;
 551 }
 552
 553 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 554                                        uint32_t tiling_config)
 555 {
 556         switch (tiling_config & 0xf) {
 557         case 0:
 558                 rscreen->tiling_info.num_channels = 1;
 559                 break;
 560         case 1:
 561                 rscreen->tiling_info.num_channels = 2;
 562                 break;
 563         case 2:
 564                 rscreen->tiling_info.num_channels = 4;
 565                 break;
 566         case 3:
 567                 rscreen->tiling_info.num_channels = 8;
 568                 break;
 569         default:
 570                 return false;
 571         }
 572
 573         switch ((tiling_config & 0xf0) >> 4) {
 574         case 0:
 575                 rscreen->tiling_info.num_banks = 4;
 576                 break;
 577         case 1:
 578                 rscreen->tiling_info.num_banks = 8;
 579                 break;
 580         case 2:
 581                 rscreen->tiling_info.num_banks = 16;
 582                 break;
 583         default:
 584                 return false;
 585         }
 586
 587         switch ((tiling_config & 0xf00) >> 8) {
 588         case 0:
 589                 rscreen->tiling_info.group_bytes = 256;
 590                 break;
 591         case 1:
 592                 rscreen->tiling_info.group_bytes = 512;
 593                 break;
 594         default:
 595                 return false;
 596         }
 597         return true;
 598 }
 599
 600 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 601 {
 602         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 603
 604         /* set default group bytes, overridden by tiling info ioctl */
 605         if (rscreen->chip_class <= R700) {
 606                 rscreen->tiling_info.group_bytes = 256;
 607         } else {
 608                 rscreen->tiling_info.group_bytes = 512;
 609         }
 610
 611         if (!tiling_config)
 612                 return true;
 613
 614         if (rscreen->chip_class <= R700) {
 615                 return r600_interpret_tiling(rscreen, tiling_config);
 616         } else {
 617                 return evergreen_interpret_tiling(rscreen, tiling_config);
 618         }
 619 }
 620
 621 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 622                                                   const struct pipe_resource *templ)
 623 {
 624         if (templ->target == PIPE_BUFFER) {
 625                 return r600_buffer_create(screen, templ, 4096);
 626         } else {
 627                 return r600_texture_create(screen, templ);
 628         }
 629 }
 630
 631 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 632                              struct radeon_winsys *ws)
 633 {
 634         ws->query_info(ws, &rscreen->info);
 635
 636         rscreen->b.get_name = r600_get_name;
 637         rscreen->b.get_vendor = r600_get_vendor;
 638         rscreen->b.get_compute_param = r600_get_compute_param;
 639         rscreen->b.get_paramf = r600_get_paramf;
 640         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 641         rscreen->b.get_timestamp = r600_get_timestamp;
 642         rscreen->b.fence_finish = r600_fence_finish;
 643         rscreen->b.fence_reference = r600_fence_reference;
 644         rscreen->b.fence_signalled = r600_fence_signalled;
 645         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 646
 647         if (rscreen->info.has_uvd) {
 648                 rscreen->b.get_video_param = rvid_get_video_param;
 649                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 650         } else {
 651                 rscreen->b.get_video_param = r600_get_video_param;
 652                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 653         }
 654
 655         r600_init_screen_texture_functions(rscreen);
 656
 657         rscreen->ws = ws;
 658         rscreen->family = rscreen->info.family;
 659         rscreen->chip_class = rscreen->info.chip_class;
 660         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 661
 662         if (!r600_init_tiling(rscreen)) {
 663                 return false;
 664         }
 665         util_format_s3tc_init();
 666         pipe_mutex_init(rscreen->aux_context_lock);
 667
 668         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 669                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 670                                                                                 PIPE_BIND_CUSTOM,
 671                                                                                 PIPE_USAGE_STAGING,
 672                                                                                 4096);
 673                 if (rscreen->trace_bo) {
 674                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 675                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 676                 }
 677         }
 678
 679         return true;
 680 }
 681
 682 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 683 {
 684         pipe_mutex_destroy(rscreen->aux_context_lock);
 685         rscreen->aux_context->destroy(rscreen->aux_context);
 686
 687         if (rscreen->trace_bo) {
 688                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 689                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 690         }
 691
 692         rscreen->ws->destroy(rscreen->ws);
 693         FREE(rscreen);
 694 }
 695
 696 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 697 {
 698         struct tgsi_parse_context parse;
 699
 700         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 701                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 702                 return ~0;
 703         }
 704         return parse.FullHeader.Processor.Processor;
 705 }
 706
 707 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 708                           const struct tgsi_token *tokens)
 709 {
 710         /* Compute shader don't have tgsi_tokens */
 711         if (!tokens)
 712                 return (rscreen->debug_flags & DBG_CS) != 0;
 713
 714         switch (tgsi_get_processor_type(tokens)) {
 715         case TGSI_PROCESSOR_VERTEX:
 716                 return (rscreen->debug_flags & DBG_VS) != 0;
 717         case TGSI_PROCESSOR_GEOMETRY:
 718                 return (rscreen->debug_flags & DBG_GS) != 0;
 719         case TGSI_PROCESSOR_FRAGMENT:
 720                 return (rscreen->debug_flags & DBG_PS) != 0;
 721         case TGSI_PROCESSOR_COMPUTE:
 722                 return (rscreen->debug_flags & DBG_CS) != 0;
 723         default:
 724                 return false;
 725         }
 726 }
 727
 728 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 729                               unsigned offset, unsigned size, unsigned value)
 730 {
 731         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 732
 733         pipe_mutex_lock(rscreen->aux_context_lock);
 734         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 735         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 736         pipe_mutex_unlock(rscreen->aux_context_lock);
 737 }