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gallium/radeon: use unflushed fences for deferred flushes (v2)
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
52 struct {
53 struct r600_common_context *ctx;
54 unsigned ib_index;
55 } gfx_unflushed;
56 };
57
58 /*
59 * shader binary helpers.
60 */
61 void radeon_shader_binary_init(struct radeon_shader_binary *b)
62 {
63 memset(b, 0, sizeof(*b));
64 }
65
66 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
67 {
68 if (!b)
69 return;
70 FREE(b->code);
71 FREE(b->config);
72 FREE(b->rodata);
73 FREE(b->global_symbol_offsets);
74 FREE(b->relocs);
75 FREE(b->disasm_string);
76 FREE(b->llvm_ir_string);
77 }
78
79 /*
80 * pipe_context
81 */
82
83 void r600_draw_rectangle(struct blitter_context *blitter,
84 int x1, int y1, int x2, int y2, float depth,
85 enum blitter_attrib_type type,
86 const union pipe_color_union *attrib)
87 {
88 struct r600_common_context *rctx =
89 (struct r600_common_context*)util_blitter_get_pipe(blitter);
90 struct pipe_viewport_state viewport;
91 struct pipe_resource *buf = NULL;
92 unsigned offset = 0;
93 float *vb;
94
95 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
96 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
97 return;
98 }
99
100 /* Some operations (like color resolve on r6xx) don't work
101 * with the conventional primitive types.
102 * One that works is PT_RECTLIST, which we use here. */
103
104 /* setup viewport */
105 viewport.scale[0] = 1.0f;
106 viewport.scale[1] = 1.0f;
107 viewport.scale[2] = 1.0f;
108 viewport.translate[0] = 0.0f;
109 viewport.translate[1] = 0.0f;
110 viewport.translate[2] = 0.0f;
111 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
112
113 /* Upload vertices. The hw rectangle has only 3 vertices,
114 * I guess the 4th one is derived from the first 3.
115 * The vertex specification should match u_blitter's vertex element state. */
116 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
117 if (!buf)
118 return;
119
120 vb[0] = x1;
121 vb[1] = y1;
122 vb[2] = depth;
123 vb[3] = 1;
124
125 vb[8] = x1;
126 vb[9] = y2;
127 vb[10] = depth;
128 vb[11] = 1;
129
130 vb[16] = x2;
131 vb[17] = y1;
132 vb[18] = depth;
133 vb[19] = 1;
134
135 if (attrib) {
136 memcpy(vb+4, attrib->f, sizeof(float)*4);
137 memcpy(vb+12, attrib->f, sizeof(float)*4);
138 memcpy(vb+20, attrib->f, sizeof(float)*4);
139 }
140
141 /* draw */
142 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
143 R600_PRIM_RECTANGLE_LIST, 3, 2);
144 pipe_resource_reference(&buf, NULL);
145 }
146
147 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
148 struct r600_resource *dst, struct r600_resource *src)
149 {
150 uint64_t vram = 0, gtt = 0;
151
152 if (dst) {
153 vram += dst->vram_usage;
154 gtt += dst->gart_usage;
155 }
156 if (src) {
157 vram += src->vram_usage;
158 gtt += src->gart_usage;
159 }
160
161 /* Flush the GFX IB if DMA depends on it. */
162 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
163 ((dst &&
164 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
165 RADEON_USAGE_READWRITE)) ||
166 (src &&
167 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
168 RADEON_USAGE_WRITE))))
169 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
170
171 /* Flush if there's not enough space, or if the memory usage per IB
172 * is too large.
173 */
174 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
175 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
176 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
177 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
178 }
179
180 /* If GPUVM is not supported, the CS checker needs 2 entries
181 * in the buffer list per packet, which has to be done manually.
182 */
183 if (ctx->screen->info.has_virtual_memory) {
184 if (dst)
185 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
186 RADEON_USAGE_WRITE,
187 RADEON_PRIO_SDMA_BUFFER);
188 if (src)
189 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
190 RADEON_USAGE_READ,
191 RADEON_PRIO_SDMA_BUFFER);
192 }
193 }
194
195 /* This is required to prevent read-after-write hazards. */
196 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
197 {
198 struct radeon_winsys_cs *cs = rctx->dma.cs;
199
200 /* done at the end of DMA calls, so increment this. */
201 rctx->num_dma_calls++;
202
203 /* IBs using too little memory are limited by the IB submission overhead.
204 * IBs using too much memory are limited by the kernel/TTM overhead.
205 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
206 *
207 * This heuristic makes sure that DMA requests are executed
208 * very soon after the call is made and lowers memory usage.
209 * It improves texture upload performance by keeping the DMA
210 * engine busy while uploads are being submitted.
211 */
212 if (cs->used_vram + cs->used_gart > 64 * 1024 * 1024) {
213 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
214 return;
215 }
216
217 r600_need_dma_space(rctx, 1, NULL, NULL);
218
219 if (!radeon_emitted(cs, 0)) /* empty queue */
220 return;
221
222 /* NOP waits for idle on Evergreen and later. */
223 if (rctx->chip_class >= CIK)
224 radeon_emit(cs, 0x00000000); /* NOP */
225 else if (rctx->chip_class >= EVERGREEN)
226 radeon_emit(cs, 0xf0000000); /* NOP */
227 else {
228 /* TODO: R600-R700 should use the FENCE packet.
229 * CS checker support is required. */
230 }
231 }
232
233 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
234 {
235 }
236
237 void r600_preflush_suspend_features(struct r600_common_context *ctx)
238 {
239 /* suspend queries */
240 if (!LIST_IS_EMPTY(&ctx->active_queries))
241 r600_suspend_queries(ctx);
242
243 ctx->streamout.suspended = false;
244 if (ctx->streamout.begin_emitted) {
245 r600_emit_streamout_end(ctx);
246 ctx->streamout.suspended = true;
247 }
248 }
249
250 void r600_postflush_resume_features(struct r600_common_context *ctx)
251 {
252 if (ctx->streamout.suspended) {
253 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
254 r600_streamout_buffers_dirty(ctx);
255 }
256
257 /* resume queries */
258 if (!LIST_IS_EMPTY(&ctx->active_queries))
259 r600_resume_queries(ctx);
260 }
261
262 static void r600_flush_from_st(struct pipe_context *ctx,
263 struct pipe_fence_handle **fence,
264 unsigned flags)
265 {
266 struct pipe_screen *screen = ctx->screen;
267 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
268 unsigned rflags = 0;
269 struct pipe_fence_handle *gfx_fence = NULL;
270 struct pipe_fence_handle *sdma_fence = NULL;
271 bool deferred_fence = false;
272
273 if (flags & PIPE_FLUSH_END_OF_FRAME)
274 rflags |= RADEON_FLUSH_END_OF_FRAME;
275 if (flags & PIPE_FLUSH_DEFERRED)
276 rflags |= RADEON_FLUSH_ASYNC;
277
278 if (rctx->dma.cs) {
279 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
280 }
281
282 /* Instead of flushing, create a deferred fence. Constraints:
283 * - The state tracker must allow a deferred flush.
284 * - The state tracker must request a fence.
285 * Thread safety in fence_finish must be ensured by the state tracker.
286 */
287 if (flags & PIPE_FLUSH_DEFERRED && fence) {
288 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
289 deferred_fence = true;
290 } else {
291 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
292 }
293
294 /* Both engines can signal out of order, so we need to keep both fences. */
295 if (gfx_fence || sdma_fence) {
296 struct r600_multi_fence *multi_fence =
297 CALLOC_STRUCT(r600_multi_fence);
298 if (!multi_fence)
299 return;
300
301 multi_fence->reference.count = 1;
302 multi_fence->gfx = gfx_fence;
303 multi_fence->sdma = sdma_fence;
304
305 if (deferred_fence) {
306 multi_fence->gfx_unflushed.ctx = rctx;
307 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
308 }
309
310 screen->fence_reference(screen, fence, NULL);
311 *fence = (struct pipe_fence_handle*)multi_fence;
312 }
313 }
314
315 static void r600_flush_dma_ring(void *ctx, unsigned flags,
316 struct pipe_fence_handle **fence)
317 {
318 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
319 struct radeon_winsys_cs *cs = rctx->dma.cs;
320 struct radeon_saved_cs saved;
321 bool check_vm =
322 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
323 rctx->check_vm_faults;
324
325 if (!radeon_emitted(cs, 0)) {
326 if (fence)
327 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
328 return;
329 }
330
331 if (check_vm)
332 radeon_save_cs(rctx->ws, cs, &saved);
333
334 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
335 if (fence)
336 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
337
338 if (check_vm) {
339 /* Use conservative timeout 800ms, after which we won't wait any
340 * longer and assume the GPU is hung.
341 */
342 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
343
344 rctx->check_vm_faults(rctx, &saved, RING_DMA);
345 radeon_clear_saved_cs(&saved);
346 }
347 }
348
349 /**
350 * Store a linearized copy of all chunks of \p cs together with the buffer
351 * list in \p saved.
352 */
353 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
354 struct radeon_saved_cs *saved)
355 {
356 void *buf;
357 unsigned i;
358
359 /* Save the IB chunks. */
360 saved->num_dw = cs->prev_dw + cs->current.cdw;
361 saved->ib = MALLOC(4 * saved->num_dw);
362 if (!saved->ib)
363 goto oom;
364
365 buf = saved->ib;
366 for (i = 0; i < cs->num_prev; ++i) {
367 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
368 buf += cs->prev[i].cdw;
369 }
370 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
371
372 /* Save the buffer list. */
373 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
374 saved->bo_list = CALLOC(saved->bo_count,
375 sizeof(saved->bo_list[0]));
376 if (!saved->bo_list) {
377 FREE(saved->ib);
378 goto oom;
379 }
380 ws->cs_get_buffer_list(cs, saved->bo_list);
381
382 return;
383
384 oom:
385 fprintf(stderr, "%s: out of memory\n", __func__);
386 memset(saved, 0, sizeof(*saved));
387 }
388
389 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
390 {
391 FREE(saved->ib);
392 FREE(saved->bo_list);
393
394 memset(saved, 0, sizeof(*saved));
395 }
396
397 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
398 {
399 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
400 unsigned latest = rctx->ws->query_value(rctx->ws,
401 RADEON_GPU_RESET_COUNTER);
402
403 if (rctx->gpu_reset_counter == latest)
404 return PIPE_NO_RESET;
405
406 rctx->gpu_reset_counter = latest;
407 return PIPE_UNKNOWN_CONTEXT_RESET;
408 }
409
410 static void r600_set_debug_callback(struct pipe_context *ctx,
411 const struct pipe_debug_callback *cb)
412 {
413 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
414
415 if (cb)
416 rctx->debug = *cb;
417 else
418 memset(&rctx->debug, 0, sizeof(rctx->debug));
419 }
420
421 bool r600_common_context_init(struct r600_common_context *rctx,
422 struct r600_common_screen *rscreen,
423 unsigned context_flags)
424 {
425 util_slab_create(&rctx->pool_transfers,
426 sizeof(struct r600_transfer), 64,
427 UTIL_SLAB_SINGLETHREADED);
428
429 rctx->screen = rscreen;
430 rctx->ws = rscreen->ws;
431 rctx->family = rscreen->family;
432 rctx->chip_class = rscreen->chip_class;
433
434 if (rscreen->chip_class >= CIK)
435 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
436 else if (rscreen->chip_class >= EVERGREEN)
437 rctx->max_db = 8;
438 else
439 rctx->max_db = 4;
440
441 rctx->b.invalidate_resource = r600_invalidate_resource;
442 rctx->b.transfer_map = u_transfer_map_vtbl;
443 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
444 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
445 rctx->b.texture_subdata = u_default_texture_subdata;
446 rctx->b.memory_barrier = r600_memory_barrier;
447 rctx->b.flush = r600_flush_from_st;
448 rctx->b.set_debug_callback = r600_set_debug_callback;
449
450 /* evergreen_compute.c has a special codepath for global buffers.
451 * Everything else can use the direct path.
452 */
453 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
454 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
455 rctx->b.buffer_subdata = u_default_buffer_subdata;
456 else
457 rctx->b.buffer_subdata = r600_buffer_subdata;
458
459 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
460 rctx->b.get_device_reset_status = r600_get_reset_status;
461 rctx->gpu_reset_counter =
462 rctx->ws->query_value(rctx->ws,
463 RADEON_GPU_RESET_COUNTER);
464 }
465
466 LIST_INITHEAD(&rctx->texture_buffers);
467
468 r600_init_context_texture_functions(rctx);
469 r600_init_viewport_functions(rctx);
470 r600_streamout_init(rctx);
471 r600_query_init(rctx);
472 cayman_init_msaa(&rctx->b);
473
474 rctx->allocator_zeroed_memory =
475 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
476 0, PIPE_USAGE_DEFAULT, true);
477 if (!rctx->allocator_zeroed_memory)
478 return false;
479
480 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
481 PIPE_BIND_INDEX_BUFFER |
482 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
483 if (!rctx->uploader)
484 return false;
485
486 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
487 if (!rctx->ctx)
488 return false;
489
490 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
491 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
492 r600_flush_dma_ring,
493 rctx);
494 rctx->dma.flush = r600_flush_dma_ring;
495 }
496
497 return true;
498 }
499
500 void r600_common_context_cleanup(struct r600_common_context *rctx)
501 {
502 unsigned i,j;
503
504 /* Release DCC stats. */
505 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
506 assert(!rctx->dcc_stats[i].query_active);
507
508 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
509 if (rctx->dcc_stats[i].ps_stats[j])
510 rctx->b.destroy_query(&rctx->b,
511 rctx->dcc_stats[i].ps_stats[j]);
512
513 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
514 }
515
516 if (rctx->gfx.cs)
517 rctx->ws->cs_destroy(rctx->gfx.cs);
518 if (rctx->dma.cs)
519 rctx->ws->cs_destroy(rctx->dma.cs);
520 if (rctx->ctx)
521 rctx->ws->ctx_destroy(rctx->ctx);
522
523 if (rctx->uploader) {
524 u_upload_destroy(rctx->uploader);
525 }
526
527 util_slab_destroy(&rctx->pool_transfers);
528
529 if (rctx->allocator_zeroed_memory) {
530 u_suballocator_destroy(rctx->allocator_zeroed_memory);
531 }
532 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
533 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
534 }
535
536 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
537 {
538 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
539 struct r600_resource *rr = (struct r600_resource *)r;
540
541 if (!r) {
542 return;
543 }
544
545 /*
546 * The idea is to compute a gross estimate of memory requirement of
547 * each draw call. After each draw call, memory will be precisely
548 * accounted. So the uncertainty is only on the current draw call.
549 * In practice this gave very good estimate (+/- 10% of the target
550 * memory limit).
551 */
552 rctx->vram += rr->vram_usage;
553 rctx->gtt += rr->gart_usage;
554 }
555
556 /*
557 * pipe_screen
558 */
559
560 static const struct debug_named_value common_debug_options[] = {
561 /* logging */
562 { "tex", DBG_TEX, "Print texture info" },
563 { "compute", DBG_COMPUTE, "Print compute info" },
564 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
565 { "info", DBG_INFO, "Print driver information" },
566
567 /* shaders */
568 { "fs", DBG_FS, "Print fetch shaders" },
569 { "vs", DBG_VS, "Print vertex shaders" },
570 { "gs", DBG_GS, "Print geometry shaders" },
571 { "ps", DBG_PS, "Print pixel shaders" },
572 { "cs", DBG_CS, "Print compute shaders" },
573 { "tcs", DBG_TCS, "Print tessellation control shaders" },
574 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
575 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
576 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
577 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
578 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
579
580 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
581
582 /* features */
583 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
584 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
585 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
586 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
587 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
588 { "notiling", DBG_NO_TILING, "Disable tiling" },
589 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
590 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
591 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
592 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
593 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
594 { "nodcc", DBG_NO_DCC, "Disable DCC." },
595 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
596 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
597 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
598 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
599 { "noce", DBG_NO_CE, "Disable the constant engine"},
600 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
601 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
602
603 DEBUG_NAMED_VALUE_END /* must be last */
604 };
605
606 static const char* r600_get_vendor(struct pipe_screen* pscreen)
607 {
608 return "X.Org";
609 }
610
611 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
612 {
613 return "AMD";
614 }
615
616 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
617 {
618 switch (rscreen->info.family) {
619 case CHIP_R600: return "AMD R600";
620 case CHIP_RV610: return "AMD RV610";
621 case CHIP_RV630: return "AMD RV630";
622 case CHIP_RV670: return "AMD RV670";
623 case CHIP_RV620: return "AMD RV620";
624 case CHIP_RV635: return "AMD RV635";
625 case CHIP_RS780: return "AMD RS780";
626 case CHIP_RS880: return "AMD RS880";
627 case CHIP_RV770: return "AMD RV770";
628 case CHIP_RV730: return "AMD RV730";
629 case CHIP_RV710: return "AMD RV710";
630 case CHIP_RV740: return "AMD RV740";
631 case CHIP_CEDAR: return "AMD CEDAR";
632 case CHIP_REDWOOD: return "AMD REDWOOD";
633 case CHIP_JUNIPER: return "AMD JUNIPER";
634 case CHIP_CYPRESS: return "AMD CYPRESS";
635 case CHIP_HEMLOCK: return "AMD HEMLOCK";
636 case CHIP_PALM: return "AMD PALM";
637 case CHIP_SUMO: return "AMD SUMO";
638 case CHIP_SUMO2: return "AMD SUMO2";
639 case CHIP_BARTS: return "AMD BARTS";
640 case CHIP_TURKS: return "AMD TURKS";
641 case CHIP_CAICOS: return "AMD CAICOS";
642 case CHIP_CAYMAN: return "AMD CAYMAN";
643 case CHIP_ARUBA: return "AMD ARUBA";
644 case CHIP_TAHITI: return "AMD TAHITI";
645 case CHIP_PITCAIRN: return "AMD PITCAIRN";
646 case CHIP_VERDE: return "AMD CAPE VERDE";
647 case CHIP_OLAND: return "AMD OLAND";
648 case CHIP_HAINAN: return "AMD HAINAN";
649 case CHIP_BONAIRE: return "AMD BONAIRE";
650 case CHIP_KAVERI: return "AMD KAVERI";
651 case CHIP_KABINI: return "AMD KABINI";
652 case CHIP_HAWAII: return "AMD HAWAII";
653 case CHIP_MULLINS: return "AMD MULLINS";
654 case CHIP_TONGA: return "AMD TONGA";
655 case CHIP_ICELAND: return "AMD ICELAND";
656 case CHIP_CARRIZO: return "AMD CARRIZO";
657 case CHIP_FIJI: return "AMD FIJI";
658 case CHIP_POLARIS10: return "AMD POLARIS10";
659 case CHIP_POLARIS11: return "AMD POLARIS11";
660 case CHIP_STONEY: return "AMD STONEY";
661 default: return "AMD unknown";
662 }
663 }
664
665 static const char* r600_get_name(struct pipe_screen* pscreen)
666 {
667 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
668
669 return rscreen->renderer_string;
670 }
671
672 static float r600_get_paramf(struct pipe_screen* pscreen,
673 enum pipe_capf param)
674 {
675 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
676
677 switch (param) {
678 case PIPE_CAPF_MAX_LINE_WIDTH:
679 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
680 case PIPE_CAPF_MAX_POINT_WIDTH:
681 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
682 if (rscreen->family >= CHIP_CEDAR)
683 return 16384.0f;
684 else
685 return 8192.0f;
686 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
687 return 16.0f;
688 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
689 return 16.0f;
690 case PIPE_CAPF_GUARD_BAND_LEFT:
691 case PIPE_CAPF_GUARD_BAND_TOP:
692 case PIPE_CAPF_GUARD_BAND_RIGHT:
693 case PIPE_CAPF_GUARD_BAND_BOTTOM:
694 return 0.0f;
695 }
696 return 0.0f;
697 }
698
699 static int r600_get_video_param(struct pipe_screen *screen,
700 enum pipe_video_profile profile,
701 enum pipe_video_entrypoint entrypoint,
702 enum pipe_video_cap param)
703 {
704 switch (param) {
705 case PIPE_VIDEO_CAP_SUPPORTED:
706 return vl_profile_supported(screen, profile, entrypoint);
707 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
708 return 1;
709 case PIPE_VIDEO_CAP_MAX_WIDTH:
710 case PIPE_VIDEO_CAP_MAX_HEIGHT:
711 return vl_video_buffer_max_size(screen);
712 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
713 return PIPE_FORMAT_NV12;
714 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
715 return false;
716 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
717 return false;
718 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
719 return true;
720 case PIPE_VIDEO_CAP_MAX_LEVEL:
721 return vl_level_supported(screen, profile);
722 default:
723 return 0;
724 }
725 }
726
727 const char *r600_get_llvm_processor_name(enum radeon_family family)
728 {
729 switch (family) {
730 case CHIP_R600:
731 case CHIP_RV630:
732 case CHIP_RV635:
733 case CHIP_RV670:
734 return "r600";
735 case CHIP_RV610:
736 case CHIP_RV620:
737 case CHIP_RS780:
738 case CHIP_RS880:
739 return "rs880";
740 case CHIP_RV710:
741 return "rv710";
742 case CHIP_RV730:
743 return "rv730";
744 case CHIP_RV740:
745 case CHIP_RV770:
746 return "rv770";
747 case CHIP_PALM:
748 case CHIP_CEDAR:
749 return "cedar";
750 case CHIP_SUMO:
751 case CHIP_SUMO2:
752 return "sumo";
753 case CHIP_REDWOOD:
754 return "redwood";
755 case CHIP_JUNIPER:
756 return "juniper";
757 case CHIP_HEMLOCK:
758 case CHIP_CYPRESS:
759 return "cypress";
760 case CHIP_BARTS:
761 return "barts";
762 case CHIP_TURKS:
763 return "turks";
764 case CHIP_CAICOS:
765 return "caicos";
766 case CHIP_CAYMAN:
767 case CHIP_ARUBA:
768 return "cayman";
769
770 case CHIP_TAHITI: return "tahiti";
771 case CHIP_PITCAIRN: return "pitcairn";
772 case CHIP_VERDE: return "verde";
773 case CHIP_OLAND: return "oland";
774 case CHIP_HAINAN: return "hainan";
775 case CHIP_BONAIRE: return "bonaire";
776 case CHIP_KABINI: return "kabini";
777 case CHIP_KAVERI: return "kaveri";
778 case CHIP_HAWAII: return "hawaii";
779 case CHIP_MULLINS:
780 return "mullins";
781 case CHIP_TONGA: return "tonga";
782 case CHIP_ICELAND: return "iceland";
783 case CHIP_CARRIZO: return "carrizo";
784 #if HAVE_LLVM <= 0x0307
785 case CHIP_FIJI: return "tonga";
786 case CHIP_STONEY: return "carrizo";
787 #else
788 case CHIP_FIJI: return "fiji";
789 case CHIP_STONEY: return "stoney";
790 #endif
791 #if HAVE_LLVM <= 0x0308
792 case CHIP_POLARIS10: return "tonga";
793 case CHIP_POLARIS11: return "tonga";
794 #else
795 case CHIP_POLARIS10: return "polaris10";
796 case CHIP_POLARIS11: return "polaris11";
797 #endif
798 default: return "";
799 }
800 }
801
802 static int r600_get_compute_param(struct pipe_screen *screen,
803 enum pipe_shader_ir ir_type,
804 enum pipe_compute_cap param,
805 void *ret)
806 {
807 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
808
809 //TODO: select these params by asic
810 switch (param) {
811 case PIPE_COMPUTE_CAP_IR_TARGET: {
812 const char *gpu;
813 const char *triple;
814 if (rscreen->family <= CHIP_ARUBA) {
815 triple = "r600--";
816 } else {
817 triple = "amdgcn--";
818 }
819 switch(rscreen->family) {
820 /* Clang < 3.6 is missing Hainan in its list of
821 * GPUs, so we need to use the name of a similar GPU.
822 */
823 default:
824 gpu = r600_get_llvm_processor_name(rscreen->family);
825 break;
826 }
827 if (ret) {
828 sprintf(ret, "%s-%s", gpu, triple);
829 }
830 /* +2 for dash and terminating NIL byte */
831 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
832 }
833 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
834 if (ret) {
835 uint64_t *grid_dimension = ret;
836 grid_dimension[0] = 3;
837 }
838 return 1 * sizeof(uint64_t);
839
840 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
841 if (ret) {
842 uint64_t *grid_size = ret;
843 grid_size[0] = 65535;
844 grid_size[1] = 65535;
845 grid_size[2] = 65535;
846 }
847 return 3 * sizeof(uint64_t) ;
848
849 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
850 if (ret) {
851 uint64_t *block_size = ret;
852 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
853 ir_type == PIPE_SHADER_IR_TGSI) {
854 block_size[0] = 2048;
855 block_size[1] = 2048;
856 block_size[2] = 2048;
857 } else {
858 block_size[0] = 256;
859 block_size[1] = 256;
860 block_size[2] = 256;
861 }
862 }
863 return 3 * sizeof(uint64_t);
864
865 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
866 if (ret) {
867 uint64_t *max_threads_per_block = ret;
868 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
869 ir_type == PIPE_SHADER_IR_TGSI)
870 *max_threads_per_block = 2048;
871 else
872 *max_threads_per_block = 256;
873 }
874 return sizeof(uint64_t);
875
876 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
877 if (ret) {
878 uint64_t *max_global_size = ret;
879 uint64_t max_mem_alloc_size;
880
881 r600_get_compute_param(screen, ir_type,
882 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
883 &max_mem_alloc_size);
884
885 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
886 * 1/4 of the MAX_GLOBAL_SIZE. Since the
887 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
888 * make sure we never report more than
889 * 4 * MAX_MEM_ALLOC_SIZE.
890 */
891 *max_global_size = MIN2(4 * max_mem_alloc_size,
892 MAX2(rscreen->info.gart_size,
893 rscreen->info.vram_size));
894 }
895 return sizeof(uint64_t);
896
897 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
898 if (ret) {
899 uint64_t *max_local_size = ret;
900 /* Value reported by the closed source driver. */
901 *max_local_size = 32768;
902 }
903 return sizeof(uint64_t);
904
905 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
906 if (ret) {
907 uint64_t *max_input_size = ret;
908 /* Value reported by the closed source driver. */
909 *max_input_size = 1024;
910 }
911 return sizeof(uint64_t);
912
913 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
914 if (ret) {
915 uint64_t *max_mem_alloc_size = ret;
916
917 *max_mem_alloc_size = rscreen->info.max_alloc_size;
918 }
919 return sizeof(uint64_t);
920
921 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
922 if (ret) {
923 uint32_t *max_clock_frequency = ret;
924 *max_clock_frequency = rscreen->info.max_shader_clock;
925 }
926 return sizeof(uint32_t);
927
928 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
929 if (ret) {
930 uint32_t *max_compute_units = ret;
931 *max_compute_units = rscreen->info.num_good_compute_units;
932 }
933 return sizeof(uint32_t);
934
935 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
936 if (ret) {
937 uint32_t *images_supported = ret;
938 *images_supported = 0;
939 }
940 return sizeof(uint32_t);
941 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
942 break; /* unused */
943 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
944 if (ret) {
945 uint32_t *subgroup_size = ret;
946 *subgroup_size = r600_wavefront_size(rscreen->family);
947 }
948 return sizeof(uint32_t);
949 }
950
951 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
952 return 0;
953 }
954
955 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
956 {
957 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
958
959 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
960 rscreen->info.clock_crystal_freq;
961 }
962
963 static void r600_fence_reference(struct pipe_screen *screen,
964 struct pipe_fence_handle **dst,
965 struct pipe_fence_handle *src)
966 {
967 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
968 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
969 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
970
971 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
972 ws->fence_reference(&(*rdst)->gfx, NULL);
973 ws->fence_reference(&(*rdst)->sdma, NULL);
974 FREE(*rdst);
975 }
976 *rdst = rsrc;
977 }
978
979 static boolean r600_fence_finish(struct pipe_screen *screen,
980 struct pipe_context *ctx,
981 struct pipe_fence_handle *fence,
982 uint64_t timeout)
983 {
984 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
985 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
986 struct r600_common_context *rctx =
987 ctx ? (struct r600_common_context*)ctx : NULL;
988 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
989
990 if (rfence->sdma) {
991 if (!rws->fence_wait(rws, rfence->sdma, timeout))
992 return false;
993
994 /* Recompute the timeout after waiting. */
995 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
996 int64_t time = os_time_get_nano();
997 timeout = abs_timeout > time ? abs_timeout - time : 0;
998 }
999 }
1000
1001 if (!rfence->gfx)
1002 return true;
1003
1004 /* Flush the gfx IB if it hasn't been flushed yet. */
1005 if (rctx &&
1006 rfence->gfx_unflushed.ctx == rctx &&
1007 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1008 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1009 rfence->gfx_unflushed.ctx = NULL;
1010
1011 if (!timeout)
1012 return false;
1013
1014 /* Recompute the timeout after all that. */
1015 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1016 int64_t time = os_time_get_nano();
1017 timeout = abs_timeout > time ? abs_timeout - time : 0;
1018 }
1019 }
1020
1021 return rws->fence_wait(rws, rfence->gfx, timeout);
1022 }
1023
1024 static void r600_query_memory_info(struct pipe_screen *screen,
1025 struct pipe_memory_info *info)
1026 {
1027 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1028 struct radeon_winsys *ws = rscreen->ws;
1029 unsigned vram_usage, gtt_usage;
1030
1031 info->total_device_memory = rscreen->info.vram_size / 1024;
1032 info->total_staging_memory = rscreen->info.gart_size / 1024;
1033
1034 /* The real TTM memory usage is somewhat random, because:
1035 *
1036 * 1) TTM delays freeing memory, because it can only free it after
1037 * fences expire.
1038 *
1039 * 2) The memory usage can be really low if big VRAM evictions are
1040 * taking place, but the real usage is well above the size of VRAM.
1041 *
1042 * Instead, return statistics of this process.
1043 */
1044 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1045 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1046
1047 info->avail_device_memory =
1048 vram_usage <= info->total_device_memory ?
1049 info->total_device_memory - vram_usage : 0;
1050 info->avail_staging_memory =
1051 gtt_usage <= info->total_staging_memory ?
1052 info->total_staging_memory - gtt_usage : 0;
1053
1054 info->device_memory_evicted =
1055 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1056 /* Just return the number of evicted 64KB pages. */
1057 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1058 }
1059
1060 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1061 const struct pipe_resource *templ)
1062 {
1063 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1064
1065 if (templ->target == PIPE_BUFFER) {
1066 return r600_buffer_create(screen, templ,
1067 rscreen->info.gart_page_size);
1068 } else {
1069 return r600_texture_create(screen, templ);
1070 }
1071 }
1072
1073 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1074 struct radeon_winsys *ws)
1075 {
1076 char llvm_string[32] = {}, kernel_version[128] = {};
1077 struct utsname uname_data;
1078
1079 ws->query_info(ws, &rscreen->info);
1080
1081 if (uname(&uname_data) == 0)
1082 snprintf(kernel_version, sizeof(kernel_version),
1083 " / %s", uname_data.release);
1084
1085 #if HAVE_LLVM
1086 snprintf(llvm_string, sizeof(llvm_string),
1087 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1088 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1089 #endif
1090
1091 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1092 "%s (DRM %i.%i.%i%s%s)",
1093 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1094 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1095 kernel_version, llvm_string);
1096
1097 rscreen->b.get_name = r600_get_name;
1098 rscreen->b.get_vendor = r600_get_vendor;
1099 rscreen->b.get_device_vendor = r600_get_device_vendor;
1100 rscreen->b.get_compute_param = r600_get_compute_param;
1101 rscreen->b.get_paramf = r600_get_paramf;
1102 rscreen->b.get_timestamp = r600_get_timestamp;
1103 rscreen->b.fence_finish = r600_fence_finish;
1104 rscreen->b.fence_reference = r600_fence_reference;
1105 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1106 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1107 rscreen->b.query_memory_info = r600_query_memory_info;
1108
1109 if (rscreen->info.has_uvd) {
1110 rscreen->b.get_video_param = rvid_get_video_param;
1111 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1112 } else {
1113 rscreen->b.get_video_param = r600_get_video_param;
1114 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1115 }
1116
1117 r600_init_screen_texture_functions(rscreen);
1118 r600_init_screen_query_functions(rscreen);
1119
1120 rscreen->ws = ws;
1121 rscreen->family = rscreen->info.family;
1122 rscreen->chip_class = rscreen->info.chip_class;
1123 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1124
1125 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1126 if (rscreen->force_aniso >= 0) {
1127 printf("radeon: Forcing anisotropy filter to %ix\n",
1128 /* round down to a power of two */
1129 1 << util_logbase2(rscreen->force_aniso));
1130 }
1131
1132 util_format_s3tc_init();
1133 pipe_mutex_init(rscreen->aux_context_lock);
1134 pipe_mutex_init(rscreen->gpu_load_mutex);
1135
1136 if (rscreen->debug_flags & DBG_INFO) {
1137 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1138 printf("family = %i (%s)\n", rscreen->info.family,
1139 r600_get_chip_name(rscreen));
1140 printf("chip_class = %i\n", rscreen->info.chip_class);
1141 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1142 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1143 printf("max_alloc_size = %i MB\n",
1144 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1145 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1146 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1147 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1148 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1149 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1150 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1151 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1152 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1153 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1154 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1155 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1156 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1157 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1158
1159 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1160 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1161 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1162 printf("max_se = %i\n", rscreen->info.max_se);
1163 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1164
1165 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1166 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1167 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1168 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1169 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1170 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1171 }
1172 return true;
1173 }
1174
1175 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1176 {
1177 r600_perfcounters_destroy(rscreen);
1178 r600_gpu_load_kill_thread(rscreen);
1179
1180 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1181 pipe_mutex_destroy(rscreen->aux_context_lock);
1182 rscreen->aux_context->destroy(rscreen->aux_context);
1183
1184 rscreen->ws->destroy(rscreen->ws);
1185 FREE(rscreen);
1186 }
1187
1188 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1189 unsigned processor)
1190 {
1191 switch (processor) {
1192 case PIPE_SHADER_VERTEX:
1193 return (rscreen->debug_flags & DBG_VS) != 0;
1194 case PIPE_SHADER_TESS_CTRL:
1195 return (rscreen->debug_flags & DBG_TCS) != 0;
1196 case PIPE_SHADER_TESS_EVAL:
1197 return (rscreen->debug_flags & DBG_TES) != 0;
1198 case PIPE_SHADER_GEOMETRY:
1199 return (rscreen->debug_flags & DBG_GS) != 0;
1200 case PIPE_SHADER_FRAGMENT:
1201 return (rscreen->debug_flags & DBG_PS) != 0;
1202 case PIPE_SHADER_COMPUTE:
1203 return (rscreen->debug_flags & DBG_CS) != 0;
1204 default:
1205 return false;
1206 }
1207 }
1208
1209 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1210 uint64_t offset, uint64_t size, unsigned value,
1211 enum r600_coherency coher)
1212 {
1213 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1214
1215 pipe_mutex_lock(rscreen->aux_context_lock);
1216 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1217 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1218 pipe_mutex_unlock(rscreen->aux_context_lock);
1219 }