projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx9: prevent a GPU hang after a timestamp event
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t old_fence, uint32_t new_fence,
107 unsigned query_type)
108 {
109 struct radeon_winsys_cs *cs = ctx->gfx.cs;
110 unsigned op = EVENT_TYPE(event) |
111 EVENT_INDEX(5) |
112 event_flags;
113
114 if (ctx->chip_class >= GFX9) {
115 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
116 * counters) must immediately precede every timestamp event to
117 * prevent a GPU hang on GFX9.
118 *
119 * Occlusion queries don't need to do it here, because they
120 * always do ZPASS_DONE before the timestamp.
121 */
122 if (ctx->chip_class == GFX9 &&
123 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
124 query_type != PIPE_QUERY_OCCLUSION_PREDICATE) {
125 struct r600_resource *scratch = ctx->eop_bug_scratch;
126
127 assert(16 * ctx->screen->info.num_render_backends <=
128 scratch->b.b.width0);
129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
130 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
131 radeon_emit(cs, scratch->gpu_address);
132 radeon_emit(cs, scratch->gpu_address >> 32);
133
134 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
135 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
136 }
137
138 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
139 radeon_emit(cs, op);
140 radeon_emit(cs, EOP_DATA_SEL(data_sel));
141 radeon_emit(cs, va); /* address lo */
142 radeon_emit(cs, va >> 32); /* address hi */
143 radeon_emit(cs, new_fence); /* immediate data lo */
144 radeon_emit(cs, 0); /* immediate data hi */
145 radeon_emit(cs, 0); /* unused */
146 } else {
147 if (ctx->chip_class == CIK ||
148 ctx->chip_class == VI) {
149 /* Two EOP events are required to make all engines go idle
150 * (and optional cache flushes executed) before the timestamp
151 * is written.
152 */
153 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
154 radeon_emit(cs, op);
155 radeon_emit(cs, va);
156 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
157 radeon_emit(cs, old_fence); /* immediate data */
158 radeon_emit(cs, 0); /* unused */
159 }
160
161 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
162 radeon_emit(cs, op);
163 radeon_emit(cs, va);
164 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
165 radeon_emit(cs, new_fence); /* immediate data */
166 radeon_emit(cs, 0); /* unused */
167 }
168
169 if (buf)
170 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
171 RADEON_PRIO_QUERY);
172 }
173
174 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
175 {
176 unsigned dwords = 6;
177
178 if (screen->chip_class == CIK ||
179 screen->chip_class == VI)
180 dwords *= 2;
181
182 if (!screen->info.has_virtual_memory)
183 dwords += 2;
184
185 return dwords;
186 }
187
188 void r600_gfx_wait_fence(struct r600_common_context *ctx,
189 uint64_t va, uint32_t ref, uint32_t mask)
190 {
191 struct radeon_winsys_cs *cs = ctx->gfx.cs;
192
193 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
194 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
195 radeon_emit(cs, va);
196 radeon_emit(cs, va >> 32);
197 radeon_emit(cs, ref); /* reference value */
198 radeon_emit(cs, mask); /* mask */
199 radeon_emit(cs, 4); /* poll interval */
200 }
201
202 void r600_draw_rectangle(struct blitter_context *blitter,
203 int x1, int y1, int x2, int y2, float depth,
204 enum blitter_attrib_type type,
205 const union pipe_color_union *attrib)
206 {
207 struct r600_common_context *rctx =
208 (struct r600_common_context*)util_blitter_get_pipe(blitter);
209 struct pipe_viewport_state viewport;
210 struct pipe_resource *buf = NULL;
211 unsigned offset = 0;
212 float *vb;
213
214 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
215 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
216 return;
217 }
218
219 /* Some operations (like color resolve on r6xx) don't work
220 * with the conventional primitive types.
221 * One that works is PT_RECTLIST, which we use here. */
222
223 /* setup viewport */
224 viewport.scale[0] = 1.0f;
225 viewport.scale[1] = 1.0f;
226 viewport.scale[2] = 1.0f;
227 viewport.translate[0] = 0.0f;
228 viewport.translate[1] = 0.0f;
229 viewport.translate[2] = 0.0f;
230 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
231
232 /* Upload vertices. The hw rectangle has only 3 vertices,
233 * I guess the 4th one is derived from the first 3.
234 * The vertex specification should match u_blitter's vertex element state. */
235 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
236 rctx->screen->info.tcc_cache_line_size,
237 &offset, &buf, (void**)&vb);
238 if (!buf)
239 return;
240
241 vb[0] = x1;
242 vb[1] = y1;
243 vb[2] = depth;
244 vb[3] = 1;
245
246 vb[8] = x1;
247 vb[9] = y2;
248 vb[10] = depth;
249 vb[11] = 1;
250
251 vb[16] = x2;
252 vb[17] = y1;
253 vb[18] = depth;
254 vb[19] = 1;
255
256 if (attrib) {
257 memcpy(vb+4, attrib->f, sizeof(float)*4);
258 memcpy(vb+12, attrib->f, sizeof(float)*4);
259 memcpy(vb+20, attrib->f, sizeof(float)*4);
260 }
261
262 /* draw */
263 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
264 R600_PRIM_RECTANGLE_LIST, 3, 2);
265 pipe_resource_reference(&buf, NULL);
266 }
267
268 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
269 {
270 struct radeon_winsys_cs *cs = rctx->dma.cs;
271
272 /* NOP waits for idle on Evergreen and later. */
273 if (rctx->chip_class >= CIK)
274 radeon_emit(cs, 0x00000000); /* NOP */
275 else if (rctx->chip_class >= EVERGREEN)
276 radeon_emit(cs, 0xf0000000); /* NOP */
277 else {
278 /* TODO: R600-R700 should use the FENCE packet.
279 * CS checker support is required. */
280 }
281 }
282
283 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
284 struct r600_resource *dst, struct r600_resource *src)
285 {
286 uint64_t vram = ctx->dma.cs->used_vram;
287 uint64_t gtt = ctx->dma.cs->used_gart;
288
289 if (dst) {
290 vram += dst->vram_usage;
291 gtt += dst->gart_usage;
292 }
293 if (src) {
294 vram += src->vram_usage;
295 gtt += src->gart_usage;
296 }
297
298 /* Flush the GFX IB if DMA depends on it. */
299 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
300 ((dst &&
301 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
302 RADEON_USAGE_READWRITE)) ||
303 (src &&
304 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
305 RADEON_USAGE_WRITE))))
306 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
307
308 /* Flush if there's not enough space, or if the memory usage per IB
309 * is too large.
310 *
311 * IBs using too little memory are limited by the IB submission overhead.
312 * IBs using too much memory are limited by the kernel/TTM overhead.
313 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
314 *
315 * This heuristic makes sure that DMA requests are executed
316 * very soon after the call is made and lowers memory usage.
317 * It improves texture upload performance by keeping the DMA
318 * engine busy while uploads are being submitted.
319 */
320 num_dw++; /* for emit_wait_idle below */
321 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
322 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
323 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
324 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
325 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
326 }
327
328 /* Wait for idle if either buffer has been used in the IB before to
329 * prevent read-after-write hazards.
330 */
331 if ((dst &&
332 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
333 RADEON_USAGE_READWRITE)) ||
334 (src &&
335 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
336 RADEON_USAGE_WRITE)))
337 r600_dma_emit_wait_idle(ctx);
338
339 /* If GPUVM is not supported, the CS checker needs 2 entries
340 * in the buffer list per packet, which has to be done manually.
341 */
342 if (ctx->screen->info.has_virtual_memory) {
343 if (dst)
344 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
345 RADEON_USAGE_WRITE,
346 RADEON_PRIO_SDMA_BUFFER);
347 if (src)
348 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
349 RADEON_USAGE_READ,
350 RADEON_PRIO_SDMA_BUFFER);
351 }
352
353 /* this function is called before all DMA calls, so increment this. */
354 ctx->num_dma_calls++;
355 }
356
357 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
358 {
359 }
360
361 void r600_preflush_suspend_features(struct r600_common_context *ctx)
362 {
363 /* suspend queries */
364 if (!LIST_IS_EMPTY(&ctx->active_queries))
365 r600_suspend_queries(ctx);
366
367 ctx->streamout.suspended = false;
368 if (ctx->streamout.begin_emitted) {
369 r600_emit_streamout_end(ctx);
370 ctx->streamout.suspended = true;
371 }
372 }
373
374 void r600_postflush_resume_features(struct r600_common_context *ctx)
375 {
376 if (ctx->streamout.suspended) {
377 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
378 r600_streamout_buffers_dirty(ctx);
379 }
380
381 /* resume queries */
382 if (!LIST_IS_EMPTY(&ctx->active_queries))
383 r600_resume_queries(ctx);
384 }
385
386 static void r600_flush_from_st(struct pipe_context *ctx,
387 struct pipe_fence_handle **fence,
388 unsigned flags)
389 {
390 struct pipe_screen *screen = ctx->screen;
391 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
392 struct radeon_winsys *ws = rctx->ws;
393 struct pipe_fence_handle *gfx_fence = NULL;
394 struct pipe_fence_handle *sdma_fence = NULL;
395 bool deferred_fence = false;
396 unsigned rflags = RADEON_FLUSH_ASYNC;
397
398 if (flags & PIPE_FLUSH_END_OF_FRAME)
399 rflags |= RADEON_FLUSH_END_OF_FRAME;
400
401 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
402 if (rctx->dma.cs)
403 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
404
405 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
406 if (fence)
407 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
408 if (!(flags & PIPE_FLUSH_DEFERRED))
409 ws->cs_sync_flush(rctx->gfx.cs);
410 } else {
411 /* Instead of flushing, create a deferred fence. Constraints:
412 * - The state tracker must allow a deferred flush.
413 * - The state tracker must request a fence.
414 * Thread safety in fence_finish must be ensured by the state tracker.
415 */
416 if (flags & PIPE_FLUSH_DEFERRED && fence) {
417 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
418 deferred_fence = true;
419 } else {
420 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
421 }
422 }
423
424 /* Both engines can signal out of order, so we need to keep both fences. */
425 if (fence) {
426 struct r600_multi_fence *multi_fence =
427 CALLOC_STRUCT(r600_multi_fence);
428 if (!multi_fence)
429 return;
430
431 multi_fence->reference.count = 1;
432 /* If both fences are NULL, fence_finish will always return true. */
433 multi_fence->gfx = gfx_fence;
434 multi_fence->sdma = sdma_fence;
435
436 if (deferred_fence) {
437 multi_fence->gfx_unflushed.ctx = rctx;
438 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
439 }
440
441 screen->fence_reference(screen, fence, NULL);
442 *fence = (struct pipe_fence_handle*)multi_fence;
443 }
444
445 if (!(flags & PIPE_FLUSH_DEFERRED)) {
446 if (rctx->dma.cs)
447 ws->cs_sync_flush(rctx->dma.cs);
448 ws->cs_sync_flush(rctx->gfx.cs);
449 }
450 }
451
452 static void r600_flush_dma_ring(void *ctx, unsigned flags,
453 struct pipe_fence_handle **fence)
454 {
455 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
456 struct radeon_winsys_cs *cs = rctx->dma.cs;
457 struct radeon_saved_cs saved;
458 bool check_vm =
459 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
460 rctx->check_vm_faults;
461
462 if (!radeon_emitted(cs, 0)) {
463 if (fence)
464 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
465 return;
466 }
467
468 if (check_vm)
469 radeon_save_cs(rctx->ws, cs, &saved, true);
470
471 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
472 if (fence)
473 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
474
475 if (check_vm) {
476 /* Use conservative timeout 800ms, after which we won't wait any
477 * longer and assume the GPU is hung.
478 */
479 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
480
481 rctx->check_vm_faults(rctx, &saved, RING_DMA);
482 radeon_clear_saved_cs(&saved);
483 }
484 }
485
486 /**
487 * Store a linearized copy of all chunks of \p cs together with the buffer
488 * list in \p saved.
489 */
490 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
491 struct radeon_saved_cs *saved, bool get_buffer_list)
492 {
493 void *buf;
494 unsigned i;
495
496 /* Save the IB chunks. */
497 saved->num_dw = cs->prev_dw + cs->current.cdw;
498 saved->ib = MALLOC(4 * saved->num_dw);
499 if (!saved->ib)
500 goto oom;
501
502 buf = saved->ib;
503 for (i = 0; i < cs->num_prev; ++i) {
504 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
505 buf += cs->prev[i].cdw;
506 }
507 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
508
509 if (!get_buffer_list)
510 return;
511
512 /* Save the buffer list. */
513 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
514 saved->bo_list = CALLOC(saved->bo_count,
515 sizeof(saved->bo_list[0]));
516 if (!saved->bo_list) {
517 FREE(saved->ib);
518 goto oom;
519 }
520 ws->cs_get_buffer_list(cs, saved->bo_list);
521
522 return;
523
524 oom:
525 fprintf(stderr, "%s: out of memory\n", __func__);
526 memset(saved, 0, sizeof(*saved));
527 }
528
529 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
530 {
531 FREE(saved->ib);
532 FREE(saved->bo_list);
533
534 memset(saved, 0, sizeof(*saved));
535 }
536
537 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
538 {
539 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
540 unsigned latest = rctx->ws->query_value(rctx->ws,
541 RADEON_GPU_RESET_COUNTER);
542
543 if (rctx->gpu_reset_counter == latest)
544 return PIPE_NO_RESET;
545
546 rctx->gpu_reset_counter = latest;
547 return PIPE_UNKNOWN_CONTEXT_RESET;
548 }
549
550 static void r600_set_debug_callback(struct pipe_context *ctx,
551 const struct pipe_debug_callback *cb)
552 {
553 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
554
555 if (cb)
556 rctx->debug = *cb;
557 else
558 memset(&rctx->debug, 0, sizeof(rctx->debug));
559 }
560
561 static void r600_set_device_reset_callback(struct pipe_context *ctx,
562 const struct pipe_device_reset_callback *cb)
563 {
564 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
565
566 if (cb)
567 rctx->device_reset_callback = *cb;
568 else
569 memset(&rctx->device_reset_callback, 0,
570 sizeof(rctx->device_reset_callback));
571 }
572
573 bool r600_check_device_reset(struct r600_common_context *rctx)
574 {
575 enum pipe_reset_status status;
576
577 if (!rctx->device_reset_callback.reset)
578 return false;
579
580 if (!rctx->b.get_device_reset_status)
581 return false;
582
583 status = rctx->b.get_device_reset_status(&rctx->b);
584 if (status == PIPE_NO_RESET)
585 return false;
586
587 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
588 return true;
589 }
590
591 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
592 struct pipe_resource *dst,
593 uint64_t offset, uint64_t size,
594 unsigned value)
595 {
596 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
597
598 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
599 }
600
601 static bool r600_resource_commit(struct pipe_context *pctx,
602 struct pipe_resource *resource,
603 unsigned level, struct pipe_box *box,
604 bool commit)
605 {
606 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
607 struct r600_resource *res = r600_resource(resource);
608
609 /*
610 * Since buffer commitment changes cannot be pipelined, we need to
611 * (a) flush any pending commands that refer to the buffer we're about
612 * to change, and
613 * (b) wait for threaded submit to finish, including those that were
614 * triggered by some other, earlier operation.
615 */
616 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
617 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
618 res->buf, RADEON_USAGE_READWRITE)) {
619 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
620 }
621 if (radeon_emitted(ctx->dma.cs, 0) &&
622 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
623 res->buf, RADEON_USAGE_READWRITE)) {
624 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
625 }
626
627 ctx->ws->cs_sync_flush(ctx->dma.cs);
628 ctx->ws->cs_sync_flush(ctx->gfx.cs);
629
630 assert(resource->target == PIPE_BUFFER);
631
632 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
633 }
634
635 bool r600_common_context_init(struct r600_common_context *rctx,
636 struct r600_common_screen *rscreen,
637 unsigned context_flags)
638 {
639 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
640 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
641
642 rctx->screen = rscreen;
643 rctx->ws = rscreen->ws;
644 rctx->family = rscreen->family;
645 rctx->chip_class = rscreen->chip_class;
646
647 rctx->b.invalidate_resource = r600_invalidate_resource;
648 rctx->b.resource_commit = r600_resource_commit;
649 rctx->b.transfer_map = u_transfer_map_vtbl;
650 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
651 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
652 rctx->b.texture_subdata = u_default_texture_subdata;
653 rctx->b.memory_barrier = r600_memory_barrier;
654 rctx->b.flush = r600_flush_from_st;
655 rctx->b.set_debug_callback = r600_set_debug_callback;
656 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
657
658 /* evergreen_compute.c has a special codepath for global buffers.
659 * Everything else can use the direct path.
660 */
661 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
662 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
663 rctx->b.buffer_subdata = u_default_buffer_subdata;
664 else
665 rctx->b.buffer_subdata = r600_buffer_subdata;
666
667 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
668 rctx->b.get_device_reset_status = r600_get_reset_status;
669 rctx->gpu_reset_counter =
670 rctx->ws->query_value(rctx->ws,
671 RADEON_GPU_RESET_COUNTER);
672 }
673
674 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
675
676 r600_init_context_texture_functions(rctx);
677 r600_init_viewport_functions(rctx);
678 r600_streamout_init(rctx);
679 r600_query_init(rctx);
680 cayman_init_msaa(&rctx->b);
681
682 if (rctx->chip_class == GFX9) {
683 rctx->eop_bug_scratch = (struct r600_resource*)
684 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
685 16 * rscreen->info.num_render_backends);
686 if (!rctx->eop_bug_scratch)
687 return false;
688 }
689
690 rctx->allocator_zeroed_memory =
691 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
692 0, PIPE_USAGE_DEFAULT, 0, true);
693 if (!rctx->allocator_zeroed_memory)
694 return false;
695
696 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
697 0, PIPE_USAGE_STREAM);
698 if (!rctx->b.stream_uploader)
699 return false;
700
701 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
702 0, PIPE_USAGE_DEFAULT);
703 if (!rctx->b.const_uploader)
704 return false;
705
706 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
707 if (!rctx->ctx)
708 return false;
709
710 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
711 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
712 r600_flush_dma_ring,
713 rctx);
714 rctx->dma.flush = r600_flush_dma_ring;
715 }
716
717 return true;
718 }
719
720 void r600_common_context_cleanup(struct r600_common_context *rctx)
721 {
722 unsigned i,j;
723
724 /* Release DCC stats. */
725 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
726 assert(!rctx->dcc_stats[i].query_active);
727
728 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
729 if (rctx->dcc_stats[i].ps_stats[j])
730 rctx->b.destroy_query(&rctx->b,
731 rctx->dcc_stats[i].ps_stats[j]);
732
733 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
734 }
735
736 if (rctx->query_result_shader)
737 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
738
739 if (rctx->gfx.cs)
740 rctx->ws->cs_destroy(rctx->gfx.cs);
741 if (rctx->dma.cs)
742 rctx->ws->cs_destroy(rctx->dma.cs);
743 if (rctx->ctx)
744 rctx->ws->ctx_destroy(rctx->ctx);
745
746 if (rctx->b.stream_uploader)
747 u_upload_destroy(rctx->b.stream_uploader);
748 if (rctx->b.const_uploader)
749 u_upload_destroy(rctx->b.const_uploader);
750
751 slab_destroy_child(&rctx->pool_transfers);
752 slab_destroy_child(&rctx->pool_transfers_unsync);
753
754 if (rctx->allocator_zeroed_memory) {
755 u_suballocator_destroy(rctx->allocator_zeroed_memory);
756 }
757 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
758 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
759 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
760 }
761
762 /*
763 * pipe_screen
764 */
765
766 static const struct debug_named_value common_debug_options[] = {
767 /* logging */
768 { "tex", DBG_TEX, "Print texture info" },
769 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
770 { "compute", DBG_COMPUTE, "Print compute info" },
771 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
772 { "info", DBG_INFO, "Print driver information" },
773
774 /* shaders */
775 { "fs", DBG_FS, "Print fetch shaders" },
776 { "vs", DBG_VS, "Print vertex shaders" },
777 { "gs", DBG_GS, "Print geometry shaders" },
778 { "ps", DBG_PS, "Print pixel shaders" },
779 { "cs", DBG_CS, "Print compute shaders" },
780 { "tcs", DBG_TCS, "Print tessellation control shaders" },
781 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
782 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
783 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
784 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
785 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
786 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
787 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
788
789 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
790 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
791 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
792 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
793
794 /* features */
795 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
796 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
797 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
798 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
799 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
800 { "notiling", DBG_NO_TILING, "Disable tiling" },
801 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
802 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
803 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
804 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
805 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
806 { "nodcc", DBG_NO_DCC, "Disable DCC." },
807 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
808 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
809 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
810 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
811 { "ce", DBG_CE, "Force enable the constant engine" },
812 { "noce", DBG_NO_CE, "Disable the constant engine"},
813 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
814 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
815
816 DEBUG_NAMED_VALUE_END /* must be last */
817 };
818
819 static const char* r600_get_vendor(struct pipe_screen* pscreen)
820 {
821 return "X.Org";
822 }
823
824 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
825 {
826 return "AMD";
827 }
828
829 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
830 {
831 if (!ws->get_chip_name)
832 return NULL;
833 return ws->get_chip_name(ws);
834 }
835
836 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
837 {
838 switch (rscreen->info.family) {
839 case CHIP_R600: return "AMD R600";
840 case CHIP_RV610: return "AMD RV610";
841 case CHIP_RV630: return "AMD RV630";
842 case CHIP_RV670: return "AMD RV670";
843 case CHIP_RV620: return "AMD RV620";
844 case CHIP_RV635: return "AMD RV635";
845 case CHIP_RS780: return "AMD RS780";
846 case CHIP_RS880: return "AMD RS880";
847 case CHIP_RV770: return "AMD RV770";
848 case CHIP_RV730: return "AMD RV730";
849 case CHIP_RV710: return "AMD RV710";
850 case CHIP_RV740: return "AMD RV740";
851 case CHIP_CEDAR: return "AMD CEDAR";
852 case CHIP_REDWOOD: return "AMD REDWOOD";
853 case CHIP_JUNIPER: return "AMD JUNIPER";
854 case CHIP_CYPRESS: return "AMD CYPRESS";
855 case CHIP_HEMLOCK: return "AMD HEMLOCK";
856 case CHIP_PALM: return "AMD PALM";
857 case CHIP_SUMO: return "AMD SUMO";
858 case CHIP_SUMO2: return "AMD SUMO2";
859 case CHIP_BARTS: return "AMD BARTS";
860 case CHIP_TURKS: return "AMD TURKS";
861 case CHIP_CAICOS: return "AMD CAICOS";
862 case CHIP_CAYMAN: return "AMD CAYMAN";
863 case CHIP_ARUBA: return "AMD ARUBA";
864 case CHIP_TAHITI: return "AMD TAHITI";
865 case CHIP_PITCAIRN: return "AMD PITCAIRN";
866 case CHIP_VERDE: return "AMD CAPE VERDE";
867 case CHIP_OLAND: return "AMD OLAND";
868 case CHIP_HAINAN: return "AMD HAINAN";
869 case CHIP_BONAIRE: return "AMD BONAIRE";
870 case CHIP_KAVERI: return "AMD KAVERI";
871 case CHIP_KABINI: return "AMD KABINI";
872 case CHIP_HAWAII: return "AMD HAWAII";
873 case CHIP_MULLINS: return "AMD MULLINS";
874 case CHIP_TONGA: return "AMD TONGA";
875 case CHIP_ICELAND: return "AMD ICELAND";
876 case CHIP_CARRIZO: return "AMD CARRIZO";
877 case CHIP_FIJI: return "AMD FIJI";
878 case CHIP_POLARIS10: return "AMD POLARIS10";
879 case CHIP_POLARIS11: return "AMD POLARIS11";
880 case CHIP_POLARIS12: return "AMD POLARIS12";
881 case CHIP_STONEY: return "AMD STONEY";
882 case CHIP_VEGA10: return "AMD VEGA10";
883 case CHIP_RAVEN: return "AMD RAVEN";
884 default: return "AMD unknown";
885 }
886 }
887
888 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
889 {
890 /* Don't use the cache if shader dumping is enabled. */
891 if (rscreen->debug_flags &
892 (DBG_FS | DBG_VS | DBG_TCS | DBG_TES | DBG_GS | DBG_PS | DBG_CS))
893 return;
894
895 uint32_t mesa_timestamp;
896 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
897 &mesa_timestamp)) {
898 char *timestamp_str;
899 int res = -1;
900 if (rscreen->chip_class < SI) {
901 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
902 }
903 #if HAVE_LLVM
904 else {
905 uint32_t llvm_timestamp;
906 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
907 &llvm_timestamp)) {
908 res = asprintf(&timestamp_str, "%u_%u",
909 mesa_timestamp, llvm_timestamp);
910 }
911 }
912 #endif
913 if (res != -1) {
914 /* These flags affect shader compilation. */
915 uint64_t shader_debug_flags =
916 rscreen->debug_flags &
917 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
918 DBG_SI_SCHED |
919 DBG_UNSAFE_MATH);
920
921 rscreen->disk_shader_cache =
922 disk_cache_create(r600_get_family_name(rscreen),
923 timestamp_str,
924 shader_debug_flags);
925 free(timestamp_str);
926 }
927 }
928 }
929
930 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
931 {
932 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
933 return rscreen->disk_shader_cache;
934 }
935
936 static const char* r600_get_name(struct pipe_screen* pscreen)
937 {
938 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
939
940 return rscreen->renderer_string;
941 }
942
943 static float r600_get_paramf(struct pipe_screen* pscreen,
944 enum pipe_capf param)
945 {
946 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
947
948 switch (param) {
949 case PIPE_CAPF_MAX_LINE_WIDTH:
950 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
951 case PIPE_CAPF_MAX_POINT_WIDTH:
952 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
953 if (rscreen->family >= CHIP_CEDAR)
954 return 16384.0f;
955 else
956 return 8192.0f;
957 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
958 return 16.0f;
959 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
960 return 16.0f;
961 case PIPE_CAPF_GUARD_BAND_LEFT:
962 case PIPE_CAPF_GUARD_BAND_TOP:
963 case PIPE_CAPF_GUARD_BAND_RIGHT:
964 case PIPE_CAPF_GUARD_BAND_BOTTOM:
965 return 0.0f;
966 }
967 return 0.0f;
968 }
969
970 static int r600_get_video_param(struct pipe_screen *screen,
971 enum pipe_video_profile profile,
972 enum pipe_video_entrypoint entrypoint,
973 enum pipe_video_cap param)
974 {
975 switch (param) {
976 case PIPE_VIDEO_CAP_SUPPORTED:
977 return vl_profile_supported(screen, profile, entrypoint);
978 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
979 return 1;
980 case PIPE_VIDEO_CAP_MAX_WIDTH:
981 case PIPE_VIDEO_CAP_MAX_HEIGHT:
982 return vl_video_buffer_max_size(screen);
983 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
984 return PIPE_FORMAT_NV12;
985 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
986 return false;
987 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
988 return false;
989 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
990 return true;
991 case PIPE_VIDEO_CAP_MAX_LEVEL:
992 return vl_level_supported(screen, profile);
993 default:
994 return 0;
995 }
996 }
997
998 const char *r600_get_llvm_processor_name(enum radeon_family family)
999 {
1000 switch (family) {
1001 case CHIP_R600:
1002 case CHIP_RV630:
1003 case CHIP_RV635:
1004 case CHIP_RV670:
1005 return "r600";
1006 case CHIP_RV610:
1007 case CHIP_RV620:
1008 case CHIP_RS780:
1009 case CHIP_RS880:
1010 return "rs880";
1011 case CHIP_RV710:
1012 return "rv710";
1013 case CHIP_RV730:
1014 return "rv730";
1015 case CHIP_RV740:
1016 case CHIP_RV770:
1017 return "rv770";
1018 case CHIP_PALM:
1019 case CHIP_CEDAR:
1020 return "cedar";
1021 case CHIP_SUMO:
1022 case CHIP_SUMO2:
1023 return "sumo";
1024 case CHIP_REDWOOD:
1025 return "redwood";
1026 case CHIP_JUNIPER:
1027 return "juniper";
1028 case CHIP_HEMLOCK:
1029 case CHIP_CYPRESS:
1030 return "cypress";
1031 case CHIP_BARTS:
1032 return "barts";
1033 case CHIP_TURKS:
1034 return "turks";
1035 case CHIP_CAICOS:
1036 return "caicos";
1037 case CHIP_CAYMAN:
1038 case CHIP_ARUBA:
1039 return "cayman";
1040
1041 case CHIP_TAHITI: return "tahiti";
1042 case CHIP_PITCAIRN: return "pitcairn";
1043 case CHIP_VERDE: return "verde";
1044 case CHIP_OLAND: return "oland";
1045 case CHIP_HAINAN: return "hainan";
1046 case CHIP_BONAIRE: return "bonaire";
1047 case CHIP_KABINI: return "kabini";
1048 case CHIP_KAVERI: return "kaveri";
1049 case CHIP_HAWAII: return "hawaii";
1050 case CHIP_MULLINS:
1051 return "mullins";
1052 case CHIP_TONGA: return "tonga";
1053 case CHIP_ICELAND: return "iceland";
1054 case CHIP_CARRIZO: return "carrizo";
1055 case CHIP_FIJI:
1056 return "fiji";
1057 case CHIP_STONEY:
1058 return "stoney";
1059 case CHIP_POLARIS10:
1060 return "polaris10";
1061 case CHIP_POLARIS11:
1062 case CHIP_POLARIS12: /* same as polaris11 */
1063 return "polaris11";
1064 case CHIP_VEGA10:
1065 case CHIP_RAVEN:
1066 return "gfx900";
1067 default:
1068 return "";
1069 }
1070 }
1071
1072 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1073 enum pipe_shader_ir ir_type)
1074 {
1075 if (ir_type != PIPE_SHADER_IR_TGSI)
1076 return 256;
1077
1078 /* Only 16 waves per thread-group on gfx9. */
1079 if (screen->chip_class >= GFX9)
1080 return 1024;
1081
1082 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1083 * round number.
1084 */
1085 if (screen->chip_class >= SI)
1086 return 2048;
1087
1088 return 256;
1089 }
1090
1091 static int r600_get_compute_param(struct pipe_screen *screen,
1092 enum pipe_shader_ir ir_type,
1093 enum pipe_compute_cap param,
1094 void *ret)
1095 {
1096 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1097
1098 //TODO: select these params by asic
1099 switch (param) {
1100 case PIPE_COMPUTE_CAP_IR_TARGET: {
1101 const char *gpu;
1102 const char *triple;
1103 if (rscreen->family <= CHIP_ARUBA) {
1104 triple = "r600--";
1105 } else {
1106 if (HAVE_LLVM < 0x0400) {
1107 triple = "amdgcn--";
1108 } else {
1109 triple = "amdgcn-mesa-mesa3d";
1110 }
1111 }
1112 switch(rscreen->family) {
1113 /* Clang < 3.6 is missing Hainan in its list of
1114 * GPUs, so we need to use the name of a similar GPU.
1115 */
1116 default:
1117 gpu = r600_get_llvm_processor_name(rscreen->family);
1118 break;
1119 }
1120 if (ret) {
1121 sprintf(ret, "%s-%s", gpu, triple);
1122 }
1123 /* +2 for dash and terminating NIL byte */
1124 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1125 }
1126 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1127 if (ret) {
1128 uint64_t *grid_dimension = ret;
1129 grid_dimension[0] = 3;
1130 }
1131 return 1 * sizeof(uint64_t);
1132
1133 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1134 if (ret) {
1135 uint64_t *grid_size = ret;
1136 grid_size[0] = 65535;
1137 grid_size[1] = 65535;
1138 grid_size[2] = 65535;
1139 }
1140 return 3 * sizeof(uint64_t) ;
1141
1142 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1143 if (ret) {
1144 uint64_t *block_size = ret;
1145 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1146 block_size[0] = threads_per_block;
1147 block_size[1] = threads_per_block;
1148 block_size[2] = threads_per_block;
1149 }
1150 return 3 * sizeof(uint64_t);
1151
1152 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1153 if (ret) {
1154 uint64_t *max_threads_per_block = ret;
1155 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1156 }
1157 return sizeof(uint64_t);
1158 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1159 if (ret) {
1160 uint32_t *address_bits = ret;
1161 address_bits[0] = 32;
1162 if (rscreen->chip_class >= SI)
1163 address_bits[0] = 64;
1164 }
1165 return 1 * sizeof(uint32_t);
1166
1167 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1168 if (ret) {
1169 uint64_t *max_global_size = ret;
1170 uint64_t max_mem_alloc_size;
1171
1172 r600_get_compute_param(screen, ir_type,
1173 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1174 &max_mem_alloc_size);
1175
1176 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1177 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1178 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1179 * make sure we never report more than
1180 * 4 * MAX_MEM_ALLOC_SIZE.
1181 */
1182 *max_global_size = MIN2(4 * max_mem_alloc_size,
1183 MAX2(rscreen->info.gart_size,
1184 rscreen->info.vram_size));
1185 }
1186 return sizeof(uint64_t);
1187
1188 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1189 if (ret) {
1190 uint64_t *max_local_size = ret;
1191 /* Value reported by the closed source driver. */
1192 *max_local_size = 32768;
1193 }
1194 return sizeof(uint64_t);
1195
1196 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1197 if (ret) {
1198 uint64_t *max_input_size = ret;
1199 /* Value reported by the closed source driver. */
1200 *max_input_size = 1024;
1201 }
1202 return sizeof(uint64_t);
1203
1204 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1205 if (ret) {
1206 uint64_t *max_mem_alloc_size = ret;
1207
1208 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1209 }
1210 return sizeof(uint64_t);
1211
1212 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1213 if (ret) {
1214 uint32_t *max_clock_frequency = ret;
1215 *max_clock_frequency = rscreen->info.max_shader_clock;
1216 }
1217 return sizeof(uint32_t);
1218
1219 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1220 if (ret) {
1221 uint32_t *max_compute_units = ret;
1222 *max_compute_units = rscreen->info.num_good_compute_units;
1223 }
1224 return sizeof(uint32_t);
1225
1226 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1227 if (ret) {
1228 uint32_t *images_supported = ret;
1229 *images_supported = 0;
1230 }
1231 return sizeof(uint32_t);
1232 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1233 break; /* unused */
1234 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1235 if (ret) {
1236 uint32_t *subgroup_size = ret;
1237 *subgroup_size = r600_wavefront_size(rscreen->family);
1238 }
1239 return sizeof(uint32_t);
1240 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1241 if (ret) {
1242 uint64_t *max_variable_threads_per_block = ret;
1243 if (rscreen->chip_class >= SI &&
1244 ir_type == PIPE_SHADER_IR_TGSI)
1245 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1246 else
1247 *max_variable_threads_per_block = 0;
1248 }
1249 return sizeof(uint64_t);
1250 }
1251
1252 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1253 return 0;
1254 }
1255
1256 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1257 {
1258 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1259
1260 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1261 rscreen->info.clock_crystal_freq;
1262 }
1263
1264 static void r600_fence_reference(struct pipe_screen *screen,
1265 struct pipe_fence_handle **dst,
1266 struct pipe_fence_handle *src)
1267 {
1268 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1269 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1270 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1271
1272 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1273 ws->fence_reference(&(*rdst)->gfx, NULL);
1274 ws->fence_reference(&(*rdst)->sdma, NULL);
1275 FREE(*rdst);
1276 }
1277 *rdst = rsrc;
1278 }
1279
1280 static boolean r600_fence_finish(struct pipe_screen *screen,
1281 struct pipe_context *ctx,
1282 struct pipe_fence_handle *fence,
1283 uint64_t timeout)
1284 {
1285 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1286 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1287 struct r600_common_context *rctx;
1288 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1289
1290 ctx = threaded_context_unwrap_sync(ctx);
1291 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1292
1293 if (rfence->sdma) {
1294 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1295 return false;
1296
1297 /* Recompute the timeout after waiting. */
1298 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1299 int64_t time = os_time_get_nano();
1300 timeout = abs_timeout > time ? abs_timeout - time : 0;
1301 }
1302 }
1303
1304 if (!rfence->gfx)
1305 return true;
1306
1307 /* Flush the gfx IB if it hasn't been flushed yet. */
1308 if (rctx &&
1309 rfence->gfx_unflushed.ctx == rctx &&
1310 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1311 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1312 rfence->gfx_unflushed.ctx = NULL;
1313
1314 if (!timeout)
1315 return false;
1316
1317 /* Recompute the timeout after all that. */
1318 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1319 int64_t time = os_time_get_nano();
1320 timeout = abs_timeout > time ? abs_timeout - time : 0;
1321 }
1322 }
1323
1324 return rws->fence_wait(rws, rfence->gfx, timeout);
1325 }
1326
1327 static void r600_query_memory_info(struct pipe_screen *screen,
1328 struct pipe_memory_info *info)
1329 {
1330 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1331 struct radeon_winsys *ws = rscreen->ws;
1332 unsigned vram_usage, gtt_usage;
1333
1334 info->total_device_memory = rscreen->info.vram_size / 1024;
1335 info->total_staging_memory = rscreen->info.gart_size / 1024;
1336
1337 /* The real TTM memory usage is somewhat random, because:
1338 *
1339 * 1) TTM delays freeing memory, because it can only free it after
1340 * fences expire.
1341 *
1342 * 2) The memory usage can be really low if big VRAM evictions are
1343 * taking place, but the real usage is well above the size of VRAM.
1344 *
1345 * Instead, return statistics of this process.
1346 */
1347 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1348 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1349
1350 info->avail_device_memory =
1351 vram_usage <= info->total_device_memory ?
1352 info->total_device_memory - vram_usage : 0;
1353 info->avail_staging_memory =
1354 gtt_usage <= info->total_staging_memory ?
1355 info->total_staging_memory - gtt_usage : 0;
1356
1357 info->device_memory_evicted =
1358 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1359
1360 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1361 info->nr_device_memory_evictions =
1362 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1363 else
1364 /* Just return the number of evicted 64KB pages. */
1365 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1366 }
1367
1368 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1369 const struct pipe_resource *templ)
1370 {
1371 if (templ->target == PIPE_BUFFER) {
1372 return r600_buffer_create(screen, templ, 256);
1373 } else {
1374 return r600_texture_create(screen, templ);
1375 }
1376 }
1377
1378 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1379 struct radeon_winsys *ws)
1380 {
1381 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1382 struct utsname uname_data;
1383 const char *chip_name;
1384
1385 ws->query_info(ws, &rscreen->info);
1386 rscreen->ws = ws;
1387
1388 if ((chip_name = r600_get_marketing_name(ws)))
1389 snprintf(family_name, sizeof(family_name), "%s / ",
1390 r600_get_family_name(rscreen) + 4);
1391 else
1392 chip_name = r600_get_family_name(rscreen);
1393
1394 if (uname(&uname_data) == 0)
1395 snprintf(kernel_version, sizeof(kernel_version),
1396 " / %s", uname_data.release);
1397
1398 if (HAVE_LLVM > 0) {
1399 snprintf(llvm_string, sizeof(llvm_string),
1400 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1401 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1402 }
1403
1404 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1405 "%s (%sDRM %i.%i.%i%s%s)",
1406 chip_name, family_name, rscreen->info.drm_major,
1407 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1408 kernel_version, llvm_string);
1409
1410 rscreen->b.get_name = r600_get_name;
1411 rscreen->b.get_vendor = r600_get_vendor;
1412 rscreen->b.get_device_vendor = r600_get_device_vendor;
1413 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1414 rscreen->b.get_compute_param = r600_get_compute_param;
1415 rscreen->b.get_paramf = r600_get_paramf;
1416 rscreen->b.get_timestamp = r600_get_timestamp;
1417 rscreen->b.fence_finish = r600_fence_finish;
1418 rscreen->b.fence_reference = r600_fence_reference;
1419 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1420 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1421 rscreen->b.query_memory_info = r600_query_memory_info;
1422
1423 if (rscreen->info.has_hw_decode) {
1424 rscreen->b.get_video_param = rvid_get_video_param;
1425 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1426 } else {
1427 rscreen->b.get_video_param = r600_get_video_param;
1428 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1429 }
1430
1431 r600_init_screen_texture_functions(rscreen);
1432 r600_init_screen_query_functions(rscreen);
1433
1434 rscreen->family = rscreen->info.family;
1435 rscreen->chip_class = rscreen->info.chip_class;
1436 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1437 rscreen->has_rbplus = false;
1438 rscreen->rbplus_allowed = false;
1439
1440 r600_disk_cache_create(rscreen);
1441
1442 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1443
1444 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1445 if (rscreen->force_aniso >= 0) {
1446 printf("radeon: Forcing anisotropy filter to %ix\n",
1447 /* round down to a power of two */
1448 1 << util_logbase2(rscreen->force_aniso));
1449 }
1450
1451 util_format_s3tc_init();
1452 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1453 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1454
1455 if (rscreen->debug_flags & DBG_INFO) {
1456 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1457 rscreen->info.pci_domain, rscreen->info.pci_bus,
1458 rscreen->info.pci_dev, rscreen->info.pci_func);
1459 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1460 printf("family = %i (%s)\n", rscreen->info.family,
1461 r600_get_family_name(rscreen));
1462 printf("chip_class = %i\n", rscreen->info.chip_class);
1463 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1464 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1465 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1466 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1467 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1468 printf("max_alloc_size = %i MB\n",
1469 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1470 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1471 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1472 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1473 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1474 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1475 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1476 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1477 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1478 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1479 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1480 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1481 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1482 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1483 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1484 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1485 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1486 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1487 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1488 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1489
1490 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1491 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1492 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1493 printf("max_se = %i\n", rscreen->info.max_se);
1494 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1495
1496 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1497 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1498 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1499 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1500 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1501 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1502 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1503 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1504 }
1505 return true;
1506 }
1507
1508 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1509 {
1510 r600_perfcounters_destroy(rscreen);
1511 r600_gpu_load_kill_thread(rscreen);
1512
1513 mtx_destroy(&rscreen->gpu_load_mutex);
1514 mtx_destroy(&rscreen->aux_context_lock);
1515 rscreen->aux_context->destroy(rscreen->aux_context);
1516
1517 slab_destroy_parent(&rscreen->pool_transfers);
1518
1519 disk_cache_destroy(rscreen->disk_shader_cache);
1520 rscreen->ws->destroy(rscreen->ws);
1521 FREE(rscreen);
1522 }
1523
1524 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1525 unsigned processor)
1526 {
1527 switch (processor) {
1528 case PIPE_SHADER_VERTEX:
1529 return (rscreen->debug_flags & DBG_VS) != 0;
1530 case PIPE_SHADER_TESS_CTRL:
1531 return (rscreen->debug_flags & DBG_TCS) != 0;
1532 case PIPE_SHADER_TESS_EVAL:
1533 return (rscreen->debug_flags & DBG_TES) != 0;
1534 case PIPE_SHADER_GEOMETRY:
1535 return (rscreen->debug_flags & DBG_GS) != 0;
1536 case PIPE_SHADER_FRAGMENT:
1537 return (rscreen->debug_flags & DBG_PS) != 0;
1538 case PIPE_SHADER_COMPUTE:
1539 return (rscreen->debug_flags & DBG_CS) != 0;
1540 default:
1541 return false;
1542 }
1543 }
1544
1545 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1546 {
1547 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1548 r600_can_dump_shader(rscreen, processor);
1549 }
1550
1551 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1552 uint64_t offset, uint64_t size, unsigned value)
1553 {
1554 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1555
1556 mtx_lock(&rscreen->aux_context_lock);
1557 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1558 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1559 mtx_unlock(&rscreen->aux_context_lock);
1560 }