projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: replace pipe_driver_query_info::max_value by a union
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* The number of dwords we already used in the DMA so far. */
111 num_dw += ctx->rings.dma.cs->cdw;
112 /* Flush if there's not enough space. */
113 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
114 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
115 }
116 }
117
118 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
119 {
120 }
121
122 void r600_preflush_suspend_features(struct r600_common_context *ctx)
123 {
124 /* Disable render condition. */
125 ctx->saved_render_cond = NULL;
126 ctx->saved_render_cond_cond = FALSE;
127 ctx->saved_render_cond_mode = 0;
128 if (ctx->current_render_cond) {
129 ctx->saved_render_cond = ctx->current_render_cond;
130 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
131 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
132 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
133 }
134
135 /* suspend queries */
136 ctx->nontimer_queries_suspended = false;
137 if (ctx->num_cs_dw_nontimer_queries_suspend) {
138 r600_suspend_nontimer_queries(ctx);
139 ctx->nontimer_queries_suspended = true;
140 }
141
142 ctx->streamout.suspended = false;
143 if (ctx->streamout.begin_emitted) {
144 r600_emit_streamout_end(ctx);
145 ctx->streamout.suspended = true;
146 }
147 }
148
149 void r600_postflush_resume_features(struct r600_common_context *ctx)
150 {
151 if (ctx->streamout.suspended) {
152 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
153 r600_streamout_buffers_dirty(ctx);
154 }
155
156 /* resume queries */
157 if (ctx->nontimer_queries_suspended) {
158 r600_resume_nontimer_queries(ctx);
159 }
160
161 /* Re-enable render condition. */
162 if (ctx->saved_render_cond) {
163 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
164 ctx->saved_render_cond_cond,
165 ctx->saved_render_cond_mode);
166 }
167 }
168
169 static void r600_flush_from_st(struct pipe_context *ctx,
170 struct pipe_fence_handle **fence,
171 unsigned flags)
172 {
173 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
174 unsigned rflags = 0;
175
176 if (flags & PIPE_FLUSH_END_OF_FRAME)
177 rflags |= RADEON_FLUSH_END_OF_FRAME;
178
179 if (rctx->rings.dma.cs) {
180 rctx->rings.dma.flush(rctx, rflags, NULL);
181 }
182 rctx->rings.gfx.flush(rctx, rflags, fence);
183 }
184
185 static void r600_flush_dma_ring(void *ctx, unsigned flags,
186 struct pipe_fence_handle **fence)
187 {
188 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
189 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
190
191 if (!cs->cdw) {
192 return;
193 }
194
195 rctx->rings.dma.flushing = true;
196 rctx->ws->cs_flush(cs, flags, fence, 0);
197 rctx->rings.dma.flushing = false;
198 }
199
200 bool r600_common_context_init(struct r600_common_context *rctx,
201 struct r600_common_screen *rscreen)
202 {
203 util_slab_create(&rctx->pool_transfers,
204 sizeof(struct r600_transfer), 64,
205 UTIL_SLAB_SINGLETHREADED);
206
207 rctx->screen = rscreen;
208 rctx->ws = rscreen->ws;
209 rctx->family = rscreen->family;
210 rctx->chip_class = rscreen->chip_class;
211
212 if (rscreen->family == CHIP_HAWAII)
213 rctx->max_db = 16;
214 else if (rscreen->chip_class >= EVERGREEN)
215 rctx->max_db = 8;
216 else
217 rctx->max_db = 4;
218
219 rctx->b.transfer_map = u_transfer_map_vtbl;
220 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
221 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
222 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
223 rctx->b.memory_barrier = r600_memory_barrier;
224 rctx->b.flush = r600_flush_from_st;
225
226 LIST_INITHEAD(&rctx->texture_buffers);
227
228 r600_init_context_texture_functions(rctx);
229 r600_streamout_init(rctx);
230 r600_query_init(rctx);
231 cayman_init_msaa(&rctx->b);
232
233 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
234 0, PIPE_USAGE_DEFAULT, TRUE);
235 if (!rctx->allocator_so_filled_size)
236 return false;
237
238 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
239 PIPE_BIND_INDEX_BUFFER |
240 PIPE_BIND_CONSTANT_BUFFER);
241 if (!rctx->uploader)
242 return false;
243
244 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
245 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
246 r600_flush_dma_ring,
247 rctx, NULL);
248 rctx->rings.dma.flush = r600_flush_dma_ring;
249 }
250
251 return true;
252 }
253
254 void r600_common_context_cleanup(struct r600_common_context *rctx)
255 {
256 if (rctx->rings.gfx.cs) {
257 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
258 }
259 if (rctx->rings.dma.cs) {
260 rctx->ws->cs_destroy(rctx->rings.dma.cs);
261 }
262
263 if (rctx->uploader) {
264 u_upload_destroy(rctx->uploader);
265 }
266
267 util_slab_destroy(&rctx->pool_transfers);
268
269 if (rctx->allocator_so_filled_size) {
270 u_suballocator_destroy(rctx->allocator_so_filled_size);
271 }
272 }
273
274 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
275 {
276 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
277 struct r600_resource *rr = (struct r600_resource *)r;
278
279 if (r == NULL) {
280 return;
281 }
282
283 /*
284 * The idea is to compute a gross estimate of memory requirement of
285 * each draw call. After each draw call, memory will be precisely
286 * accounted. So the uncertainty is only on the current draw call.
287 * In practice this gave very good estimate (+/- 10% of the target
288 * memory limit).
289 */
290 if (rr->domains & RADEON_DOMAIN_GTT) {
291 rctx->gtt += rr->buf->size;
292 }
293 if (rr->domains & RADEON_DOMAIN_VRAM) {
294 rctx->vram += rr->buf->size;
295 }
296 }
297
298 /*
299 * pipe_screen
300 */
301
302 static const struct debug_named_value common_debug_options[] = {
303 /* logging */
304 { "tex", DBG_TEX, "Print texture info" },
305 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
306 { "compute", DBG_COMPUTE, "Print compute info" },
307 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
308 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
309 { "info", DBG_INFO, "Print driver information" },
310
311 /* shaders */
312 { "fs", DBG_FS, "Print fetch shaders" },
313 { "vs", DBG_VS, "Print vertex shaders" },
314 { "gs", DBG_GS, "Print geometry shaders" },
315 { "ps", DBG_PS, "Print pixel shaders" },
316 { "cs", DBG_CS, "Print compute shaders" },
317
318 /* features */
319 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
320 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
321 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
322 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
323 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
324 { "notiling", DBG_NO_TILING, "Disable tiling" },
325 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
326 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
327 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
328
329 DEBUG_NAMED_VALUE_END /* must be last */
330 };
331
332 static const char* r600_get_vendor(struct pipe_screen* pscreen)
333 {
334 return "X.Org";
335 }
336
337 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
338 {
339 return "AMD";
340 }
341
342 static const char* r600_get_name(struct pipe_screen* pscreen)
343 {
344 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
345
346 switch (rscreen->family) {
347 case CHIP_R600: return "AMD R600";
348 case CHIP_RV610: return "AMD RV610";
349 case CHIP_RV630: return "AMD RV630";
350 case CHIP_RV670: return "AMD RV670";
351 case CHIP_RV620: return "AMD RV620";
352 case CHIP_RV635: return "AMD RV635";
353 case CHIP_RS780: return "AMD RS780";
354 case CHIP_RS880: return "AMD RS880";
355 case CHIP_RV770: return "AMD RV770";
356 case CHIP_RV730: return "AMD RV730";
357 case CHIP_RV710: return "AMD RV710";
358 case CHIP_RV740: return "AMD RV740";
359 case CHIP_CEDAR: return "AMD CEDAR";
360 case CHIP_REDWOOD: return "AMD REDWOOD";
361 case CHIP_JUNIPER: return "AMD JUNIPER";
362 case CHIP_CYPRESS: return "AMD CYPRESS";
363 case CHIP_HEMLOCK: return "AMD HEMLOCK";
364 case CHIP_PALM: return "AMD PALM";
365 case CHIP_SUMO: return "AMD SUMO";
366 case CHIP_SUMO2: return "AMD SUMO2";
367 case CHIP_BARTS: return "AMD BARTS";
368 case CHIP_TURKS: return "AMD TURKS";
369 case CHIP_CAICOS: return "AMD CAICOS";
370 case CHIP_CAYMAN: return "AMD CAYMAN";
371 case CHIP_ARUBA: return "AMD ARUBA";
372 case CHIP_TAHITI: return "AMD TAHITI";
373 case CHIP_PITCAIRN: return "AMD PITCAIRN";
374 case CHIP_VERDE: return "AMD CAPE VERDE";
375 case CHIP_OLAND: return "AMD OLAND";
376 case CHIP_HAINAN: return "AMD HAINAN";
377 case CHIP_BONAIRE: return "AMD BONAIRE";
378 case CHIP_KAVERI: return "AMD KAVERI";
379 case CHIP_KABINI: return "AMD KABINI";
380 case CHIP_HAWAII: return "AMD HAWAII";
381 case CHIP_MULLINS: return "AMD MULLINS";
382 default: return "AMD unknown";
383 }
384 }
385
386 static float r600_get_paramf(struct pipe_screen* pscreen,
387 enum pipe_capf param)
388 {
389 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
390
391 switch (param) {
392 case PIPE_CAPF_MAX_LINE_WIDTH:
393 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
394 case PIPE_CAPF_MAX_POINT_WIDTH:
395 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
396 if (rscreen->family >= CHIP_CEDAR)
397 return 16384.0f;
398 else
399 return 8192.0f;
400 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
401 return 16.0f;
402 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
403 return 16.0f;
404 case PIPE_CAPF_GUARD_BAND_LEFT:
405 case PIPE_CAPF_GUARD_BAND_TOP:
406 case PIPE_CAPF_GUARD_BAND_RIGHT:
407 case PIPE_CAPF_GUARD_BAND_BOTTOM:
408 return 0.0f;
409 }
410 return 0.0f;
411 }
412
413 static int r600_get_video_param(struct pipe_screen *screen,
414 enum pipe_video_profile profile,
415 enum pipe_video_entrypoint entrypoint,
416 enum pipe_video_cap param)
417 {
418 switch (param) {
419 case PIPE_VIDEO_CAP_SUPPORTED:
420 return vl_profile_supported(screen, profile, entrypoint);
421 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
422 return 1;
423 case PIPE_VIDEO_CAP_MAX_WIDTH:
424 case PIPE_VIDEO_CAP_MAX_HEIGHT:
425 return vl_video_buffer_max_size(screen);
426 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
427 return PIPE_FORMAT_NV12;
428 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
429 return false;
430 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
431 return false;
432 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
433 return true;
434 case PIPE_VIDEO_CAP_MAX_LEVEL:
435 return vl_level_supported(screen, profile);
436 default:
437 return 0;
438 }
439 }
440
441 const char *r600_get_llvm_processor_name(enum radeon_family family)
442 {
443 switch (family) {
444 case CHIP_R600:
445 case CHIP_RV630:
446 case CHIP_RV635:
447 case CHIP_RV670:
448 return "r600";
449 case CHIP_RV610:
450 case CHIP_RV620:
451 case CHIP_RS780:
452 case CHIP_RS880:
453 return "rs880";
454 case CHIP_RV710:
455 return "rv710";
456 case CHIP_RV730:
457 return "rv730";
458 case CHIP_RV740:
459 case CHIP_RV770:
460 return "rv770";
461 case CHIP_PALM:
462 case CHIP_CEDAR:
463 return "cedar";
464 case CHIP_SUMO:
465 case CHIP_SUMO2:
466 return "sumo";
467 case CHIP_REDWOOD:
468 return "redwood";
469 case CHIP_JUNIPER:
470 return "juniper";
471 case CHIP_HEMLOCK:
472 case CHIP_CYPRESS:
473 return "cypress";
474 case CHIP_BARTS:
475 return "barts";
476 case CHIP_TURKS:
477 return "turks";
478 case CHIP_CAICOS:
479 return "caicos";
480 case CHIP_CAYMAN:
481 case CHIP_ARUBA:
482 return "cayman";
483
484 case CHIP_TAHITI: return "tahiti";
485 case CHIP_PITCAIRN: return "pitcairn";
486 case CHIP_VERDE: return "verde";
487 case CHIP_OLAND: return "oland";
488 case CHIP_HAINAN: return "hainan";
489 case CHIP_BONAIRE: return "bonaire";
490 case CHIP_KABINI: return "kabini";
491 case CHIP_KAVERI: return "kaveri";
492 case CHIP_HAWAII: return "hawaii";
493 case CHIP_MULLINS:
494 #if HAVE_LLVM >= 0x0305
495 return "mullins";
496 #else
497 return "kabini";
498 #endif
499 default: return "";
500 }
501 }
502
503 static int r600_get_compute_param(struct pipe_screen *screen,
504 enum pipe_compute_cap param,
505 void *ret)
506 {
507 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
508
509 //TODO: select these params by asic
510 switch (param) {
511 case PIPE_COMPUTE_CAP_IR_TARGET: {
512 const char *gpu;
513 const char *triple;
514 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
515 triple = "r600--";
516 } else {
517 triple = "amdgcn--";
518 }
519 switch(rscreen->family) {
520 /* Clang < 3.6 is missing Hainan in its list of
521 * GPUs, so we need to use the name of a similar GPU.
522 */
523 #if HAVE_LLVM < 0x0306
524 case CHIP_HAINAN:
525 gpu = "oland";
526 break;
527 #endif
528 default:
529 gpu = r600_get_llvm_processor_name(rscreen->family);
530 break;
531 }
532 if (ret) {
533 sprintf(ret, "%s-%s", gpu, triple);
534 }
535 /* +2 for dash and terminating NIL byte */
536 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
537 }
538 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
539 if (ret) {
540 uint64_t *grid_dimension = ret;
541 grid_dimension[0] = 3;
542 }
543 return 1 * sizeof(uint64_t);
544
545 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
546 if (ret) {
547 uint64_t *grid_size = ret;
548 grid_size[0] = 65535;
549 grid_size[1] = 65535;
550 grid_size[2] = 1;
551 }
552 return 3 * sizeof(uint64_t) ;
553
554 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
555 if (ret) {
556 uint64_t *block_size = ret;
557 block_size[0] = 256;
558 block_size[1] = 256;
559 block_size[2] = 256;
560 }
561 return 3 * sizeof(uint64_t);
562
563 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
564 if (ret) {
565 uint64_t *max_threads_per_block = ret;
566 *max_threads_per_block = 256;
567 }
568 return sizeof(uint64_t);
569
570 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
571 if (ret) {
572 uint64_t *max_global_size = ret;
573 uint64_t max_mem_alloc_size;
574
575 r600_get_compute_param(screen,
576 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
577 &max_mem_alloc_size);
578
579 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
580 * 1/4 of the MAX_GLOBAL_SIZE. Since the
581 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
582 * make sure we never report more than
583 * 4 * MAX_MEM_ALLOC_SIZE.
584 */
585 *max_global_size = MIN2(4 * max_mem_alloc_size,
586 rscreen->info.gart_size +
587 rscreen->info.vram_size);
588 }
589 return sizeof(uint64_t);
590
591 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
592 if (ret) {
593 uint64_t *max_local_size = ret;
594 /* Value reported by the closed source driver. */
595 *max_local_size = 32768;
596 }
597 return sizeof(uint64_t);
598
599 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
600 if (ret) {
601 uint64_t *max_input_size = ret;
602 /* Value reported by the closed source driver. */
603 *max_input_size = 1024;
604 }
605 return sizeof(uint64_t);
606
607 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
608 if (ret) {
609 uint64_t *max_mem_alloc_size = ret;
610
611 /* XXX: The limit in older kernels is 256 MB. We
612 * should add a query here for newer kernels.
613 */
614 *max_mem_alloc_size = 256 * 1024 * 1024;
615 }
616 return sizeof(uint64_t);
617
618 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
619 if (ret) {
620 uint32_t *max_clock_frequency = ret;
621 *max_clock_frequency = rscreen->info.max_sclk;
622 }
623 return sizeof(uint32_t);
624
625 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
626 if (ret) {
627 uint32_t *max_compute_units = ret;
628 *max_compute_units = rscreen->info.max_compute_units;
629 }
630 return sizeof(uint32_t);
631
632 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
633 if (ret) {
634 uint32_t *images_supported = ret;
635 *images_supported = 0;
636 }
637 return sizeof(uint32_t);
638 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
639 break; /* unused */
640 }
641
642 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
643 return 0;
644 }
645
646 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
647 {
648 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
649
650 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
651 rscreen->info.r600_clock_crystal_freq;
652 }
653
654 static int r600_get_driver_query_info(struct pipe_screen *screen,
655 unsigned index,
656 struct pipe_driver_query_info *info)
657 {
658 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
659 struct pipe_driver_query_info list[] = {
660 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
661 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
662 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
663 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}},
664 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
665 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES},
666 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
667 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
668 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
669 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}},
670 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}},
671 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
672 };
673 unsigned num_queries;
674
675 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
676 num_queries = Elements(list);
677 else
678 num_queries = 8;
679
680 if (!info)
681 return num_queries;
682
683 if (index >= num_queries)
684 return 0;
685
686 *info = list[index];
687 return 1;
688 }
689
690 static void r600_fence_reference(struct pipe_screen *screen,
691 struct pipe_fence_handle **ptr,
692 struct pipe_fence_handle *fence)
693 {
694 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
695
696 rws->fence_reference(ptr, fence);
697 }
698
699 static boolean r600_fence_signalled(struct pipe_screen *screen,
700 struct pipe_fence_handle *fence)
701 {
702 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
703
704 return rws->fence_wait(rws, fence, 0);
705 }
706
707 static boolean r600_fence_finish(struct pipe_screen *screen,
708 struct pipe_fence_handle *fence,
709 uint64_t timeout)
710 {
711 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
712
713 return rws->fence_wait(rws, fence, timeout);
714 }
715
716 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
717 uint32_t tiling_config)
718 {
719 switch ((tiling_config & 0xe) >> 1) {
720 case 0:
721 rscreen->tiling_info.num_channels = 1;
722 break;
723 case 1:
724 rscreen->tiling_info.num_channels = 2;
725 break;
726 case 2:
727 rscreen->tiling_info.num_channels = 4;
728 break;
729 case 3:
730 rscreen->tiling_info.num_channels = 8;
731 break;
732 default:
733 return false;
734 }
735
736 switch ((tiling_config & 0x30) >> 4) {
737 case 0:
738 rscreen->tiling_info.num_banks = 4;
739 break;
740 case 1:
741 rscreen->tiling_info.num_banks = 8;
742 break;
743 default:
744 return false;
745
746 }
747 switch ((tiling_config & 0xc0) >> 6) {
748 case 0:
749 rscreen->tiling_info.group_bytes = 256;
750 break;
751 case 1:
752 rscreen->tiling_info.group_bytes = 512;
753 break;
754 default:
755 return false;
756 }
757 return true;
758 }
759
760 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
761 uint32_t tiling_config)
762 {
763 switch (tiling_config & 0xf) {
764 case 0:
765 rscreen->tiling_info.num_channels = 1;
766 break;
767 case 1:
768 rscreen->tiling_info.num_channels = 2;
769 break;
770 case 2:
771 rscreen->tiling_info.num_channels = 4;
772 break;
773 case 3:
774 rscreen->tiling_info.num_channels = 8;
775 break;
776 default:
777 return false;
778 }
779
780 switch ((tiling_config & 0xf0) >> 4) {
781 case 0:
782 rscreen->tiling_info.num_banks = 4;
783 break;
784 case 1:
785 rscreen->tiling_info.num_banks = 8;
786 break;
787 case 2:
788 rscreen->tiling_info.num_banks = 16;
789 break;
790 default:
791 return false;
792 }
793
794 switch ((tiling_config & 0xf00) >> 8) {
795 case 0:
796 rscreen->tiling_info.group_bytes = 256;
797 break;
798 case 1:
799 rscreen->tiling_info.group_bytes = 512;
800 break;
801 default:
802 return false;
803 }
804 return true;
805 }
806
807 static bool r600_init_tiling(struct r600_common_screen *rscreen)
808 {
809 uint32_t tiling_config = rscreen->info.r600_tiling_config;
810
811 /* set default group bytes, overridden by tiling info ioctl */
812 if (rscreen->chip_class <= R700) {
813 rscreen->tiling_info.group_bytes = 256;
814 } else {
815 rscreen->tiling_info.group_bytes = 512;
816 }
817
818 if (!tiling_config)
819 return true;
820
821 if (rscreen->chip_class <= R700) {
822 return r600_interpret_tiling(rscreen, tiling_config);
823 } else {
824 return evergreen_interpret_tiling(rscreen, tiling_config);
825 }
826 }
827
828 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
829 const struct pipe_resource *templ)
830 {
831 if (templ->target == PIPE_BUFFER) {
832 return r600_buffer_create(screen, templ, 4096);
833 } else {
834 return r600_texture_create(screen, templ);
835 }
836 }
837
838 bool r600_common_screen_init(struct r600_common_screen *rscreen,
839 struct radeon_winsys *ws)
840 {
841 ws->query_info(ws, &rscreen->info);
842
843 rscreen->b.get_name = r600_get_name;
844 rscreen->b.get_vendor = r600_get_vendor;
845 rscreen->b.get_device_vendor = r600_get_device_vendor;
846 rscreen->b.get_compute_param = r600_get_compute_param;
847 rscreen->b.get_paramf = r600_get_paramf;
848 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
849 rscreen->b.get_timestamp = r600_get_timestamp;
850 rscreen->b.fence_finish = r600_fence_finish;
851 rscreen->b.fence_reference = r600_fence_reference;
852 rscreen->b.fence_signalled = r600_fence_signalled;
853 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
854 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
855
856 if (rscreen->info.has_uvd) {
857 rscreen->b.get_video_param = rvid_get_video_param;
858 rscreen->b.is_video_format_supported = rvid_is_format_supported;
859 } else {
860 rscreen->b.get_video_param = r600_get_video_param;
861 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
862 }
863
864 r600_init_screen_texture_functions(rscreen);
865
866 rscreen->ws = ws;
867 rscreen->family = rscreen->info.family;
868 rscreen->chip_class = rscreen->info.chip_class;
869 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
870
871 if (!r600_init_tiling(rscreen)) {
872 return false;
873 }
874 util_format_s3tc_init();
875 pipe_mutex_init(rscreen->aux_context_lock);
876 pipe_mutex_init(rscreen->gpu_load_mutex);
877
878 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
879 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
880 PIPE_BIND_CUSTOM,
881 PIPE_USAGE_STAGING,
882 4096);
883 if (rscreen->trace_bo) {
884 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
885 PIPE_TRANSFER_UNSYNCHRONIZED);
886 }
887 }
888
889 if (rscreen->debug_flags & DBG_INFO) {
890 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
891 printf("family = %i\n", rscreen->info.family);
892 printf("chip_class = %i\n", rscreen->info.chip_class);
893 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
894 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
895 printf("max_sclk = %i\n", rscreen->info.max_sclk);
896 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
897 printf("max_se = %i\n", rscreen->info.max_se);
898 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
899 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
900 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
901 printf("has_uvd = %i\n", rscreen->info.has_uvd);
902 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
903 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
904 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
905 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
906 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
907 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
908 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
909 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
910 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
911 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
912 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
913 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
914 }
915 return true;
916 }
917
918 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
919 {
920 r600_gpu_load_kill_thread(rscreen);
921
922 pipe_mutex_destroy(rscreen->gpu_load_mutex);
923 pipe_mutex_destroy(rscreen->aux_context_lock);
924 rscreen->aux_context->destroy(rscreen->aux_context);
925
926 if (rscreen->trace_bo) {
927 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
928 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
929 }
930
931 rscreen->ws->destroy(rscreen->ws);
932 FREE(rscreen);
933 }
934
935 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
936 const struct tgsi_token *tokens)
937 {
938 /* Compute shader don't have tgsi_tokens */
939 if (!tokens)
940 return (rscreen->debug_flags & DBG_CS) != 0;
941
942 switch (tgsi_get_processor_type(tokens)) {
943 case TGSI_PROCESSOR_VERTEX:
944 return (rscreen->debug_flags & DBG_VS) != 0;
945 case TGSI_PROCESSOR_GEOMETRY:
946 return (rscreen->debug_flags & DBG_GS) != 0;
947 case TGSI_PROCESSOR_FRAGMENT:
948 return (rscreen->debug_flags & DBG_PS) != 0;
949 case TGSI_PROCESSOR_COMPUTE:
950 return (rscreen->debug_flags & DBG_CS) != 0;
951 default:
952 return false;
953 }
954 }
955
956 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
957 unsigned offset, unsigned size, unsigned value,
958 bool is_framebuffer)
959 {
960 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
961
962 pipe_mutex_lock(rscreen->aux_context_lock);
963 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
964 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
965 pipe_mutex_unlock(rscreen->aux_context_lock);
966 }