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radeonsi: implement buffer_subdata without indirect calls
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 struct r600_multi_fence {
47 struct pipe_reference reference;
48 struct pipe_fence_handle *gfx;
49 struct pipe_fence_handle *sdma;
50 };
51
52 /*
53 * shader binary helpers.
54 */
55 void radeon_shader_binary_init(struct radeon_shader_binary *b)
56 {
57 memset(b, 0, sizeof(*b));
58 }
59
60 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
61 {
62 if (!b)
63 return;
64 FREE(b->code);
65 FREE(b->config);
66 FREE(b->rodata);
67 FREE(b->global_symbol_offsets);
68 FREE(b->relocs);
69 FREE(b->disasm_string);
70 FREE(b->llvm_ir_string);
71 }
72
73 /*
74 * pipe_context
75 */
76
77 void r600_draw_rectangle(struct blitter_context *blitter,
78 int x1, int y1, int x2, int y2, float depth,
79 enum blitter_attrib_type type,
80 const union pipe_color_union *attrib)
81 {
82 struct r600_common_context *rctx =
83 (struct r600_common_context*)util_blitter_get_pipe(blitter);
84 struct pipe_viewport_state viewport;
85 struct pipe_resource *buf = NULL;
86 unsigned offset = 0;
87 float *vb;
88
89 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
90 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
91 return;
92 }
93
94 /* Some operations (like color resolve on r6xx) don't work
95 * with the conventional primitive types.
96 * One that works is PT_RECTLIST, which we use here. */
97
98 /* setup viewport */
99 viewport.scale[0] = 1.0f;
100 viewport.scale[1] = 1.0f;
101 viewport.scale[2] = 1.0f;
102 viewport.translate[0] = 0.0f;
103 viewport.translate[1] = 0.0f;
104 viewport.translate[2] = 0.0f;
105 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
106
107 /* Upload vertices. The hw rectangle has only 3 vertices,
108 * I guess the 4th one is derived from the first 3.
109 * The vertex specification should match u_blitter's vertex element state. */
110 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
111 if (!buf)
112 return;
113
114 vb[0] = x1;
115 vb[1] = y1;
116 vb[2] = depth;
117 vb[3] = 1;
118
119 vb[8] = x1;
120 vb[9] = y2;
121 vb[10] = depth;
122 vb[11] = 1;
123
124 vb[16] = x2;
125 vb[17] = y1;
126 vb[18] = depth;
127 vb[19] = 1;
128
129 if (attrib) {
130 memcpy(vb+4, attrib->f, sizeof(float)*4);
131 memcpy(vb+12, attrib->f, sizeof(float)*4);
132 memcpy(vb+20, attrib->f, sizeof(float)*4);
133 }
134
135 /* draw */
136 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
137 R600_PRIM_RECTANGLE_LIST, 3, 2);
138 pipe_resource_reference(&buf, NULL);
139 }
140
141 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
142 struct r600_resource *dst, struct r600_resource *src)
143 {
144 uint64_t vram = 0, gtt = 0;
145
146 if (dst) {
147 if (dst->domains & RADEON_DOMAIN_VRAM)
148 vram += dst->buf->size;
149 else if (dst->domains & RADEON_DOMAIN_GTT)
150 gtt += dst->buf->size;
151 }
152 if (src) {
153 if (src->domains & RADEON_DOMAIN_VRAM)
154 vram += src->buf->size;
155 else if (src->domains & RADEON_DOMAIN_GTT)
156 gtt += src->buf->size;
157 }
158
159 /* Flush the GFX IB if DMA depends on it. */
160 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
161 ((dst &&
162 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
163 RADEON_USAGE_READWRITE)) ||
164 (src &&
165 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
166 RADEON_USAGE_WRITE))))
167 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
168
169 /* Flush if there's not enough space, or if the memory usage per IB
170 * is too large.
171 */
172 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
173 !ctx->ws->cs_memory_below_limit(ctx->dma.cs, vram, gtt)) {
174 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
175 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
176 }
177
178 /* If GPUVM is not supported, the CS checker needs 2 entries
179 * in the buffer list per packet, which has to be done manually.
180 */
181 if (ctx->screen->info.has_virtual_memory) {
182 if (dst)
183 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
184 RADEON_USAGE_WRITE,
185 RADEON_PRIO_SDMA_BUFFER);
186 if (src)
187 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
188 RADEON_USAGE_READ,
189 RADEON_PRIO_SDMA_BUFFER);
190 }
191 }
192
193 /* This is required to prevent read-after-write hazards. */
194 void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
195 {
196 struct radeon_winsys_cs *cs = rctx->dma.cs;
197
198 /* done at the end of DMA calls, so increment this. */
199 rctx->num_dma_calls++;
200
201 /* IBs using too little memory are limited by the IB submission overhead.
202 * IBs using too much memory are limited by the kernel/TTM overhead.
203 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
204 *
205 * This heuristic makes sure that DMA requests are executed
206 * very soon after the call is made and lowers memory usage.
207 * It improves texture upload performance by keeping the DMA
208 * engine busy while uploads are being submitted.
209 */
210 if (rctx->ws->cs_query_memory_usage(rctx->dma.cs) > 64 * 1024 * 1024) {
211 rctx->dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
212 return;
213 }
214
215 r600_need_dma_space(rctx, 1, NULL, NULL);
216
217 if (!radeon_emitted(cs, 0)) /* empty queue */
218 return;
219
220 /* NOP waits for idle on Evergreen and later. */
221 if (rctx->chip_class >= CIK)
222 radeon_emit(cs, 0x00000000); /* NOP */
223 else if (rctx->chip_class >= EVERGREEN)
224 radeon_emit(cs, 0xf0000000); /* NOP */
225 else {
226 /* TODO: R600-R700 should use the FENCE packet.
227 * CS checker support is required. */
228 }
229 }
230
231 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
232 {
233 }
234
235 void r600_preflush_suspend_features(struct r600_common_context *ctx)
236 {
237 /* suspend queries */
238 if (!LIST_IS_EMPTY(&ctx->active_queries))
239 r600_suspend_queries(ctx);
240
241 ctx->streamout.suspended = false;
242 if (ctx->streamout.begin_emitted) {
243 r600_emit_streamout_end(ctx);
244 ctx->streamout.suspended = true;
245 }
246 }
247
248 void r600_postflush_resume_features(struct r600_common_context *ctx)
249 {
250 if (ctx->streamout.suspended) {
251 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
252 r600_streamout_buffers_dirty(ctx);
253 }
254
255 /* resume queries */
256 if (!LIST_IS_EMPTY(&ctx->active_queries))
257 r600_resume_queries(ctx);
258 }
259
260 static void r600_flush_from_st(struct pipe_context *ctx,
261 struct pipe_fence_handle **fence,
262 unsigned flags)
263 {
264 struct pipe_screen *screen = ctx->screen;
265 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
266 unsigned rflags = 0;
267 struct pipe_fence_handle *gfx_fence = NULL;
268 struct pipe_fence_handle *sdma_fence = NULL;
269
270 if (flags & PIPE_FLUSH_END_OF_FRAME)
271 rflags |= RADEON_FLUSH_END_OF_FRAME;
272 if (flags & PIPE_FLUSH_DEFERRED)
273 rflags |= RADEON_FLUSH_ASYNC;
274
275 if (rctx->dma.cs) {
276 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
277 }
278 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
279
280 /* Both engines can signal out of order, so we need to keep both fences. */
281 if (gfx_fence || sdma_fence) {
282 struct r600_multi_fence *multi_fence =
283 CALLOC_STRUCT(r600_multi_fence);
284 if (!multi_fence)
285 return;
286
287 multi_fence->reference.count = 1;
288 multi_fence->gfx = gfx_fence;
289 multi_fence->sdma = sdma_fence;
290
291 screen->fence_reference(screen, fence, NULL);
292 *fence = (struct pipe_fence_handle*)multi_fence;
293 }
294 }
295
296 static void r600_flush_dma_ring(void *ctx, unsigned flags,
297 struct pipe_fence_handle **fence)
298 {
299 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
300 struct radeon_winsys_cs *cs = rctx->dma.cs;
301 struct radeon_saved_cs saved;
302 bool check_vm =
303 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
304 rctx->check_vm_faults;
305
306 if (!radeon_emitted(cs, 0)) {
307 if (fence)
308 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
309 return;
310 }
311
312 if (check_vm)
313 radeon_save_cs(rctx->ws, cs, &saved);
314
315 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
316 if (fence)
317 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
318
319 if (check_vm) {
320 /* Use conservative timeout 800ms, after which we won't wait any
321 * longer and assume the GPU is hung.
322 */
323 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
324
325 rctx->check_vm_faults(rctx, &saved, RING_DMA);
326 radeon_clear_saved_cs(&saved);
327 }
328 }
329
330 /**
331 * Store a linearized copy of all chunks of \p cs together with the buffer
332 * list in \p saved.
333 */
334 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
335 struct radeon_saved_cs *saved)
336 {
337 void *buf;
338 unsigned i;
339
340 /* Save the IB chunks. */
341 saved->num_dw = cs->prev_dw + cs->current.cdw;
342 saved->ib = MALLOC(4 * saved->num_dw);
343 if (!saved->ib)
344 goto oom;
345
346 buf = saved->ib;
347 for (i = 0; i < cs->num_prev; ++i) {
348 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
349 buf += cs->prev[i].cdw;
350 }
351 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
352
353 /* Save the buffer list. */
354 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
355 saved->bo_list = CALLOC(saved->bo_count,
356 sizeof(saved->bo_list[0]));
357 if (!saved->bo_list) {
358 FREE(saved->ib);
359 goto oom;
360 }
361 ws->cs_get_buffer_list(cs, saved->bo_list);
362
363 return;
364
365 oom:
366 fprintf(stderr, "%s: out of memory\n", __func__);
367 memset(saved, 0, sizeof(*saved));
368 }
369
370 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
371 {
372 FREE(saved->ib);
373 FREE(saved->bo_list);
374
375 memset(saved, 0, sizeof(*saved));
376 }
377
378 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
379 {
380 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
381 unsigned latest = rctx->ws->query_value(rctx->ws,
382 RADEON_GPU_RESET_COUNTER);
383
384 if (rctx->gpu_reset_counter == latest)
385 return PIPE_NO_RESET;
386
387 rctx->gpu_reset_counter = latest;
388 return PIPE_UNKNOWN_CONTEXT_RESET;
389 }
390
391 static void r600_set_debug_callback(struct pipe_context *ctx,
392 const struct pipe_debug_callback *cb)
393 {
394 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
395
396 if (cb)
397 rctx->debug = *cb;
398 else
399 memset(&rctx->debug, 0, sizeof(rctx->debug));
400 }
401
402 bool r600_common_context_init(struct r600_common_context *rctx,
403 struct r600_common_screen *rscreen,
404 unsigned context_flags)
405 {
406 util_slab_create(&rctx->pool_transfers,
407 sizeof(struct r600_transfer), 64,
408 UTIL_SLAB_SINGLETHREADED);
409
410 rctx->screen = rscreen;
411 rctx->ws = rscreen->ws;
412 rctx->family = rscreen->family;
413 rctx->chip_class = rscreen->chip_class;
414
415 if (rscreen->chip_class >= CIK)
416 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
417 else if (rscreen->chip_class >= EVERGREEN)
418 rctx->max_db = 8;
419 else
420 rctx->max_db = 4;
421
422 rctx->b.invalidate_resource = r600_invalidate_resource;
423 rctx->b.transfer_map = u_transfer_map_vtbl;
424 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
425 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
426 rctx->b.texture_subdata = u_default_texture_subdata;
427 rctx->b.memory_barrier = r600_memory_barrier;
428 rctx->b.flush = r600_flush_from_st;
429 rctx->b.set_debug_callback = r600_set_debug_callback;
430
431 /* evergreen_compute.c has a special codepath for global buffers.
432 * Everything else can use the direct path.
433 */
434 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
435 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
436 rctx->b.buffer_subdata = u_default_buffer_subdata;
437 else
438 rctx->b.buffer_subdata = r600_buffer_subdata;
439
440 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
441 rctx->b.get_device_reset_status = r600_get_reset_status;
442 rctx->gpu_reset_counter =
443 rctx->ws->query_value(rctx->ws,
444 RADEON_GPU_RESET_COUNTER);
445 }
446
447 LIST_INITHEAD(&rctx->texture_buffers);
448
449 r600_init_context_texture_functions(rctx);
450 r600_init_viewport_functions(rctx);
451 r600_streamout_init(rctx);
452 r600_query_init(rctx);
453 cayman_init_msaa(&rctx->b);
454
455 rctx->allocator_zeroed_memory =
456 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
457 0, PIPE_USAGE_DEFAULT, true);
458 if (!rctx->allocator_zeroed_memory)
459 return false;
460
461 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
462 PIPE_BIND_INDEX_BUFFER |
463 PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
464 if (!rctx->uploader)
465 return false;
466
467 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
468 if (!rctx->ctx)
469 return false;
470
471 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
472 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
473 r600_flush_dma_ring,
474 rctx);
475 rctx->dma.flush = r600_flush_dma_ring;
476 }
477
478 return true;
479 }
480
481 void r600_common_context_cleanup(struct r600_common_context *rctx)
482 {
483 unsigned i,j;
484
485 /* Release DCC stats. */
486 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
487 assert(!rctx->dcc_stats[i].query_active);
488
489 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
490 if (rctx->dcc_stats[i].ps_stats[j])
491 rctx->b.destroy_query(&rctx->b,
492 rctx->dcc_stats[i].ps_stats[j]);
493
494 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
495 }
496
497 if (rctx->gfx.cs)
498 rctx->ws->cs_destroy(rctx->gfx.cs);
499 if (rctx->dma.cs)
500 rctx->ws->cs_destroy(rctx->dma.cs);
501 if (rctx->ctx)
502 rctx->ws->ctx_destroy(rctx->ctx);
503
504 if (rctx->uploader) {
505 u_upload_destroy(rctx->uploader);
506 }
507
508 util_slab_destroy(&rctx->pool_transfers);
509
510 if (rctx->allocator_zeroed_memory) {
511 u_suballocator_destroy(rctx->allocator_zeroed_memory);
512 }
513 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
514 }
515
516 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
517 {
518 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
519 struct r600_resource *rr = (struct r600_resource *)r;
520
521 if (!r) {
522 return;
523 }
524
525 /*
526 * The idea is to compute a gross estimate of memory requirement of
527 * each draw call. After each draw call, memory will be precisely
528 * accounted. So the uncertainty is only on the current draw call.
529 * In practice this gave very good estimate (+/- 10% of the target
530 * memory limit).
531 */
532 if (rr->domains & RADEON_DOMAIN_VRAM)
533 rctx->vram += rr->buf->size;
534 else if (rr->domains & RADEON_DOMAIN_GTT)
535 rctx->gtt += rr->buf->size;
536 }
537
538 /*
539 * pipe_screen
540 */
541
542 static const struct debug_named_value common_debug_options[] = {
543 /* logging */
544 { "tex", DBG_TEX, "Print texture info" },
545 { "compute", DBG_COMPUTE, "Print compute info" },
546 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
547 { "info", DBG_INFO, "Print driver information" },
548
549 /* shaders */
550 { "fs", DBG_FS, "Print fetch shaders" },
551 { "vs", DBG_VS, "Print vertex shaders" },
552 { "gs", DBG_GS, "Print geometry shaders" },
553 { "ps", DBG_PS, "Print pixel shaders" },
554 { "cs", DBG_CS, "Print compute shaders" },
555 { "tcs", DBG_TCS, "Print tessellation control shaders" },
556 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
557 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
558 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
559 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
560 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
561
562 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
563
564 /* features */
565 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
566 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
567 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
568 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
569 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
570 { "notiling", DBG_NO_TILING, "Disable tiling" },
571 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
572 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
573 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
574 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
575 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
576 { "nodcc", DBG_NO_DCC, "Disable DCC." },
577 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
578 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
579 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
580 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
581 { "noce", DBG_NO_CE, "Disable the constant engine"},
582 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
583 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
584
585 DEBUG_NAMED_VALUE_END /* must be last */
586 };
587
588 static const char* r600_get_vendor(struct pipe_screen* pscreen)
589 {
590 return "X.Org";
591 }
592
593 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
594 {
595 return "AMD";
596 }
597
598 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
599 {
600 switch (rscreen->info.family) {
601 case CHIP_R600: return "AMD R600";
602 case CHIP_RV610: return "AMD RV610";
603 case CHIP_RV630: return "AMD RV630";
604 case CHIP_RV670: return "AMD RV670";
605 case CHIP_RV620: return "AMD RV620";
606 case CHIP_RV635: return "AMD RV635";
607 case CHIP_RS780: return "AMD RS780";
608 case CHIP_RS880: return "AMD RS880";
609 case CHIP_RV770: return "AMD RV770";
610 case CHIP_RV730: return "AMD RV730";
611 case CHIP_RV710: return "AMD RV710";
612 case CHIP_RV740: return "AMD RV740";
613 case CHIP_CEDAR: return "AMD CEDAR";
614 case CHIP_REDWOOD: return "AMD REDWOOD";
615 case CHIP_JUNIPER: return "AMD JUNIPER";
616 case CHIP_CYPRESS: return "AMD CYPRESS";
617 case CHIP_HEMLOCK: return "AMD HEMLOCK";
618 case CHIP_PALM: return "AMD PALM";
619 case CHIP_SUMO: return "AMD SUMO";
620 case CHIP_SUMO2: return "AMD SUMO2";
621 case CHIP_BARTS: return "AMD BARTS";
622 case CHIP_TURKS: return "AMD TURKS";
623 case CHIP_CAICOS: return "AMD CAICOS";
624 case CHIP_CAYMAN: return "AMD CAYMAN";
625 case CHIP_ARUBA: return "AMD ARUBA";
626 case CHIP_TAHITI: return "AMD TAHITI";
627 case CHIP_PITCAIRN: return "AMD PITCAIRN";
628 case CHIP_VERDE: return "AMD CAPE VERDE";
629 case CHIP_OLAND: return "AMD OLAND";
630 case CHIP_HAINAN: return "AMD HAINAN";
631 case CHIP_BONAIRE: return "AMD BONAIRE";
632 case CHIP_KAVERI: return "AMD KAVERI";
633 case CHIP_KABINI: return "AMD KABINI";
634 case CHIP_HAWAII: return "AMD HAWAII";
635 case CHIP_MULLINS: return "AMD MULLINS";
636 case CHIP_TONGA: return "AMD TONGA";
637 case CHIP_ICELAND: return "AMD ICELAND";
638 case CHIP_CARRIZO: return "AMD CARRIZO";
639 case CHIP_FIJI: return "AMD FIJI";
640 case CHIP_POLARIS10: return "AMD POLARIS10";
641 case CHIP_POLARIS11: return "AMD POLARIS11";
642 case CHIP_STONEY: return "AMD STONEY";
643 default: return "AMD unknown";
644 }
645 }
646
647 static const char* r600_get_name(struct pipe_screen* pscreen)
648 {
649 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
650
651 return rscreen->renderer_string;
652 }
653
654 static float r600_get_paramf(struct pipe_screen* pscreen,
655 enum pipe_capf param)
656 {
657 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
658
659 switch (param) {
660 case PIPE_CAPF_MAX_LINE_WIDTH:
661 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
662 case PIPE_CAPF_MAX_POINT_WIDTH:
663 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
664 if (rscreen->family >= CHIP_CEDAR)
665 return 16384.0f;
666 else
667 return 8192.0f;
668 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
669 return 16.0f;
670 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
671 return 16.0f;
672 case PIPE_CAPF_GUARD_BAND_LEFT:
673 case PIPE_CAPF_GUARD_BAND_TOP:
674 case PIPE_CAPF_GUARD_BAND_RIGHT:
675 case PIPE_CAPF_GUARD_BAND_BOTTOM:
676 return 0.0f;
677 }
678 return 0.0f;
679 }
680
681 static int r600_get_video_param(struct pipe_screen *screen,
682 enum pipe_video_profile profile,
683 enum pipe_video_entrypoint entrypoint,
684 enum pipe_video_cap param)
685 {
686 switch (param) {
687 case PIPE_VIDEO_CAP_SUPPORTED:
688 return vl_profile_supported(screen, profile, entrypoint);
689 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
690 return 1;
691 case PIPE_VIDEO_CAP_MAX_WIDTH:
692 case PIPE_VIDEO_CAP_MAX_HEIGHT:
693 return vl_video_buffer_max_size(screen);
694 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
695 return PIPE_FORMAT_NV12;
696 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
697 return false;
698 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
699 return false;
700 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
701 return true;
702 case PIPE_VIDEO_CAP_MAX_LEVEL:
703 return vl_level_supported(screen, profile);
704 default:
705 return 0;
706 }
707 }
708
709 const char *r600_get_llvm_processor_name(enum radeon_family family)
710 {
711 switch (family) {
712 case CHIP_R600:
713 case CHIP_RV630:
714 case CHIP_RV635:
715 case CHIP_RV670:
716 return "r600";
717 case CHIP_RV610:
718 case CHIP_RV620:
719 case CHIP_RS780:
720 case CHIP_RS880:
721 return "rs880";
722 case CHIP_RV710:
723 return "rv710";
724 case CHIP_RV730:
725 return "rv730";
726 case CHIP_RV740:
727 case CHIP_RV770:
728 return "rv770";
729 case CHIP_PALM:
730 case CHIP_CEDAR:
731 return "cedar";
732 case CHIP_SUMO:
733 case CHIP_SUMO2:
734 return "sumo";
735 case CHIP_REDWOOD:
736 return "redwood";
737 case CHIP_JUNIPER:
738 return "juniper";
739 case CHIP_HEMLOCK:
740 case CHIP_CYPRESS:
741 return "cypress";
742 case CHIP_BARTS:
743 return "barts";
744 case CHIP_TURKS:
745 return "turks";
746 case CHIP_CAICOS:
747 return "caicos";
748 case CHIP_CAYMAN:
749 case CHIP_ARUBA:
750 return "cayman";
751
752 case CHIP_TAHITI: return "tahiti";
753 case CHIP_PITCAIRN: return "pitcairn";
754 case CHIP_VERDE: return "verde";
755 case CHIP_OLAND: return "oland";
756 case CHIP_HAINAN: return "hainan";
757 case CHIP_BONAIRE: return "bonaire";
758 case CHIP_KABINI: return "kabini";
759 case CHIP_KAVERI: return "kaveri";
760 case CHIP_HAWAII: return "hawaii";
761 case CHIP_MULLINS:
762 return "mullins";
763 case CHIP_TONGA: return "tonga";
764 case CHIP_ICELAND: return "iceland";
765 case CHIP_CARRIZO: return "carrizo";
766 #if HAVE_LLVM <= 0x0307
767 case CHIP_FIJI: return "tonga";
768 case CHIP_STONEY: return "carrizo";
769 #else
770 case CHIP_FIJI: return "fiji";
771 case CHIP_STONEY: return "stoney";
772 #endif
773 #if HAVE_LLVM <= 0x0308
774 case CHIP_POLARIS10: return "tonga";
775 case CHIP_POLARIS11: return "tonga";
776 #else
777 case CHIP_POLARIS10: return "polaris10";
778 case CHIP_POLARIS11: return "polaris11";
779 #endif
780 default: return "";
781 }
782 }
783
784 static int r600_get_compute_param(struct pipe_screen *screen,
785 enum pipe_shader_ir ir_type,
786 enum pipe_compute_cap param,
787 void *ret)
788 {
789 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
790
791 //TODO: select these params by asic
792 switch (param) {
793 case PIPE_COMPUTE_CAP_IR_TARGET: {
794 const char *gpu;
795 const char *triple;
796 if (rscreen->family <= CHIP_ARUBA) {
797 triple = "r600--";
798 } else {
799 triple = "amdgcn--";
800 }
801 switch(rscreen->family) {
802 /* Clang < 3.6 is missing Hainan in its list of
803 * GPUs, so we need to use the name of a similar GPU.
804 */
805 default:
806 gpu = r600_get_llvm_processor_name(rscreen->family);
807 break;
808 }
809 if (ret) {
810 sprintf(ret, "%s-%s", gpu, triple);
811 }
812 /* +2 for dash and terminating NIL byte */
813 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
814 }
815 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
816 if (ret) {
817 uint64_t *grid_dimension = ret;
818 grid_dimension[0] = 3;
819 }
820 return 1 * sizeof(uint64_t);
821
822 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
823 if (ret) {
824 uint64_t *grid_size = ret;
825 grid_size[0] = 65535;
826 grid_size[1] = 65535;
827 grid_size[2] = 65535;
828 }
829 return 3 * sizeof(uint64_t) ;
830
831 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
832 if (ret) {
833 uint64_t *block_size = ret;
834 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
835 ir_type == PIPE_SHADER_IR_TGSI) {
836 block_size[0] = 2048;
837 block_size[1] = 2048;
838 block_size[2] = 2048;
839 } else {
840 block_size[0] = 256;
841 block_size[1] = 256;
842 block_size[2] = 256;
843 }
844 }
845 return 3 * sizeof(uint64_t);
846
847 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
848 if (ret) {
849 uint64_t *max_threads_per_block = ret;
850 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
851 ir_type == PIPE_SHADER_IR_TGSI)
852 *max_threads_per_block = 2048;
853 else
854 *max_threads_per_block = 256;
855 }
856 return sizeof(uint64_t);
857
858 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
859 if (ret) {
860 uint64_t *max_global_size = ret;
861 uint64_t max_mem_alloc_size;
862
863 r600_get_compute_param(screen, ir_type,
864 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
865 &max_mem_alloc_size);
866
867 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
868 * 1/4 of the MAX_GLOBAL_SIZE. Since the
869 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
870 * make sure we never report more than
871 * 4 * MAX_MEM_ALLOC_SIZE.
872 */
873 *max_global_size = MIN2(4 * max_mem_alloc_size,
874 MAX2(rscreen->info.gart_size,
875 rscreen->info.vram_size));
876 }
877 return sizeof(uint64_t);
878
879 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
880 if (ret) {
881 uint64_t *max_local_size = ret;
882 /* Value reported by the closed source driver. */
883 *max_local_size = 32768;
884 }
885 return sizeof(uint64_t);
886
887 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
888 if (ret) {
889 uint64_t *max_input_size = ret;
890 /* Value reported by the closed source driver. */
891 *max_input_size = 1024;
892 }
893 return sizeof(uint64_t);
894
895 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
896 if (ret) {
897 uint64_t *max_mem_alloc_size = ret;
898
899 *max_mem_alloc_size = rscreen->info.max_alloc_size;
900 }
901 return sizeof(uint64_t);
902
903 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
904 if (ret) {
905 uint32_t *max_clock_frequency = ret;
906 *max_clock_frequency = rscreen->info.max_shader_clock;
907 }
908 return sizeof(uint32_t);
909
910 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
911 if (ret) {
912 uint32_t *max_compute_units = ret;
913 *max_compute_units = rscreen->info.num_good_compute_units;
914 }
915 return sizeof(uint32_t);
916
917 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
918 if (ret) {
919 uint32_t *images_supported = ret;
920 *images_supported = 0;
921 }
922 return sizeof(uint32_t);
923 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
924 break; /* unused */
925 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
926 if (ret) {
927 uint32_t *subgroup_size = ret;
928 *subgroup_size = r600_wavefront_size(rscreen->family);
929 }
930 return sizeof(uint32_t);
931 }
932
933 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
934 return 0;
935 }
936
937 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
938 {
939 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
940
941 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
942 rscreen->info.clock_crystal_freq;
943 }
944
945 static void r600_fence_reference(struct pipe_screen *screen,
946 struct pipe_fence_handle **dst,
947 struct pipe_fence_handle *src)
948 {
949 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
950 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
951 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
952
953 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
954 ws->fence_reference(&(*rdst)->gfx, NULL);
955 ws->fence_reference(&(*rdst)->sdma, NULL);
956 FREE(*rdst);
957 }
958 *rdst = rsrc;
959 }
960
961 static boolean r600_fence_finish(struct pipe_screen *screen,
962 struct pipe_fence_handle *fence,
963 uint64_t timeout)
964 {
965 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
966 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
967 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
968
969 if (rfence->sdma) {
970 if (!rws->fence_wait(rws, rfence->sdma, timeout))
971 return false;
972
973 /* Recompute the timeout after waiting. */
974 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
975 int64_t time = os_time_get_nano();
976 timeout = abs_timeout > time ? abs_timeout - time : 0;
977 }
978 }
979
980 if (!rfence->gfx)
981 return true;
982
983 return rws->fence_wait(rws, rfence->gfx, timeout);
984 }
985
986 static void r600_query_memory_info(struct pipe_screen *screen,
987 struct pipe_memory_info *info)
988 {
989 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
990 struct radeon_winsys *ws = rscreen->ws;
991 unsigned vram_usage, gtt_usage;
992
993 info->total_device_memory = rscreen->info.vram_size / 1024;
994 info->total_staging_memory = rscreen->info.gart_size / 1024;
995
996 /* The real TTM memory usage is somewhat random, because:
997 *
998 * 1) TTM delays freeing memory, because it can only free it after
999 * fences expire.
1000 *
1001 * 2) The memory usage can be really low if big VRAM evictions are
1002 * taking place, but the real usage is well above the size of VRAM.
1003 *
1004 * Instead, return statistics of this process.
1005 */
1006 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1007 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1008
1009 info->avail_device_memory =
1010 vram_usage <= info->total_device_memory ?
1011 info->total_device_memory - vram_usage : 0;
1012 info->avail_staging_memory =
1013 gtt_usage <= info->total_staging_memory ?
1014 info->total_staging_memory - gtt_usage : 0;
1015
1016 info->device_memory_evicted =
1017 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1018 /* Just return the number of evicted 64KB pages. */
1019 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1020 }
1021
1022 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1023 const struct pipe_resource *templ)
1024 {
1025 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1026
1027 if (templ->target == PIPE_BUFFER) {
1028 return r600_buffer_create(screen, templ,
1029 rscreen->info.gart_page_size);
1030 } else {
1031 return r600_texture_create(screen, templ);
1032 }
1033 }
1034
1035 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1036 struct radeon_winsys *ws)
1037 {
1038 char llvm_string[32] = {}, kernel_version[128] = {};
1039 struct utsname uname_data;
1040
1041 ws->query_info(ws, &rscreen->info);
1042
1043 if (uname(&uname_data) == 0)
1044 snprintf(kernel_version, sizeof(kernel_version),
1045 " / %s", uname_data.release);
1046
1047 #if HAVE_LLVM
1048 snprintf(llvm_string, sizeof(llvm_string),
1049 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1050 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1051 #endif
1052
1053 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1054 "%s (DRM %i.%i.%i%s%s)",
1055 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1056 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1057 kernel_version, llvm_string);
1058
1059 rscreen->b.get_name = r600_get_name;
1060 rscreen->b.get_vendor = r600_get_vendor;
1061 rscreen->b.get_device_vendor = r600_get_device_vendor;
1062 rscreen->b.get_compute_param = r600_get_compute_param;
1063 rscreen->b.get_paramf = r600_get_paramf;
1064 rscreen->b.get_timestamp = r600_get_timestamp;
1065 rscreen->b.fence_finish = r600_fence_finish;
1066 rscreen->b.fence_reference = r600_fence_reference;
1067 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1068 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1069 rscreen->b.query_memory_info = r600_query_memory_info;
1070
1071 if (rscreen->info.has_uvd) {
1072 rscreen->b.get_video_param = rvid_get_video_param;
1073 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1074 } else {
1075 rscreen->b.get_video_param = r600_get_video_param;
1076 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1077 }
1078
1079 r600_init_screen_texture_functions(rscreen);
1080 r600_init_screen_query_functions(rscreen);
1081
1082 rscreen->ws = ws;
1083 rscreen->family = rscreen->info.family;
1084 rscreen->chip_class = rscreen->info.chip_class;
1085 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1086
1087 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1088 if (rscreen->force_aniso >= 0) {
1089 printf("radeon: Forcing anisotropy filter to %ix\n",
1090 /* round down to a power of two */
1091 1 << util_logbase2(rscreen->force_aniso));
1092 }
1093
1094 util_format_s3tc_init();
1095 pipe_mutex_init(rscreen->aux_context_lock);
1096 pipe_mutex_init(rscreen->gpu_load_mutex);
1097
1098 if (rscreen->debug_flags & DBG_INFO) {
1099 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1100 printf("family = %i (%s)\n", rscreen->info.family,
1101 r600_get_chip_name(rscreen));
1102 printf("chip_class = %i\n", rscreen->info.chip_class);
1103 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1104 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1105 printf("max_alloc_size = %i MB\n",
1106 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1107 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1108 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1109 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1110 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1111 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1112 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1113 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1114 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1115 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1116 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1117
1118 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1119 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1120 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1121 printf("max_se = %i\n", rscreen->info.max_se);
1122 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1123
1124 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1125 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1126 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1127 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1128 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1129 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1130 }
1131 return true;
1132 }
1133
1134 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1135 {
1136 r600_perfcounters_destroy(rscreen);
1137 r600_gpu_load_kill_thread(rscreen);
1138
1139 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1140 pipe_mutex_destroy(rscreen->aux_context_lock);
1141 rscreen->aux_context->destroy(rscreen->aux_context);
1142
1143 rscreen->ws->destroy(rscreen->ws);
1144 FREE(rscreen);
1145 }
1146
1147 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1148 unsigned processor)
1149 {
1150 switch (processor) {
1151 case PIPE_SHADER_VERTEX:
1152 return (rscreen->debug_flags & DBG_VS) != 0;
1153 case PIPE_SHADER_TESS_CTRL:
1154 return (rscreen->debug_flags & DBG_TCS) != 0;
1155 case PIPE_SHADER_TESS_EVAL:
1156 return (rscreen->debug_flags & DBG_TES) != 0;
1157 case PIPE_SHADER_GEOMETRY:
1158 return (rscreen->debug_flags & DBG_GS) != 0;
1159 case PIPE_SHADER_FRAGMENT:
1160 return (rscreen->debug_flags & DBG_PS) != 0;
1161 case PIPE_SHADER_COMPUTE:
1162 return (rscreen->debug_flags & DBG_CS) != 0;
1163 default:
1164 return false;
1165 }
1166 }
1167
1168 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1169 uint64_t offset, uint64_t size, unsigned value,
1170 enum r600_coherency coher)
1171 {
1172 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1173
1174 pipe_mutex_lock(rscreen->aux_context_lock);
1175 rctx->clear_buffer(&rctx->b, dst, offset, size, value, coher);
1176 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1177 pipe_mutex_unlock(rscreen->aux_context_lock);
1178 }