src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/list.h"
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "os/os_time.h"
  36 #include "vl/vl_decoder.h"
  37 #include "vl/vl_video_buffer.h"
  38 #include "radeon/radeon_video.h"
  39 #include <inttypes.h>
  40
  41 #ifndef HAVE_LLVM
  42 #define HAVE_LLVM 0
  43 #endif
  44
  45 struct r600_multi_fence {
  46         struct pipe_reference reference;
  47         struct pipe_fence_handle *gfx;
  48         struct pipe_fence_handle *sdma;
  49 };
  50
  51 /*
  52  * shader binary helpers.
  53  */
  54 void radeon_shader_binary_init(struct radeon_shader_binary *b)
  55 {
  56         memset(b, 0, sizeof(*b));
  57 }
  58
  59 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
  60 {
  61         if (!b)
  62                 return;
  63         FREE(b->code);
  64         FREE(b->config);
  65         FREE(b->rodata);
  66         FREE(b->global_symbol_offsets);
  67         FREE(b->relocs);
  68         FREE(b->disasm_string);
  69 }
  70
  71 /*
  72  * pipe_context
  73  */
  74
  75 void r600_draw_rectangle(struct blitter_context *blitter,
  76                          int x1, int y1, int x2, int y2, float depth,
  77                          enum blitter_attrib_type type,
  78                          const union pipe_color_union *attrib)
  79 {
  80         struct r600_common_context *rctx =
  81                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  82         struct pipe_viewport_state viewport;
  83         struct pipe_resource *buf = NULL;
  84         unsigned offset = 0;
  85         float *vb;
  86
  87         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  88                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  89                 return;
  90         }
  91
  92         /* Some operations (like color resolve on r6xx) don't work
  93          * with the conventional primitive types.
  94          * One that works is PT_RECTLIST, which we use here. */
  95
  96         /* setup viewport */
  97         viewport.scale[0] = 1.0f;
  98         viewport.scale[1] = 1.0f;
  99         viewport.scale[2] = 1.0f;
 100         viewport.translate[0] = 0.0f;
 101         viewport.translate[1] = 0.0f;
 102         viewport.translate[2] = 0.0f;
 103         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
 104
 105         /* Upload vertices. The hw rectangle has only 3 vertices,
 106          * I guess the 4th one is derived from the first 3.
 107          * The vertex specification should match u_blitter's vertex element state. */
 108         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, 256, &offset, &buf, (void**)&vb);
 109         if (!buf)
 110                 return;
 111
 112         vb[0] = x1;
 113         vb[1] = y1;
 114         vb[2] = depth;
 115         vb[3] = 1;
 116
 117         vb[8] = x1;
 118         vb[9] = y2;
 119         vb[10] = depth;
 120         vb[11] = 1;
 121
 122         vb[16] = x2;
 123         vb[17] = y1;
 124         vb[18] = depth;
 125         vb[19] = 1;
 126
 127         if (attrib) {
 128                 memcpy(vb+4, attrib->f, sizeof(float)*4);
 129                 memcpy(vb+12, attrib->f, sizeof(float)*4);
 130                 memcpy(vb+20, attrib->f, sizeof(float)*4);
 131         }
 132
 133         /* draw */
 134         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 135                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 136         pipe_resource_reference(&buf, NULL);
 137 }
 138
 139 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
 140 {
 141         /* Flush the GFX IB if it's not empty. */
 142         if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
 143                 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 144
 145         /* Flush if there's not enough space. */
 146         if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
 147                 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 148                 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
 149         }
 150 }
 151
 152 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 153 {
 154 }
 155
 156 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 157 {
 158         /* suspend queries */
 159         if (!LIST_IS_EMPTY(&ctx->active_queries))
 160                 r600_suspend_queries(ctx);
 161
 162         ctx->streamout.suspended = false;
 163         if (ctx->streamout.begin_emitted) {
 164                 r600_emit_streamout_end(ctx);
 165                 ctx->streamout.suspended = true;
 166         }
 167 }
 168
 169 void r600_postflush_resume_features(struct r600_common_context *ctx)
 170 {
 171         if (ctx->streamout.suspended) {
 172                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 173                 r600_streamout_buffers_dirty(ctx);
 174         }
 175
 176         /* resume queries */
 177         if (!LIST_IS_EMPTY(&ctx->active_queries))
 178                 r600_resume_queries(ctx);
 179 }
 180
 181 static void r600_flush_from_st(struct pipe_context *ctx,
 182                                struct pipe_fence_handle **fence,
 183                                unsigned flags)
 184 {
 185         struct pipe_screen *screen = ctx->screen;
 186         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 187         unsigned rflags = 0;
 188         struct pipe_fence_handle *gfx_fence = NULL;
 189         struct pipe_fence_handle *sdma_fence = NULL;
 190
 191         if (flags & PIPE_FLUSH_END_OF_FRAME)
 192                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 193
 194         if (rctx->dma.cs) {
 195                 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
 196         }
 197         rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
 198
 199         /* Both engines can signal out of order, so we need to keep both fences. */
 200         if (gfx_fence || sdma_fence) {
 201                 struct r600_multi_fence *multi_fence =
 202                         CALLOC_STRUCT(r600_multi_fence);
 203                 if (!multi_fence)
 204                         return;
 205
 206                 multi_fence->reference.count = 1;
 207                 multi_fence->gfx = gfx_fence;
 208                 multi_fence->sdma = sdma_fence;
 209
 210                 screen->fence_reference(screen, fence, NULL);
 211                 *fence = (struct pipe_fence_handle*)multi_fence;
 212         }
 213 }
 214
 215 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 216                                 struct pipe_fence_handle **fence)
 217 {
 218         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 219         struct radeon_winsys_cs *cs = rctx->dma.cs;
 220
 221         if (cs->cdw)
 222                 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
 223         if (fence)
 224                 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
 225 }
 226
 227 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
 228 {
 229         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 230         unsigned latest = rctx->ws->query_value(rctx->ws,
 231                                                 RADEON_GPU_RESET_COUNTER);
 232
 233         if (rctx->gpu_reset_counter == latest)
 234                 return PIPE_NO_RESET;
 235
 236         rctx->gpu_reset_counter = latest;
 237         return PIPE_UNKNOWN_CONTEXT_RESET;
 238 }
 239
 240 static void r600_set_debug_callback(struct pipe_context *ctx,
 241                                     const struct pipe_debug_callback *cb)
 242 {
 243         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 244
 245         if (cb)
 246                 rctx->debug = *cb;
 247         else
 248                 memset(&rctx->debug, 0, sizeof(rctx->debug));
 249 }
 250
 251 bool r600_common_context_init(struct r600_common_context *rctx,
 252                               struct r600_common_screen *rscreen)
 253 {
 254         util_slab_create(&rctx->pool_transfers,
 255                          sizeof(struct r600_transfer), 64,
 256                          UTIL_SLAB_SINGLETHREADED);
 257
 258         rctx->screen = rscreen;
 259         rctx->ws = rscreen->ws;
 260         rctx->family = rscreen->family;
 261         rctx->chip_class = rscreen->chip_class;
 262
 263         if (rscreen->chip_class >= CIK)
 264                 rctx->max_db = MAX2(8, rscreen->info.num_render_backends);
 265         else if (rscreen->chip_class >= EVERGREEN)
 266                 rctx->max_db = 8;
 267         else
 268                 rctx->max_db = 4;
 269
 270         rctx->b.invalidate_resource = r600_invalidate_resource;
 271         rctx->b.transfer_map = u_transfer_map_vtbl;
 272         rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 273         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 274         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 275         rctx->b.memory_barrier = r600_memory_barrier;
 276         rctx->b.flush = r600_flush_from_st;
 277         rctx->b.set_debug_callback = r600_set_debug_callback;
 278
 279         if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
 280                 rctx->b.get_device_reset_status = r600_get_reset_status;
 281                 rctx->gpu_reset_counter =
 282                         rctx->ws->query_value(rctx->ws,
 283                                               RADEON_GPU_RESET_COUNTER);
 284         }
 285
 286         LIST_INITHEAD(&rctx->texture_buffers);
 287
 288         r600_init_context_texture_functions(rctx);
 289         r600_streamout_init(rctx);
 290         r600_query_init(rctx);
 291         cayman_init_msaa(&rctx->b);
 292
 293         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 294                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 295         if (!rctx->allocator_so_filled_size)
 296                 return false;
 297
 298         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
 299                                         PIPE_BIND_INDEX_BUFFER |
 300                                         PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
 301         if (!rctx->uploader)
 302                 return false;
 303
 304         rctx->ctx = rctx->ws->ctx_create(rctx->ws);
 305         if (!rctx->ctx)
 306                 return false;
 307
 308         if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 309                 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
 310                                                    r600_flush_dma_ring,
 311                                                    rctx);
 312                 rctx->dma.flush = r600_flush_dma_ring;
 313         }
 314
 315         return true;
 316 }
 317
 318 void r600_common_context_cleanup(struct r600_common_context *rctx)
 319 {
 320         if (rctx->gfx.cs)
 321                 rctx->ws->cs_destroy(rctx->gfx.cs);
 322         if (rctx->dma.cs)
 323                 rctx->ws->cs_destroy(rctx->dma.cs);
 324         if (rctx->ctx)
 325                 rctx->ws->ctx_destroy(rctx->ctx);
 326
 327         if (rctx->uploader) {
 328                 u_upload_destroy(rctx->uploader);
 329         }
 330
 331         util_slab_destroy(&rctx->pool_transfers);
 332
 333         if (rctx->allocator_so_filled_size) {
 334                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 335         }
 336         rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
 337 }
 338
 339 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 340 {
 341         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 342         struct r600_resource *rr = (struct r600_resource *)r;
 343
 344         if (!r) {
 345                 return;
 346         }
 347
 348         /*
 349          * The idea is to compute a gross estimate of memory requirement of
 350          * each draw call. After each draw call, memory will be precisely
 351          * accounted. So the uncertainty is only on the current draw call.
 352          * In practice this gave very good estimate (+/- 10% of the target
 353          * memory limit).
 354          */
 355         if (rr->domains & RADEON_DOMAIN_GTT) {
 356                 rctx->gtt += rr->buf->size;
 357         }
 358         if (rr->domains & RADEON_DOMAIN_VRAM) {
 359                 rctx->vram += rr->buf->size;
 360         }
 361 }
 362
 363 /*
 364  * pipe_screen
 365  */
 366
 367 static const struct debug_named_value common_debug_options[] = {
 368         /* logging */
 369         { "tex", DBG_TEX, "Print texture info" },
 370         { "compute", DBG_COMPUTE, "Print compute info" },
 371         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 372         { "info", DBG_INFO, "Print driver information" },
 373
 374         /* shaders */
 375         { "fs", DBG_FS, "Print fetch shaders" },
 376         { "vs", DBG_VS, "Print vertex shaders" },
 377         { "gs", DBG_GS, "Print geometry shaders" },
 378         { "ps", DBG_PS, "Print pixel shaders" },
 379         { "cs", DBG_CS, "Print compute shaders" },
 380         { "tcs", DBG_TCS, "Print tessellation control shaders" },
 381         { "tes", DBG_TES, "Print tessellation evaluation shaders" },
 382         { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
 383         { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
 384         { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
 385         { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
 386
 387         /* features */
 388         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 389         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 390         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 391         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 392         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 393         { "notiling", DBG_NO_TILING, "Disable tiling" },
 394         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 395         { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 396         { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
 397         { "nowc", DBG_NO_WC, "Disable GTT write combining" },
 398         { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
 399         { "nodcc", DBG_NO_DCC, "Disable DCC." },
 400         { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
 401         { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
 402         { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
 403         { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
 404
 405         DEBUG_NAMED_VALUE_END /* must be last */
 406 };
 407
 408 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 409 {
 410         return "X.Org";
 411 }
 412
 413 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
 414 {
 415         return "AMD";
 416 }
 417
 418 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
 419 {
 420         switch (rscreen->info.family) {
 421         case CHIP_R600: return "AMD R600";
 422         case CHIP_RV610: return "AMD RV610";
 423         case CHIP_RV630: return "AMD RV630";
 424         case CHIP_RV670: return "AMD RV670";
 425         case CHIP_RV620: return "AMD RV620";
 426         case CHIP_RV635: return "AMD RV635";
 427         case CHIP_RS780: return "AMD RS780";
 428         case CHIP_RS880: return "AMD RS880";
 429         case CHIP_RV770: return "AMD RV770";
 430         case CHIP_RV730: return "AMD RV730";
 431         case CHIP_RV710: return "AMD RV710";
 432         case CHIP_RV740: return "AMD RV740";
 433         case CHIP_CEDAR: return "AMD CEDAR";
 434         case CHIP_REDWOOD: return "AMD REDWOOD";
 435         case CHIP_JUNIPER: return "AMD JUNIPER";
 436         case CHIP_CYPRESS: return "AMD CYPRESS";
 437         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 438         case CHIP_PALM: return "AMD PALM";
 439         case CHIP_SUMO: return "AMD SUMO";
 440         case CHIP_SUMO2: return "AMD SUMO2";
 441         case CHIP_BARTS: return "AMD BARTS";
 442         case CHIP_TURKS: return "AMD TURKS";
 443         case CHIP_CAICOS: return "AMD CAICOS";
 444         case CHIP_CAYMAN: return "AMD CAYMAN";
 445         case CHIP_ARUBA: return "AMD ARUBA";
 446         case CHIP_TAHITI: return "AMD TAHITI";
 447         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 448         case CHIP_VERDE: return "AMD CAPE VERDE";
 449         case CHIP_OLAND: return "AMD OLAND";
 450         case CHIP_HAINAN: return "AMD HAINAN";
 451         case CHIP_BONAIRE: return "AMD BONAIRE";
 452         case CHIP_KAVERI: return "AMD KAVERI";
 453         case CHIP_KABINI: return "AMD KABINI";
 454         case CHIP_HAWAII: return "AMD HAWAII";
 455         case CHIP_MULLINS: return "AMD MULLINS";
 456         case CHIP_TONGA: return "AMD TONGA";
 457         case CHIP_ICELAND: return "AMD ICELAND";
 458         case CHIP_CARRIZO: return "AMD CARRIZO";
 459         case CHIP_FIJI: return "AMD FIJI";
 460         case CHIP_POLARIS10: return "AMD POLARIS10";
 461         case CHIP_POLARIS11: return "AMD POLARIS11";
 462         case CHIP_STONEY: return "AMD STONEY";
 463         default: return "AMD unknown";
 464         }
 465 }
 466
 467 static const char* r600_get_name(struct pipe_screen* pscreen)
 468 {
 469         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 470
 471         return rscreen->renderer_string;
 472 }
 473
 474 static float r600_get_paramf(struct pipe_screen* pscreen,
 475                              enum pipe_capf param)
 476 {
 477         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 478
 479         switch (param) {
 480         case PIPE_CAPF_MAX_LINE_WIDTH:
 481         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 482         case PIPE_CAPF_MAX_POINT_WIDTH:
 483         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 484                 if (rscreen->family >= CHIP_CEDAR)
 485                         return 16384.0f;
 486                 else
 487                         return 8192.0f;
 488         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 489                 return 16.0f;
 490         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 491                 return 16.0f;
 492         case PIPE_CAPF_GUARD_BAND_LEFT:
 493         case PIPE_CAPF_GUARD_BAND_TOP:
 494         case PIPE_CAPF_GUARD_BAND_RIGHT:
 495         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 496                 return 0.0f;
 497         }
 498         return 0.0f;
 499 }
 500
 501 static int r600_get_video_param(struct pipe_screen *screen,
 502                                 enum pipe_video_profile profile,
 503                                 enum pipe_video_entrypoint entrypoint,
 504                                 enum pipe_video_cap param)
 505 {
 506         switch (param) {
 507         case PIPE_VIDEO_CAP_SUPPORTED:
 508                 return vl_profile_supported(screen, profile, entrypoint);
 509         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 510                 return 1;
 511         case PIPE_VIDEO_CAP_MAX_WIDTH:
 512         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 513                 return vl_video_buffer_max_size(screen);
 514         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 515                 return PIPE_FORMAT_NV12;
 516         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 517                 return false;
 518         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 519                 return false;
 520         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 521                 return true;
 522         case PIPE_VIDEO_CAP_MAX_LEVEL:
 523                 return vl_level_supported(screen, profile);
 524         default:
 525                 return 0;
 526         }
 527 }
 528
 529 const char *r600_get_llvm_processor_name(enum radeon_family family)
 530 {
 531         switch (family) {
 532         case CHIP_R600:
 533         case CHIP_RV630:
 534         case CHIP_RV635:
 535         case CHIP_RV670:
 536                 return "r600";
 537         case CHIP_RV610:
 538         case CHIP_RV620:
 539         case CHIP_RS780:
 540         case CHIP_RS880:
 541                 return "rs880";
 542         case CHIP_RV710:
 543                 return "rv710";
 544         case CHIP_RV730:
 545                 return "rv730";
 546         case CHIP_RV740:
 547         case CHIP_RV770:
 548                 return "rv770";
 549         case CHIP_PALM:
 550         case CHIP_CEDAR:
 551                 return "cedar";
 552         case CHIP_SUMO:
 553         case CHIP_SUMO2:
 554                 return "sumo";
 555         case CHIP_REDWOOD:
 556                 return "redwood";
 557         case CHIP_JUNIPER:
 558                 return "juniper";
 559         case CHIP_HEMLOCK:
 560         case CHIP_CYPRESS:
 561                 return "cypress";
 562         case CHIP_BARTS:
 563                 return "barts";
 564         case CHIP_TURKS:
 565                 return "turks";
 566         case CHIP_CAICOS:
 567                 return "caicos";
 568         case CHIP_CAYMAN:
 569         case CHIP_ARUBA:
 570                 return "cayman";
 571
 572         case CHIP_TAHITI: return "tahiti";
 573         case CHIP_PITCAIRN: return "pitcairn";
 574         case CHIP_VERDE: return "verde";
 575         case CHIP_OLAND: return "oland";
 576         case CHIP_HAINAN: return "hainan";
 577         case CHIP_BONAIRE: return "bonaire";
 578         case CHIP_KABINI: return "kabini";
 579         case CHIP_KAVERI: return "kaveri";
 580         case CHIP_HAWAII: return "hawaii";
 581         case CHIP_MULLINS:
 582                 return "mullins";
 583         case CHIP_TONGA: return "tonga";
 584         case CHIP_ICELAND: return "iceland";
 585         case CHIP_CARRIZO: return "carrizo";
 586 #if HAVE_LLVM <= 0x0307
 587         case CHIP_FIJI: return "tonga";
 588         case CHIP_STONEY: return "carrizo";
 589 #else
 590         case CHIP_FIJI: return "fiji";
 591         case CHIP_STONEY: return "stoney";
 592 #endif
 593 #if HAVE_LLVM <= 0x0308
 594         case CHIP_POLARIS10: return "tonga";
 595         case CHIP_POLARIS11: return "tonga";
 596 #else
 597         case CHIP_POLARIS10: return "polaris10";
 598         case CHIP_POLARIS11: return "polaris11";
 599 #endif
 600         default: return "";
 601         }
 602 }
 603
 604 static int r600_get_compute_param(struct pipe_screen *screen,
 605         enum pipe_shader_ir ir_type,
 606         enum pipe_compute_cap param,
 607         void *ret)
 608 {
 609         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 610
 611         //TODO: select these params by asic
 612         switch (param) {
 613         case PIPE_COMPUTE_CAP_IR_TARGET: {
 614                 const char *gpu;
 615                 const char *triple;
 616                 if (rscreen->family <= CHIP_ARUBA) {
 617                         triple = "r600--";
 618                 } else {
 619                         triple = "amdgcn--";
 620                 }
 621                 switch(rscreen->family) {
 622                 /* Clang < 3.6 is missing Hainan in its list of
 623                  * GPUs, so we need to use the name of a similar GPU.
 624                  */
 625                 default:
 626                         gpu = r600_get_llvm_processor_name(rscreen->family);
 627                         break;
 628                 }
 629                 if (ret) {
 630                         sprintf(ret, "%s-%s", gpu, triple);
 631                 }
 632                 /* +2 for dash and terminating NIL byte */
 633                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 634         }
 635         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 636                 if (ret) {
 637                         uint64_t *grid_dimension = ret;
 638                         grid_dimension[0] = 3;
 639                 }
 640                 return 1 * sizeof(uint64_t);
 641
 642         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 643                 if (ret) {
 644                         uint64_t *grid_size = ret;
 645                         grid_size[0] = 65535;
 646                         grid_size[1] = 65535;
 647                         grid_size[2] = 1;
 648                 }
 649                 return 3 * sizeof(uint64_t) ;
 650
 651         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 652                 if (ret) {
 653                         uint64_t *block_size = ret;
 654                         block_size[0] = 256;
 655                         block_size[1] = 256;
 656                         block_size[2] = 256;
 657                 }
 658                 return 3 * sizeof(uint64_t);
 659
 660         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 661                 if (ret) {
 662                         uint64_t *max_threads_per_block = ret;
 663                         *max_threads_per_block = 256;
 664                 }
 665                 return sizeof(uint64_t);
 666
 667         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 668                 if (ret) {
 669                         uint64_t *max_global_size = ret;
 670                         uint64_t max_mem_alloc_size;
 671
 672                         r600_get_compute_param(screen, ir_type,
 673                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 674                                 &max_mem_alloc_size);
 675
 676                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 677                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 678                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 679                          * make sure we never report more than
 680                          * 4 * MAX_MEM_ALLOC_SIZE.
 681                          */
 682                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 683                                 rscreen->info.gart_size +
 684                                 rscreen->info.vram_size);
 685                 }
 686                 return sizeof(uint64_t);
 687
 688         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 689                 if (ret) {
 690                         uint64_t *max_local_size = ret;
 691                         /* Value reported by the closed source driver. */
 692                         *max_local_size = 32768;
 693                 }
 694                 return sizeof(uint64_t);
 695
 696         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 697                 if (ret) {
 698                         uint64_t *max_input_size = ret;
 699                         /* Value reported by the closed source driver. */
 700                         *max_input_size = 1024;
 701                 }
 702                 return sizeof(uint64_t);
 703
 704         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 705                 if (ret) {
 706                         uint64_t *max_mem_alloc_size = ret;
 707
 708                         /* XXX: The limit in older kernels is 256 MB.  We
 709                          * should add a query here for newer kernels.
 710                          */
 711                         *max_mem_alloc_size = 256 * 1024 * 1024;
 712                 }
 713                 return sizeof(uint64_t);
 714
 715         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 716                 if (ret) {
 717                         uint32_t *max_clock_frequency = ret;
 718                         *max_clock_frequency = rscreen->info.max_shader_clock;
 719                 }
 720                 return sizeof(uint32_t);
 721
 722         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 723                 if (ret) {
 724                         uint32_t *max_compute_units = ret;
 725                         *max_compute_units = rscreen->info.num_good_compute_units;
 726                 }
 727                 return sizeof(uint32_t);
 728
 729         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 730                 if (ret) {
 731                         uint32_t *images_supported = ret;
 732                         *images_supported = 0;
 733                 }
 734                 return sizeof(uint32_t);
 735         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 736                 break; /* unused */
 737         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 738                 if (ret) {
 739                         uint32_t *subgroup_size = ret;
 740                         *subgroup_size = r600_wavefront_size(rscreen->family);
 741                 }
 742                 return sizeof(uint32_t);
 743         }
 744
 745         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 746         return 0;
 747 }
 748
 749 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 750 {
 751         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 752
 753         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 754                         rscreen->info.clock_crystal_freq;
 755 }
 756
 757 static void r600_fence_reference(struct pipe_screen *screen,
 758                                  struct pipe_fence_handle **dst,
 759                                  struct pipe_fence_handle *src)
 760 {
 761         struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
 762         struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
 763         struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
 764
 765         if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 766                 ws->fence_reference(&(*rdst)->gfx, NULL);
 767                 ws->fence_reference(&(*rdst)->sdma, NULL);
 768                 FREE(*rdst);
 769         }
 770         *rdst = rsrc;
 771 }
 772
 773 static boolean r600_fence_finish(struct pipe_screen *screen,
 774                                  struct pipe_fence_handle *fence,
 775                                  uint64_t timeout)
 776 {
 777         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 778         struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
 779         int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 780
 781         if (rfence->sdma) {
 782                 if (!rws->fence_wait(rws, rfence->sdma, timeout))
 783                         return false;
 784
 785                 /* Recompute the timeout after waiting. */
 786                 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
 787                         int64_t time = os_time_get_nano();
 788                         timeout = abs_timeout > time ? abs_timeout - time : 0;
 789                 }
 790         }
 791
 792         if (!rfence->gfx)
 793                 return true;
 794
 795         return rws->fence_wait(rws, rfence->gfx, timeout);
 796 }
 797
 798 static void r600_query_memory_info(struct pipe_screen *screen,
 799                                    struct pipe_memory_info *info)
 800 {
 801         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 802         struct radeon_winsys *ws = rscreen->ws;
 803         unsigned vram_usage, gtt_usage;
 804
 805         info->total_device_memory = rscreen->info.vram_size / 1024;
 806         info->total_staging_memory = rscreen->info.gart_size / 1024;
 807
 808         /* The real TTM memory usage is somewhat random, because:
 809          *
 810          * 1) TTM delays freeing memory, because it can only free it after
 811          *    fences expire.
 812          *
 813          * 2) The memory usage can be really low if big VRAM evictions are
 814          *    taking place, but the real usage is well above the size of VRAM.
 815          *
 816          * Instead, return statistics of this process.
 817          */
 818         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 819         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 820
 821         info->avail_device_memory =
 822                 vram_usage <= info->total_device_memory ?
 823                                 info->total_device_memory - vram_usage : 0;
 824         info->avail_staging_memory =
 825                 gtt_usage <= info->total_staging_memory ?
 826                                 info->total_staging_memory - gtt_usage : 0;
 827
 828         info->device_memory_evicted =
 829                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 830         /* Just return the number of evicted 64KB pages. */
 831         info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 832 }
 833
 834 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 835                                                   const struct pipe_resource *templ)
 836 {
 837         if (templ->target == PIPE_BUFFER) {
 838                 return r600_buffer_create(screen, templ, 4096);
 839         } else {
 840                 return r600_texture_create(screen, templ);
 841         }
 842 }
 843
 844 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 845                              struct radeon_winsys *ws)
 846 {
 847         char llvm_string[32] = {};
 848
 849         ws->query_info(ws, &rscreen->info);
 850
 851 #if HAVE_LLVM
 852         snprintf(llvm_string, sizeof(llvm_string),
 853                  ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 854                  HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 855 #endif
 856
 857         snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
 858                  "%s (DRM %i.%i.%i%s)",
 859                  r600_get_chip_name(rscreen), rscreen->info.drm_major,
 860                  rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
 861                  llvm_string);
 862
 863         rscreen->b.get_name = r600_get_name;
 864         rscreen->b.get_vendor = r600_get_vendor;
 865         rscreen->b.get_device_vendor = r600_get_device_vendor;
 866         rscreen->b.get_compute_param = r600_get_compute_param;
 867         rscreen->b.get_paramf = r600_get_paramf;
 868         rscreen->b.get_timestamp = r600_get_timestamp;
 869         rscreen->b.fence_finish = r600_fence_finish;
 870         rscreen->b.fence_reference = r600_fence_reference;
 871         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 872         rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
 873         rscreen->b.query_memory_info = r600_query_memory_info;
 874
 875         if (rscreen->info.has_uvd) {
 876                 rscreen->b.get_video_param = rvid_get_video_param;
 877                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 878         } else {
 879                 rscreen->b.get_video_param = r600_get_video_param;
 880                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 881         }
 882
 883         r600_init_screen_texture_functions(rscreen);
 884         r600_init_screen_query_functions(rscreen);
 885
 886         rscreen->ws = ws;
 887         rscreen->family = rscreen->info.family;
 888         rscreen->chip_class = rscreen->info.chip_class;
 889         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 890
 891         util_format_s3tc_init();
 892         pipe_mutex_init(rscreen->aux_context_lock);
 893         pipe_mutex_init(rscreen->gpu_load_mutex);
 894
 895         if (rscreen->debug_flags & DBG_INFO) {
 896                 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
 897                 printf("family = %i (%s)\n", rscreen->info.family,
 898                        r600_get_chip_name(rscreen));
 899                 printf("chip_class = %i\n", rscreen->info.chip_class);
 900                 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
 901                 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
 902                 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
 903                 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
 904                 printf("has_sdma = %i\n", rscreen->info.has_sdma);
 905                 printf("has_uvd = %i\n", rscreen->info.has_uvd);
 906                 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
 907                 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
 908                 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
 909                 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
 910                        rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
 911                 printf("has_userptr = %i\n", rscreen->info.has_userptr);
 912
 913                 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
 914                 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
 915                 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
 916                 printf("max_se = %i\n", rscreen->info.max_se);
 917                 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
 918
 919                 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
 920                 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
 921                 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
 922                 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
 923                 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
 924                 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
 925                 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
 926                 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
 927         }
 928         return true;
 929 }
 930
 931 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 932 {
 933         r600_perfcounters_destroy(rscreen);
 934         r600_gpu_load_kill_thread(rscreen);
 935
 936         pipe_mutex_destroy(rscreen->gpu_load_mutex);
 937         pipe_mutex_destroy(rscreen->aux_context_lock);
 938         rscreen->aux_context->destroy(rscreen->aux_context);
 939
 940         rscreen->ws->destroy(rscreen->ws);
 941         FREE(rscreen);
 942 }
 943
 944 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 945                           unsigned processor)
 946 {
 947         switch (processor) {
 948         case TGSI_PROCESSOR_VERTEX:
 949                 return (rscreen->debug_flags & DBG_VS) != 0;
 950         case TGSI_PROCESSOR_TESS_CTRL:
 951                 return (rscreen->debug_flags & DBG_TCS) != 0;
 952         case TGSI_PROCESSOR_TESS_EVAL:
 953                 return (rscreen->debug_flags & DBG_TES) != 0;
 954         case TGSI_PROCESSOR_GEOMETRY:
 955                 return (rscreen->debug_flags & DBG_GS) != 0;
 956         case TGSI_PROCESSOR_FRAGMENT:
 957                 return (rscreen->debug_flags & DBG_PS) != 0;
 958         case TGSI_PROCESSOR_COMPUTE:
 959                 return (rscreen->debug_flags & DBG_CS) != 0;
 960         default:
 961                 return false;
 962         }
 963 }
 964
 965 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 966                               uint64_t offset, uint64_t size, unsigned value,
 967                               bool is_framebuffer)
 968 {
 969         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 970
 971         pipe_mutex_lock(rscreen->aux_context_lock);
 972         rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
 973         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 974         pipe_mutex_unlock(rscreen->aux_context_lock);
 975 }