src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_draw_quad.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_upload_mgr.h"
  34 #include "vl/vl_decoder.h"
  35 #include "vl/vl_video_buffer.h"
  36 #include "radeon/radeon_video.h"
  37 #include <inttypes.h>
  38
  39 #ifndef HAVE_LLVM
  40 #define HAVE_LLVM 0
  41 #endif
  42
  43 /*
  44  * pipe_context
  45  */
  46
  47 void r600_draw_rectangle(struct blitter_context *blitter,
  48                          int x1, int y1, int x2, int y2, float depth,
  49                          enum blitter_attrib_type type,
  50                          const union pipe_color_union *attrib)
  51 {
  52         struct r600_common_context *rctx =
  53                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  54         struct pipe_viewport_state viewport;
  55         struct pipe_resource *buf = NULL;
  56         unsigned offset = 0;
  57         float *vb;
  58
  59         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  60                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  61                 return;
  62         }
  63
  64         /* Some operations (like color resolve on r6xx) don't work
  65          * with the conventional primitive types.
  66          * One that works is PT_RECTLIST, which we use here. */
  67
  68         /* setup viewport */
  69         viewport.scale[0] = 1.0f;
  70         viewport.scale[1] = 1.0f;
  71         viewport.scale[2] = 1.0f;
  72         viewport.translate[0] = 0.0f;
  73         viewport.translate[1] = 0.0f;
  74         viewport.translate[2] = 0.0f;
  75         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
  76
  77         /* Upload vertices. The hw rectangle has only 3 vertices,
  78          * I guess the 4th one is derived from the first 3.
  79          * The vertex specification should match u_blitter's vertex element state. */
  80         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
  81         vb[0] = x1;
  82         vb[1] = y1;
  83         vb[2] = depth;
  84         vb[3] = 1;
  85
  86         vb[8] = x1;
  87         vb[9] = y2;
  88         vb[10] = depth;
  89         vb[11] = 1;
  90
  91         vb[16] = x2;
  92         vb[17] = y1;
  93         vb[18] = depth;
  94         vb[19] = 1;
  95
  96         if (attrib) {
  97                 memcpy(vb+4, attrib->f, sizeof(float)*4);
  98                 memcpy(vb+12, attrib->f, sizeof(float)*4);
  99                 memcpy(vb+20, attrib->f, sizeof(float)*4);
 100         }
 101
 102         /* draw */
 103         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 104                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 105         pipe_resource_reference(&buf, NULL);
 106 }
 107
 108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
 109 {
 110         /* The number of dwords we already used in the DMA so far. */
 111         num_dw += ctx->rings.dma.cs->cdw;
 112         /* Flush if there's not enough space. */
 113         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
 114                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 115         }
 116 }
 117
 118 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 119 {
 120 }
 121
 122 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 123 {
 124         /* Disable render condition. */
 125         ctx->saved_render_cond = NULL;
 126         ctx->saved_render_cond_cond = FALSE;
 127         ctx->saved_render_cond_mode = 0;
 128         if (ctx->current_render_cond) {
 129                 ctx->saved_render_cond = ctx->current_render_cond;
 130                 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
 131                 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
 132                 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
 133         }
 134
 135         /* suspend queries */
 136         ctx->nontimer_queries_suspended = false;
 137         if (ctx->num_cs_dw_nontimer_queries_suspend) {
 138                 r600_suspend_nontimer_queries(ctx);
 139                 ctx->nontimer_queries_suspended = true;
 140         }
 141
 142         ctx->streamout.suspended = false;
 143         if (ctx->streamout.begin_emitted) {
 144                 r600_emit_streamout_end(ctx);
 145                 ctx->streamout.suspended = true;
 146         }
 147 }
 148
 149 void r600_postflush_resume_features(struct r600_common_context *ctx)
 150 {
 151         if (ctx->streamout.suspended) {
 152                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 153                 r600_streamout_buffers_dirty(ctx);
 154         }
 155
 156         /* resume queries */
 157         if (ctx->nontimer_queries_suspended) {
 158                 r600_resume_nontimer_queries(ctx);
 159         }
 160
 161         /* Re-enable render condition. */
 162         if (ctx->saved_render_cond) {
 163                 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
 164                                           ctx->saved_render_cond_cond,
 165                                           ctx->saved_render_cond_mode);
 166         }
 167 }
 168
 169 static void r600_flush_from_st(struct pipe_context *ctx,
 170                                struct pipe_fence_handle **fence,
 171                                unsigned flags)
 172 {
 173         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 174         unsigned rflags = 0;
 175
 176         if (flags & PIPE_FLUSH_END_OF_FRAME)
 177                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 178
 179         if (rctx->rings.dma.cs) {
 180                 rctx->rings.dma.flush(rctx, rflags, NULL);
 181         }
 182         rctx->rings.gfx.flush(rctx, rflags, fence);
 183 }
 184
 185 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 186                                 struct pipe_fence_handle **fence)
 187 {
 188         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 189         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 190
 191         if (!cs->cdw) {
 192                 return;
 193         }
 194
 195         rctx->rings.dma.flushing = true;
 196         rctx->ws->cs_flush(cs, flags, fence, 0);
 197         rctx->rings.dma.flushing = false;
 198 }
 199
 200 bool r600_common_context_init(struct r600_common_context *rctx,
 201                               struct r600_common_screen *rscreen)
 202 {
 203         util_slab_create(&rctx->pool_transfers,
 204                          sizeof(struct r600_transfer), 64,
 205                          UTIL_SLAB_SINGLETHREADED);
 206
 207         rctx->screen = rscreen;
 208         rctx->ws = rscreen->ws;
 209         rctx->family = rscreen->family;
 210         rctx->chip_class = rscreen->chip_class;
 211
 212         if (rscreen->family == CHIP_HAWAII)
 213                 rctx->max_db = 16;
 214         else if (rscreen->chip_class >= EVERGREEN)
 215                 rctx->max_db = 8;
 216         else
 217                 rctx->max_db = 4;
 218
 219         rctx->b.transfer_map = u_transfer_map_vtbl;
 220         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
 221         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 222         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 223         rctx->b.memory_barrier = r600_memory_barrier;
 224         rctx->b.flush = r600_flush_from_st;
 225
 226         LIST_INITHEAD(&rctx->texture_buffers);
 227
 228         r600_init_context_texture_functions(rctx);
 229         r600_streamout_init(rctx);
 230         r600_query_init(rctx);
 231         cayman_init_msaa(&rctx->b);
 232
 233         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 234                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 235         if (!rctx->allocator_so_filled_size)
 236                 return false;
 237
 238         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 239                                         PIPE_BIND_INDEX_BUFFER |
 240                                         PIPE_BIND_CONSTANT_BUFFER);
 241         if (!rctx->uploader)
 242                 return false;
 243
 244         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 245                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 246                                                          r600_flush_dma_ring,
 247                                                          rctx, NULL);
 248                 rctx->rings.dma.flush = r600_flush_dma_ring;
 249         }
 250
 251         return true;
 252 }
 253
 254 void r600_common_context_cleanup(struct r600_common_context *rctx)
 255 {
 256         if (rctx->rings.gfx.cs) {
 257                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 258         }
 259         if (rctx->rings.dma.cs) {
 260                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 261         }
 262
 263         if (rctx->uploader) {
 264                 u_upload_destroy(rctx->uploader);
 265         }
 266
 267         util_slab_destroy(&rctx->pool_transfers);
 268
 269         if (rctx->allocator_so_filled_size) {
 270                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 271         }
 272 }
 273
 274 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 275 {
 276         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 277         struct r600_resource *rr = (struct r600_resource *)r;
 278
 279         if (r == NULL) {
 280                 return;
 281         }
 282
 283         /*
 284          * The idea is to compute a gross estimate of memory requirement of
 285          * each draw call. After each draw call, memory will be precisely
 286          * accounted. So the uncertainty is only on the current draw call.
 287          * In practice this gave very good estimate (+/- 10% of the target
 288          * memory limit).
 289          */
 290         if (rr->domains & RADEON_DOMAIN_GTT) {
 291                 rctx->gtt += rr->buf->size;
 292         }
 293         if (rr->domains & RADEON_DOMAIN_VRAM) {
 294                 rctx->vram += rr->buf->size;
 295         }
 296 }
 297
 298 /*
 299  * pipe_screen
 300  */
 301
 302 static const struct debug_named_value common_debug_options[] = {
 303         /* logging */
 304         { "tex", DBG_TEX, "Print texture info" },
 305         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 306         { "compute", DBG_COMPUTE, "Print compute info" },
 307         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 308         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 309
 310         /* shaders */
 311         { "fs", DBG_FS, "Print fetch shaders" },
 312         { "vs", DBG_VS, "Print vertex shaders" },
 313         { "gs", DBG_GS, "Print geometry shaders" },
 314         { "ps", DBG_PS, "Print pixel shaders" },
 315         { "cs", DBG_CS, "Print compute shaders" },
 316
 317         /* features */
 318         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 319         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 320         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 321         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 322         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 323         { "notiling", DBG_NO_TILING, "Disable tiling" },
 324         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 325         { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 326
 327         DEBUG_NAMED_VALUE_END /* must be last */
 328 };
 329
 330 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 331 {
 332         return "X.Org";
 333 }
 334
 335 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
 336 {
 337         return "AMD";
 338 }
 339
 340 static const char* r600_get_name(struct pipe_screen* pscreen)
 341 {
 342         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 343
 344         switch (rscreen->family) {
 345         case CHIP_R600: return "AMD R600";
 346         case CHIP_RV610: return "AMD RV610";
 347         case CHIP_RV630: return "AMD RV630";
 348         case CHIP_RV670: return "AMD RV670";
 349         case CHIP_RV620: return "AMD RV620";
 350         case CHIP_RV635: return "AMD RV635";
 351         case CHIP_RS780: return "AMD RS780";
 352         case CHIP_RS880: return "AMD RS880";
 353         case CHIP_RV770: return "AMD RV770";
 354         case CHIP_RV730: return "AMD RV730";
 355         case CHIP_RV710: return "AMD RV710";
 356         case CHIP_RV740: return "AMD RV740";
 357         case CHIP_CEDAR: return "AMD CEDAR";
 358         case CHIP_REDWOOD: return "AMD REDWOOD";
 359         case CHIP_JUNIPER: return "AMD JUNIPER";
 360         case CHIP_CYPRESS: return "AMD CYPRESS";
 361         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 362         case CHIP_PALM: return "AMD PALM";
 363         case CHIP_SUMO: return "AMD SUMO";
 364         case CHIP_SUMO2: return "AMD SUMO2";
 365         case CHIP_BARTS: return "AMD BARTS";
 366         case CHIP_TURKS: return "AMD TURKS";
 367         case CHIP_CAICOS: return "AMD CAICOS";
 368         case CHIP_CAYMAN: return "AMD CAYMAN";
 369         case CHIP_ARUBA: return "AMD ARUBA";
 370         case CHIP_TAHITI: return "AMD TAHITI";
 371         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 372         case CHIP_VERDE: return "AMD CAPE VERDE";
 373         case CHIP_OLAND: return "AMD OLAND";
 374         case CHIP_HAINAN: return "AMD HAINAN";
 375         case CHIP_BONAIRE: return "AMD BONAIRE";
 376         case CHIP_KAVERI: return "AMD KAVERI";
 377         case CHIP_KABINI: return "AMD KABINI";
 378         case CHIP_HAWAII: return "AMD HAWAII";
 379         case CHIP_MULLINS: return "AMD MULLINS";
 380         default: return "AMD unknown";
 381         }
 382 }
 383
 384 static float r600_get_paramf(struct pipe_screen* pscreen,
 385                              enum pipe_capf param)
 386 {
 387         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 388
 389         switch (param) {
 390         case PIPE_CAPF_MAX_LINE_WIDTH:
 391         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 392         case PIPE_CAPF_MAX_POINT_WIDTH:
 393         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 394                 if (rscreen->family >= CHIP_CEDAR)
 395                         return 16384.0f;
 396                 else
 397                         return 8192.0f;
 398         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 399                 return 16.0f;
 400         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 401                 return 16.0f;
 402         case PIPE_CAPF_GUARD_BAND_LEFT:
 403         case PIPE_CAPF_GUARD_BAND_TOP:
 404         case PIPE_CAPF_GUARD_BAND_RIGHT:
 405         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 406                 return 0.0f;
 407         }
 408         return 0.0f;
 409 }
 410
 411 static int r600_get_video_param(struct pipe_screen *screen,
 412                                 enum pipe_video_profile profile,
 413                                 enum pipe_video_entrypoint entrypoint,
 414                                 enum pipe_video_cap param)
 415 {
 416         switch (param) {
 417         case PIPE_VIDEO_CAP_SUPPORTED:
 418                 return vl_profile_supported(screen, profile, entrypoint);
 419         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 420                 return 1;
 421         case PIPE_VIDEO_CAP_MAX_WIDTH:
 422         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 423                 return vl_video_buffer_max_size(screen);
 424         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 425                 return PIPE_FORMAT_NV12;
 426         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 427                 return false;
 428         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 429                 return false;
 430         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 431                 return true;
 432         case PIPE_VIDEO_CAP_MAX_LEVEL:
 433                 return vl_level_supported(screen, profile);
 434         default:
 435                 return 0;
 436         }
 437 }
 438
 439 const char *r600_get_llvm_processor_name(enum radeon_family family)
 440 {
 441         switch (family) {
 442         case CHIP_R600:
 443         case CHIP_RV630:
 444         case CHIP_RV635:
 445         case CHIP_RV670:
 446                 return "r600";
 447         case CHIP_RV610:
 448         case CHIP_RV620:
 449         case CHIP_RS780:
 450         case CHIP_RS880:
 451                 return "rs880";
 452         case CHIP_RV710:
 453                 return "rv710";
 454         case CHIP_RV730:
 455                 return "rv730";
 456         case CHIP_RV740:
 457         case CHIP_RV770:
 458                 return "rv770";
 459         case CHIP_PALM:
 460         case CHIP_CEDAR:
 461                 return "cedar";
 462         case CHIP_SUMO:
 463         case CHIP_SUMO2:
 464                 return "sumo";
 465         case CHIP_REDWOOD:
 466                 return "redwood";
 467         case CHIP_JUNIPER:
 468                 return "juniper";
 469         case CHIP_HEMLOCK:
 470         case CHIP_CYPRESS:
 471                 return "cypress";
 472         case CHIP_BARTS:
 473                 return "barts";
 474         case CHIP_TURKS:
 475                 return "turks";
 476         case CHIP_CAICOS:
 477                 return "caicos";
 478         case CHIP_CAYMAN:
 479         case CHIP_ARUBA:
 480                 return "cayman";
 481
 482         case CHIP_TAHITI: return "tahiti";
 483         case CHIP_PITCAIRN: return "pitcairn";
 484         case CHIP_VERDE: return "verde";
 485         case CHIP_OLAND: return "oland";
 486         case CHIP_HAINAN: return "hainan";
 487         case CHIP_BONAIRE: return "bonaire";
 488         case CHIP_KABINI: return "kabini";
 489         case CHIP_KAVERI: return "kaveri";
 490         case CHIP_HAWAII: return "hawaii";
 491         case CHIP_MULLINS:
 492 #if HAVE_LLVM >= 0x0305
 493                 return "mullins";
 494 #else
 495                 return "kabini";
 496 #endif
 497         default: return "";
 498         }
 499 }
 500
 501 static int r600_get_compute_param(struct pipe_screen *screen,
 502         enum pipe_compute_cap param,
 503         void *ret)
 504 {
 505         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 506
 507         //TODO: select these params by asic
 508         switch (param) {
 509         case PIPE_COMPUTE_CAP_IR_TARGET: {
 510                 const char *gpu;
 511                 const char *triple;
 512                 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
 513                         triple = "r600--";
 514                 } else {
 515                         triple = "amdgcn--";
 516                 }
 517                 switch(rscreen->family) {
 518                 /* Clang < 3.6 is missing Hainan in its list of
 519                  * GPUs, so we need to use the name of a similar GPU.
 520                  */
 521 #if HAVE_LLVM < 0x0306
 522                 case CHIP_HAINAN:
 523                         gpu = "oland";
 524                         break;
 525 #endif
 526                 default:
 527                         gpu = r600_get_llvm_processor_name(rscreen->family);
 528                         break;
 529                 }
 530                 if (ret) {
 531                         sprintf(ret, "%s-%s", gpu, triple);
 532                 }
 533                 /* +2 for dash and terminating NIL byte */
 534                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 535         }
 536         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 537                 if (ret) {
 538                         uint64_t *grid_dimension = ret;
 539                         grid_dimension[0] = 3;
 540                 }
 541                 return 1 * sizeof(uint64_t);
 542
 543         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 544                 if (ret) {
 545                         uint64_t *grid_size = ret;
 546                         grid_size[0] = 65535;
 547                         grid_size[1] = 65535;
 548                         grid_size[2] = 1;
 549                 }
 550                 return 3 * sizeof(uint64_t) ;
 551
 552         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 553                 if (ret) {
 554                         uint64_t *block_size = ret;
 555                         block_size[0] = 256;
 556                         block_size[1] = 256;
 557                         block_size[2] = 256;
 558                 }
 559                 return 3 * sizeof(uint64_t);
 560
 561         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 562                 if (ret) {
 563                         uint64_t *max_threads_per_block = ret;
 564                         *max_threads_per_block = 256;
 565                 }
 566                 return sizeof(uint64_t);
 567
 568         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 569                 if (ret) {
 570                         uint64_t *max_global_size = ret;
 571                         uint64_t max_mem_alloc_size;
 572
 573                         r600_get_compute_param(screen,
 574                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 575                                 &max_mem_alloc_size);
 576
 577                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 578                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 579                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 580                          * make sure we never report more than
 581                          * 4 * MAX_MEM_ALLOC_SIZE.
 582                          */
 583                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 584                                 rscreen->info.gart_size +
 585                                 rscreen->info.vram_size);
 586                 }
 587                 return sizeof(uint64_t);
 588
 589         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 590                 if (ret) {
 591                         uint64_t *max_local_size = ret;
 592                         /* Value reported by the closed source driver. */
 593                         *max_local_size = 32768;
 594                 }
 595                 return sizeof(uint64_t);
 596
 597         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 598                 if (ret) {
 599                         uint64_t *max_input_size = ret;
 600                         /* Value reported by the closed source driver. */
 601                         *max_input_size = 1024;
 602                 }
 603                 return sizeof(uint64_t);
 604
 605         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 606                 if (ret) {
 607                         uint64_t *max_mem_alloc_size = ret;
 608
 609                         /* XXX: The limit in older kernels is 256 MB.  We
 610                          * should add a query here for newer kernels.
 611                          */
 612                         *max_mem_alloc_size = 256 * 1024 * 1024;
 613                 }
 614                 return sizeof(uint64_t);
 615
 616         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 617                 if (ret) {
 618                         uint32_t *max_clock_frequency = ret;
 619                         *max_clock_frequency = rscreen->info.max_sclk;
 620                 }
 621                 return sizeof(uint32_t);
 622
 623         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 624                 if (ret) {
 625                         uint32_t *max_compute_units = ret;
 626                         *max_compute_units = rscreen->info.max_compute_units;
 627                 }
 628                 return sizeof(uint32_t);
 629
 630         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 631                 if (ret) {
 632                         uint32_t *images_supported = ret;
 633                         *images_supported = 0;
 634                 }
 635                 return sizeof(uint32_t);
 636         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 637                 break; /* unused */
 638         }
 639
 640         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 641         return 0;
 642 }
 643
 644 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 645 {
 646         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 647
 648         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 649                         rscreen->info.r600_clock_crystal_freq;
 650 }
 651
 652 static int r600_get_driver_query_info(struct pipe_screen *screen,
 653                                       unsigned index,
 654                                       struct pipe_driver_query_info *info)
 655 {
 656         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 657         struct pipe_driver_query_info list[] = {
 658                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 659                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 660                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 661                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 662                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 663                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 664                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 665                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 666         };
 667
 668         if (!info)
 669                 return Elements(list);
 670
 671         if (index >= Elements(list))
 672                 return 0;
 673
 674         *info = list[index];
 675         return 1;
 676 }
 677
 678 static void r600_fence_reference(struct pipe_screen *screen,
 679                                  struct pipe_fence_handle **ptr,
 680                                  struct pipe_fence_handle *fence)
 681 {
 682         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 683
 684         rws->fence_reference(ptr, fence);
 685 }
 686
 687 static boolean r600_fence_signalled(struct pipe_screen *screen,
 688                                     struct pipe_fence_handle *fence)
 689 {
 690         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 691
 692         return rws->fence_wait(rws, fence, 0);
 693 }
 694
 695 static boolean r600_fence_finish(struct pipe_screen *screen,
 696                                  struct pipe_fence_handle *fence,
 697                                  uint64_t timeout)
 698 {
 699         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 700
 701         return rws->fence_wait(rws, fence, timeout);
 702 }
 703
 704 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 705                                   uint32_t tiling_config)
 706 {
 707         switch ((tiling_config & 0xe) >> 1) {
 708         case 0:
 709                 rscreen->tiling_info.num_channels = 1;
 710                 break;
 711         case 1:
 712                 rscreen->tiling_info.num_channels = 2;
 713                 break;
 714         case 2:
 715                 rscreen->tiling_info.num_channels = 4;
 716                 break;
 717         case 3:
 718                 rscreen->tiling_info.num_channels = 8;
 719                 break;
 720         default:
 721                 return false;
 722         }
 723
 724         switch ((tiling_config & 0x30) >> 4) {
 725         case 0:
 726                 rscreen->tiling_info.num_banks = 4;
 727                 break;
 728         case 1:
 729                 rscreen->tiling_info.num_banks = 8;
 730                 break;
 731         default:
 732                 return false;
 733
 734         }
 735         switch ((tiling_config & 0xc0) >> 6) {
 736         case 0:
 737                 rscreen->tiling_info.group_bytes = 256;
 738                 break;
 739         case 1:
 740                 rscreen->tiling_info.group_bytes = 512;
 741                 break;
 742         default:
 743                 return false;
 744         }
 745         return true;
 746 }
 747
 748 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 749                                        uint32_t tiling_config)
 750 {
 751         switch (tiling_config & 0xf) {
 752         case 0:
 753                 rscreen->tiling_info.num_channels = 1;
 754                 break;
 755         case 1:
 756                 rscreen->tiling_info.num_channels = 2;
 757                 break;
 758         case 2:
 759                 rscreen->tiling_info.num_channels = 4;
 760                 break;
 761         case 3:
 762                 rscreen->tiling_info.num_channels = 8;
 763                 break;
 764         default:
 765                 return false;
 766         }
 767
 768         switch ((tiling_config & 0xf0) >> 4) {
 769         case 0:
 770                 rscreen->tiling_info.num_banks = 4;
 771                 break;
 772         case 1:
 773                 rscreen->tiling_info.num_banks = 8;
 774                 break;
 775         case 2:
 776                 rscreen->tiling_info.num_banks = 16;
 777                 break;
 778         default:
 779                 return false;
 780         }
 781
 782         switch ((tiling_config & 0xf00) >> 8) {
 783         case 0:
 784                 rscreen->tiling_info.group_bytes = 256;
 785                 break;
 786         case 1:
 787                 rscreen->tiling_info.group_bytes = 512;
 788                 break;
 789         default:
 790                 return false;
 791         }
 792         return true;
 793 }
 794
 795 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 796 {
 797         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 798
 799         /* set default group bytes, overridden by tiling info ioctl */
 800         if (rscreen->chip_class <= R700) {
 801                 rscreen->tiling_info.group_bytes = 256;
 802         } else {
 803                 rscreen->tiling_info.group_bytes = 512;
 804         }
 805
 806         if (!tiling_config)
 807                 return true;
 808
 809         if (rscreen->chip_class <= R700) {
 810                 return r600_interpret_tiling(rscreen, tiling_config);
 811         } else {
 812                 return evergreen_interpret_tiling(rscreen, tiling_config);
 813         }
 814 }
 815
 816 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 817                                                   const struct pipe_resource *templ)
 818 {
 819         if (templ->target == PIPE_BUFFER) {
 820                 return r600_buffer_create(screen, templ, 4096);
 821         } else {
 822                 return r600_texture_create(screen, templ);
 823         }
 824 }
 825
 826 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 827                              struct radeon_winsys *ws)
 828 {
 829         ws->query_info(ws, &rscreen->info);
 830
 831         rscreen->b.get_name = r600_get_name;
 832         rscreen->b.get_vendor = r600_get_vendor;
 833         rscreen->b.get_device_vendor = r600_get_device_vendor;
 834         rscreen->b.get_compute_param = r600_get_compute_param;
 835         rscreen->b.get_paramf = r600_get_paramf;
 836         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 837         rscreen->b.get_timestamp = r600_get_timestamp;
 838         rscreen->b.fence_finish = r600_fence_finish;
 839         rscreen->b.fence_reference = r600_fence_reference;
 840         rscreen->b.fence_signalled = r600_fence_signalled;
 841         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 842         rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
 843
 844         if (rscreen->info.has_uvd) {
 845                 rscreen->b.get_video_param = rvid_get_video_param;
 846                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 847         } else {
 848                 rscreen->b.get_video_param = r600_get_video_param;
 849                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 850         }
 851
 852         r600_init_screen_texture_functions(rscreen);
 853
 854         rscreen->ws = ws;
 855         rscreen->family = rscreen->info.family;
 856         rscreen->chip_class = rscreen->info.chip_class;
 857         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 858
 859         if (!r600_init_tiling(rscreen)) {
 860                 return false;
 861         }
 862         util_format_s3tc_init();
 863         pipe_mutex_init(rscreen->aux_context_lock);
 864
 865         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 866                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 867                                                                                 PIPE_BIND_CUSTOM,
 868                                                                                 PIPE_USAGE_STAGING,
 869                                                                                 4096);
 870                 if (rscreen->trace_bo) {
 871                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 872                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 873                 }
 874         }
 875
 876         return true;
 877 }
 878
 879 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 880 {
 881         pipe_mutex_destroy(rscreen->aux_context_lock);
 882         rscreen->aux_context->destroy(rscreen->aux_context);
 883
 884         if (rscreen->trace_bo) {
 885                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 886                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 887         }
 888
 889         rscreen->ws->destroy(rscreen->ws);
 890         FREE(rscreen);
 891 }
 892
 893 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 894                           const struct tgsi_token *tokens)
 895 {
 896         /* Compute shader don't have tgsi_tokens */
 897         if (!tokens)
 898                 return (rscreen->debug_flags & DBG_CS) != 0;
 899
 900         switch (tgsi_get_processor_type(tokens)) {
 901         case TGSI_PROCESSOR_VERTEX:
 902                 return (rscreen->debug_flags & DBG_VS) != 0;
 903         case TGSI_PROCESSOR_GEOMETRY:
 904                 return (rscreen->debug_flags & DBG_GS) != 0;
 905         case TGSI_PROCESSOR_FRAGMENT:
 906                 return (rscreen->debug_flags & DBG_PS) != 0;
 907         case TGSI_PROCESSOR_COMPUTE:
 908                 return (rscreen->debug_flags & DBG_CS) != 0;
 909         default:
 910                 return false;
 911         }
 912 }
 913
 914 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 915                               unsigned offset, unsigned size, unsigned value,
 916                               bool is_framebuffer)
 917 {
 918         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 919
 920         pipe_mutex_lock(rscreen->aux_context_lock);
 921         rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
 922         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 923         pipe_mutex_unlock(rscreen->aux_context_lock);
 924 }