radeon/compute: Fix reported values for MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_upload_mgr.h"
33 #include "vl/vl_decoder.h"
34 #include "vl/vl_video_buffer.h"
35 #include "radeon/radeon_video.h"
36 #include <inttypes.h>
37
38 /*
39 * pipe_context
40 */
41
42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
43 {
44 /* The number of dwords we already used in the DMA so far. */
45 num_dw += ctx->rings.dma.cs->cdw;
46 /* Flush if there's not enough space. */
47 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
48 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
49 }
50 }
51
52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
53 {
54 }
55
56 void r600_preflush_suspend_features(struct r600_common_context *ctx)
57 {
58 /* Disable render condition. */
59 ctx->saved_render_cond = NULL;
60 ctx->saved_render_cond_cond = FALSE;
61 ctx->saved_render_cond_mode = 0;
62 if (ctx->current_render_cond) {
63 ctx->saved_render_cond = ctx->current_render_cond;
64 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
65 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
66 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
67 }
68
69 /* suspend queries */
70 ctx->nontimer_queries_suspended = false;
71 if (ctx->num_cs_dw_nontimer_queries_suspend) {
72 r600_suspend_nontimer_queries(ctx);
73 ctx->nontimer_queries_suspended = true;
74 }
75
76 ctx->streamout.suspended = false;
77 if (ctx->streamout.begin_emitted) {
78 r600_emit_streamout_end(ctx);
79 ctx->streamout.suspended = true;
80 }
81 }
82
83 void r600_postflush_resume_features(struct r600_common_context *ctx)
84 {
85 if (ctx->streamout.suspended) {
86 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
87 r600_streamout_buffers_dirty(ctx);
88 }
89
90 /* resume queries */
91 if (ctx->nontimer_queries_suspended) {
92 r600_resume_nontimer_queries(ctx);
93 }
94
95 /* Re-enable render condition. */
96 if (ctx->saved_render_cond) {
97 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
98 ctx->saved_render_cond_cond,
99 ctx->saved_render_cond_mode);
100 }
101 }
102
103 static void r600_flush_from_st(struct pipe_context *ctx,
104 struct pipe_fence_handle **fence,
105 unsigned flags)
106 {
107 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
108 unsigned rflags = 0;
109
110 if (flags & PIPE_FLUSH_END_OF_FRAME)
111 rflags |= RADEON_FLUSH_END_OF_FRAME;
112
113 if (rctx->rings.dma.cs) {
114 rctx->rings.dma.flush(rctx, rflags, NULL);
115 }
116 rctx->rings.gfx.flush(rctx, rflags, fence);
117 }
118
119 static void r600_flush_dma_ring(void *ctx, unsigned flags,
120 struct pipe_fence_handle **fence)
121 {
122 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
123 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
124
125 if (!cs->cdw) {
126 return;
127 }
128
129 rctx->rings.dma.flushing = true;
130 rctx->ws->cs_flush(cs, flags, fence, 0);
131 rctx->rings.dma.flushing = false;
132 }
133
134 bool r600_common_context_init(struct r600_common_context *rctx,
135 struct r600_common_screen *rscreen)
136 {
137 util_slab_create(&rctx->pool_transfers,
138 sizeof(struct r600_transfer), 64,
139 UTIL_SLAB_SINGLETHREADED);
140
141 rctx->screen = rscreen;
142 rctx->ws = rscreen->ws;
143 rctx->family = rscreen->family;
144 rctx->chip_class = rscreen->chip_class;
145
146 if (rscreen->family == CHIP_HAWAII)
147 rctx->max_db = 16;
148 else if (rscreen->chip_class >= EVERGREEN)
149 rctx->max_db = 8;
150 else
151 rctx->max_db = 4;
152
153 rctx->b.transfer_map = u_transfer_map_vtbl;
154 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
155 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
156 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
157 rctx->b.memory_barrier = r600_memory_barrier;
158 rctx->b.flush = r600_flush_from_st;
159
160 r600_init_context_texture_functions(rctx);
161 r600_streamout_init(rctx);
162 r600_query_init(rctx);
163 cayman_init_msaa(&rctx->b);
164
165 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
166 0, PIPE_USAGE_DEFAULT, TRUE);
167 if (!rctx->allocator_so_filled_size)
168 return false;
169
170 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
171 PIPE_BIND_INDEX_BUFFER |
172 PIPE_BIND_CONSTANT_BUFFER);
173 if (!rctx->uploader)
174 return false;
175
176 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
177 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
178 r600_flush_dma_ring,
179 rctx, NULL);
180 rctx->rings.dma.flush = r600_flush_dma_ring;
181 }
182
183 return true;
184 }
185
186 void r600_common_context_cleanup(struct r600_common_context *rctx)
187 {
188 if (rctx->rings.gfx.cs) {
189 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
190 }
191 if (rctx->rings.dma.cs) {
192 rctx->ws->cs_destroy(rctx->rings.dma.cs);
193 }
194
195 if (rctx->uploader) {
196 u_upload_destroy(rctx->uploader);
197 }
198
199 util_slab_destroy(&rctx->pool_transfers);
200
201 if (rctx->allocator_so_filled_size) {
202 u_suballocator_destroy(rctx->allocator_so_filled_size);
203 }
204 }
205
206 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
207 {
208 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
209 struct r600_resource *rr = (struct r600_resource *)r;
210
211 if (r == NULL) {
212 return;
213 }
214
215 /*
216 * The idea is to compute a gross estimate of memory requirement of
217 * each draw call. After each draw call, memory will be precisely
218 * accounted. So the uncertainty is only on the current draw call.
219 * In practice this gave very good estimate (+/- 10% of the target
220 * memory limit).
221 */
222 if (rr->domains & RADEON_DOMAIN_GTT) {
223 rctx->gtt += rr->buf->size;
224 }
225 if (rr->domains & RADEON_DOMAIN_VRAM) {
226 rctx->vram += rr->buf->size;
227 }
228 }
229
230 /*
231 * pipe_screen
232 */
233
234 static const struct debug_named_value common_debug_options[] = {
235 /* logging */
236 { "tex", DBG_TEX, "Print texture info" },
237 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
238 { "compute", DBG_COMPUTE, "Print compute info" },
239 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
240 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
241
242 /* shaders */
243 { "fs", DBG_FS, "Print fetch shaders" },
244 { "vs", DBG_VS, "Print vertex shaders" },
245 { "gs", DBG_GS, "Print geometry shaders" },
246 { "ps", DBG_PS, "Print pixel shaders" },
247 { "cs", DBG_CS, "Print compute shaders" },
248
249 /* features */
250 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
251 { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
252 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
253 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
254 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
255 { "notiling", DBG_NO_TILING, "Disable tiling" },
256 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
257
258 DEBUG_NAMED_VALUE_END /* must be last */
259 };
260
261 static const char* r600_get_vendor(struct pipe_screen* pscreen)
262 {
263 return "X.Org";
264 }
265
266 static const char* r600_get_name(struct pipe_screen* pscreen)
267 {
268 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
269
270 switch (rscreen->family) {
271 case CHIP_R600: return "AMD R600";
272 case CHIP_RV610: return "AMD RV610";
273 case CHIP_RV630: return "AMD RV630";
274 case CHIP_RV670: return "AMD RV670";
275 case CHIP_RV620: return "AMD RV620";
276 case CHIP_RV635: return "AMD RV635";
277 case CHIP_RS780: return "AMD RS780";
278 case CHIP_RS880: return "AMD RS880";
279 case CHIP_RV770: return "AMD RV770";
280 case CHIP_RV730: return "AMD RV730";
281 case CHIP_RV710: return "AMD RV710";
282 case CHIP_RV740: return "AMD RV740";
283 case CHIP_CEDAR: return "AMD CEDAR";
284 case CHIP_REDWOOD: return "AMD REDWOOD";
285 case CHIP_JUNIPER: return "AMD JUNIPER";
286 case CHIP_CYPRESS: return "AMD CYPRESS";
287 case CHIP_HEMLOCK: return "AMD HEMLOCK";
288 case CHIP_PALM: return "AMD PALM";
289 case CHIP_SUMO: return "AMD SUMO";
290 case CHIP_SUMO2: return "AMD SUMO2";
291 case CHIP_BARTS: return "AMD BARTS";
292 case CHIP_TURKS: return "AMD TURKS";
293 case CHIP_CAICOS: return "AMD CAICOS";
294 case CHIP_CAYMAN: return "AMD CAYMAN";
295 case CHIP_ARUBA: return "AMD ARUBA";
296 case CHIP_TAHITI: return "AMD TAHITI";
297 case CHIP_PITCAIRN: return "AMD PITCAIRN";
298 case CHIP_VERDE: return "AMD CAPE VERDE";
299 case CHIP_OLAND: return "AMD OLAND";
300 case CHIP_HAINAN: return "AMD HAINAN";
301 case CHIP_BONAIRE: return "AMD BONAIRE";
302 case CHIP_KAVERI: return "AMD KAVERI";
303 case CHIP_KABINI: return "AMD KABINI";
304 case CHIP_HAWAII: return "AMD HAWAII";
305 case CHIP_MULLINS: return "AMD MULLINS";
306 default: return "AMD unknown";
307 }
308 }
309
310 static float r600_get_paramf(struct pipe_screen* pscreen,
311 enum pipe_capf param)
312 {
313 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
314
315 switch (param) {
316 case PIPE_CAPF_MAX_LINE_WIDTH:
317 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
318 case PIPE_CAPF_MAX_POINT_WIDTH:
319 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
320 if (rscreen->family >= CHIP_CEDAR)
321 return 16384.0f;
322 else
323 return 8192.0f;
324 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
325 return 16.0f;
326 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
327 return 16.0f;
328 case PIPE_CAPF_GUARD_BAND_LEFT:
329 case PIPE_CAPF_GUARD_BAND_TOP:
330 case PIPE_CAPF_GUARD_BAND_RIGHT:
331 case PIPE_CAPF_GUARD_BAND_BOTTOM:
332 return 0.0f;
333 }
334 return 0.0f;
335 }
336
337 static int r600_get_video_param(struct pipe_screen *screen,
338 enum pipe_video_profile profile,
339 enum pipe_video_entrypoint entrypoint,
340 enum pipe_video_cap param)
341 {
342 switch (param) {
343 case PIPE_VIDEO_CAP_SUPPORTED:
344 return vl_profile_supported(screen, profile, entrypoint);
345 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
346 return 1;
347 case PIPE_VIDEO_CAP_MAX_WIDTH:
348 case PIPE_VIDEO_CAP_MAX_HEIGHT:
349 return vl_video_buffer_max_size(screen);
350 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
351 return PIPE_FORMAT_NV12;
352 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
353 return false;
354 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
355 return false;
356 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
357 return true;
358 case PIPE_VIDEO_CAP_MAX_LEVEL:
359 return vl_level_supported(screen, profile);
360 default:
361 return 0;
362 }
363 }
364
365 const char *r600_get_llvm_processor_name(enum radeon_family family)
366 {
367 switch (family) {
368 case CHIP_R600:
369 case CHIP_RV630:
370 case CHIP_RV635:
371 case CHIP_RV670:
372 return "r600";
373 case CHIP_RV610:
374 case CHIP_RV620:
375 case CHIP_RS780:
376 case CHIP_RS880:
377 return "rs880";
378 case CHIP_RV710:
379 return "rv710";
380 case CHIP_RV730:
381 return "rv730";
382 case CHIP_RV740:
383 case CHIP_RV770:
384 return "rv770";
385 case CHIP_PALM:
386 case CHIP_CEDAR:
387 return "cedar";
388 case CHIP_SUMO:
389 case CHIP_SUMO2:
390 return "sumo";
391 case CHIP_REDWOOD:
392 return "redwood";
393 case CHIP_JUNIPER:
394 return "juniper";
395 case CHIP_HEMLOCK:
396 case CHIP_CYPRESS:
397 return "cypress";
398 case CHIP_BARTS:
399 return "barts";
400 case CHIP_TURKS:
401 return "turks";
402 case CHIP_CAICOS:
403 return "caicos";
404 case CHIP_CAYMAN:
405 case CHIP_ARUBA:
406 return "cayman";
407
408 case CHIP_TAHITI: return "tahiti";
409 case CHIP_PITCAIRN: return "pitcairn";
410 case CHIP_VERDE: return "verde";
411 case CHIP_OLAND: return "oland";
412 case CHIP_HAINAN: return "hainan";
413 case CHIP_BONAIRE: return "bonaire";
414 case CHIP_KABINI: return "kabini";
415 case CHIP_KAVERI: return "kaveri";
416 case CHIP_HAWAII: return "hawaii";
417 case CHIP_MULLINS:
418 #if HAVE_LLVM >= 0x0305
419 return "mullins";
420 #else
421 return "kabini";
422 #endif
423 default: return "";
424 }
425 }
426
427 static int r600_get_compute_param(struct pipe_screen *screen,
428 enum pipe_compute_cap param,
429 void *ret)
430 {
431 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
432
433 //TODO: select these params by asic
434 switch (param) {
435 case PIPE_COMPUTE_CAP_IR_TARGET: {
436 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
437 if (ret) {
438 sprintf(ret, "%s-r600--", gpu);
439 }
440 return (8 + strlen(gpu)) * sizeof(char);
441 }
442 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
443 if (ret) {
444 uint64_t *grid_dimension = ret;
445 grid_dimension[0] = 3;
446 }
447 return 1 * sizeof(uint64_t);
448
449 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
450 if (ret) {
451 uint64_t *grid_size = ret;
452 grid_size[0] = 65535;
453 grid_size[1] = 65535;
454 grid_size[2] = 1;
455 }
456 return 3 * sizeof(uint64_t) ;
457
458 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
459 if (ret) {
460 uint64_t *block_size = ret;
461 block_size[0] = 256;
462 block_size[1] = 256;
463 block_size[2] = 256;
464 }
465 return 3 * sizeof(uint64_t);
466
467 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
468 if (ret) {
469 uint64_t *max_threads_per_block = ret;
470 *max_threads_per_block = 256;
471 }
472 return sizeof(uint64_t);
473
474 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
475 if (ret) {
476 uint64_t *max_global_size = ret;
477 uint64_t max_mem_alloc_size;
478
479 r600_get_compute_param(screen,
480 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
481 &max_mem_alloc_size);
482
483 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
484 * 1/4 of the MAX_GLOBAL_SIZE. Since the
485 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
486 * make sure we never report more than
487 * 4 * MAX_MEM_ALLOC_SIZE.
488 */
489 *max_global_size = MIN2(4 * max_mem_alloc_size,
490 rscreen->info.gart_size +
491 rscreen->info.vram_size);
492 }
493 return sizeof(uint64_t);
494
495 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
496 if (ret) {
497 uint64_t *max_local_size = ret;
498 /* Value reported by the closed source driver. */
499 *max_local_size = 32768;
500 }
501 return sizeof(uint64_t);
502
503 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
504 if (ret) {
505 uint64_t *max_input_size = ret;
506 /* Value reported by the closed source driver. */
507 *max_input_size = 1024;
508 }
509 return sizeof(uint64_t);
510
511 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
512 if (ret) {
513 uint64_t max_global_size;
514 uint64_t *max_mem_alloc_size = ret;
515
516 /* XXX: The limit in older kernels is 256 MB. We
517 * should add a query here for newer kernels.
518 */
519 *max_mem_alloc_size = 256 * 1024 * 1024;
520 }
521 return sizeof(uint64_t);
522
523 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
524 if (ret) {
525 uint32_t *max_clock_frequency = ret;
526 *max_clock_frequency = rscreen->info.max_sclk;
527 }
528 return sizeof(uint32_t);
529
530 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
531 if (ret) {
532 uint32_t *max_compute_units = ret;
533 *max_compute_units = MAX2(rscreen->info.max_compute_units, 1);
534 }
535 return sizeof(uint32_t);
536
537 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
538 if (ret) {
539 uint32_t *images_supported = ret;
540 *images_supported = 0;
541 }
542 return sizeof(uint32_t);
543 }
544
545 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
546 return 0;
547 }
548
549 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
550 {
551 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
552
553 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
554 rscreen->info.r600_clock_crystal_freq;
555 }
556
557 static int r600_get_driver_query_info(struct pipe_screen *screen,
558 unsigned index,
559 struct pipe_driver_query_info *info)
560 {
561 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
562 struct pipe_driver_query_info list[] = {
563 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
564 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
565 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
566 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
567 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
568 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
569 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
570 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
571 };
572
573 if (!info)
574 return Elements(list);
575
576 if (index >= Elements(list))
577 return 0;
578
579 *info = list[index];
580 return 1;
581 }
582
583 static void r600_fence_reference(struct pipe_screen *screen,
584 struct pipe_fence_handle **ptr,
585 struct pipe_fence_handle *fence)
586 {
587 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
588
589 rws->fence_reference(ptr, fence);
590 }
591
592 static boolean r600_fence_signalled(struct pipe_screen *screen,
593 struct pipe_fence_handle *fence)
594 {
595 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
596
597 return rws->fence_wait(rws, fence, 0);
598 }
599
600 static boolean r600_fence_finish(struct pipe_screen *screen,
601 struct pipe_fence_handle *fence,
602 uint64_t timeout)
603 {
604 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
605
606 return rws->fence_wait(rws, fence, timeout);
607 }
608
609 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
610 uint32_t tiling_config)
611 {
612 switch ((tiling_config & 0xe) >> 1) {
613 case 0:
614 rscreen->tiling_info.num_channels = 1;
615 break;
616 case 1:
617 rscreen->tiling_info.num_channels = 2;
618 break;
619 case 2:
620 rscreen->tiling_info.num_channels = 4;
621 break;
622 case 3:
623 rscreen->tiling_info.num_channels = 8;
624 break;
625 default:
626 return false;
627 }
628
629 switch ((tiling_config & 0x30) >> 4) {
630 case 0:
631 rscreen->tiling_info.num_banks = 4;
632 break;
633 case 1:
634 rscreen->tiling_info.num_banks = 8;
635 break;
636 default:
637 return false;
638
639 }
640 switch ((tiling_config & 0xc0) >> 6) {
641 case 0:
642 rscreen->tiling_info.group_bytes = 256;
643 break;
644 case 1:
645 rscreen->tiling_info.group_bytes = 512;
646 break;
647 default:
648 return false;
649 }
650 return true;
651 }
652
653 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
654 uint32_t tiling_config)
655 {
656 switch (tiling_config & 0xf) {
657 case 0:
658 rscreen->tiling_info.num_channels = 1;
659 break;
660 case 1:
661 rscreen->tiling_info.num_channels = 2;
662 break;
663 case 2:
664 rscreen->tiling_info.num_channels = 4;
665 break;
666 case 3:
667 rscreen->tiling_info.num_channels = 8;
668 break;
669 default:
670 return false;
671 }
672
673 switch ((tiling_config & 0xf0) >> 4) {
674 case 0:
675 rscreen->tiling_info.num_banks = 4;
676 break;
677 case 1:
678 rscreen->tiling_info.num_banks = 8;
679 break;
680 case 2:
681 rscreen->tiling_info.num_banks = 16;
682 break;
683 default:
684 return false;
685 }
686
687 switch ((tiling_config & 0xf00) >> 8) {
688 case 0:
689 rscreen->tiling_info.group_bytes = 256;
690 break;
691 case 1:
692 rscreen->tiling_info.group_bytes = 512;
693 break;
694 default:
695 return false;
696 }
697 return true;
698 }
699
700 static bool r600_init_tiling(struct r600_common_screen *rscreen)
701 {
702 uint32_t tiling_config = rscreen->info.r600_tiling_config;
703
704 /* set default group bytes, overridden by tiling info ioctl */
705 if (rscreen->chip_class <= R700) {
706 rscreen->tiling_info.group_bytes = 256;
707 } else {
708 rscreen->tiling_info.group_bytes = 512;
709 }
710
711 if (!tiling_config)
712 return true;
713
714 if (rscreen->chip_class <= R700) {
715 return r600_interpret_tiling(rscreen, tiling_config);
716 } else {
717 return evergreen_interpret_tiling(rscreen, tiling_config);
718 }
719 }
720
721 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
722 const struct pipe_resource *templ)
723 {
724 if (templ->target == PIPE_BUFFER) {
725 return r600_buffer_create(screen, templ, 4096);
726 } else {
727 return r600_texture_create(screen, templ);
728 }
729 }
730
731 bool r600_common_screen_init(struct r600_common_screen *rscreen,
732 struct radeon_winsys *ws)
733 {
734 ws->query_info(ws, &rscreen->info);
735
736 rscreen->b.get_name = r600_get_name;
737 rscreen->b.get_vendor = r600_get_vendor;
738 rscreen->b.get_compute_param = r600_get_compute_param;
739 rscreen->b.get_paramf = r600_get_paramf;
740 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
741 rscreen->b.get_timestamp = r600_get_timestamp;
742 rscreen->b.fence_finish = r600_fence_finish;
743 rscreen->b.fence_reference = r600_fence_reference;
744 rscreen->b.fence_signalled = r600_fence_signalled;
745 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
746
747 if (rscreen->info.has_uvd) {
748 rscreen->b.get_video_param = rvid_get_video_param;
749 rscreen->b.is_video_format_supported = rvid_is_format_supported;
750 } else {
751 rscreen->b.get_video_param = r600_get_video_param;
752 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
753 }
754
755 r600_init_screen_texture_functions(rscreen);
756
757 rscreen->ws = ws;
758 rscreen->family = rscreen->info.family;
759 rscreen->chip_class = rscreen->info.chip_class;
760 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
761
762 if (!r600_init_tiling(rscreen)) {
763 return false;
764 }
765 util_format_s3tc_init();
766 pipe_mutex_init(rscreen->aux_context_lock);
767
768 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
769 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
770 PIPE_BIND_CUSTOM,
771 PIPE_USAGE_STAGING,
772 4096);
773 if (rscreen->trace_bo) {
774 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
775 PIPE_TRANSFER_UNSYNCHRONIZED);
776 }
777 }
778
779 return true;
780 }
781
782 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
783 {
784 pipe_mutex_destroy(rscreen->aux_context_lock);
785 rscreen->aux_context->destroy(rscreen->aux_context);
786
787 if (rscreen->trace_bo) {
788 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
789 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
790 }
791
792 rscreen->ws->destroy(rscreen->ws);
793 FREE(rscreen);
794 }
795
796 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
797 {
798 struct tgsi_parse_context parse;
799
800 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
801 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
802 return ~0;
803 }
804 return parse.FullHeader.Processor.Processor;
805 }
806
807 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
808 const struct tgsi_token *tokens)
809 {
810 /* Compute shader don't have tgsi_tokens */
811 if (!tokens)
812 return (rscreen->debug_flags & DBG_CS) != 0;
813
814 switch (tgsi_get_processor_type(tokens)) {
815 case TGSI_PROCESSOR_VERTEX:
816 return (rscreen->debug_flags & DBG_VS) != 0;
817 case TGSI_PROCESSOR_GEOMETRY:
818 return (rscreen->debug_flags & DBG_GS) != 0;
819 case TGSI_PROCESSOR_FRAGMENT:
820 return (rscreen->debug_flags & DBG_PS) != 0;
821 case TGSI_PROCESSOR_COMPUTE:
822 return (rscreen->debug_flags & DBG_CS) != 0;
823 default:
824 return false;
825 }
826 }
827
828 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
829 unsigned offset, unsigned size, unsigned value)
830 {
831 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
832
833 pipe_mutex_lock(rscreen->aux_context_lock);
834 rctx->clear_buffer(&rctx->b, dst, offset, size, value);
835 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
836 pipe_mutex_unlock(rscreen->aux_context_lock);
837 }