src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format_s3tc.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "vl/vl_decoder.h"
  34 #include "vl/vl_video_buffer.h"
  35 #include "radeon/radeon_video.h"
  36 #include <inttypes.h>
  37
  38 /*
  39  * pipe_context
  40  */
  41
  42 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
  43 {
  44         /* The number of dwords we already used in the DMA so far. */
  45         num_dw += ctx->rings.dma.cs->cdw;
  46         /* Flush if there's not enough space. */
  47         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
  48                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  49         }
  50 }
  51
  52 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
  53 {
  54 }
  55
  56 void r600_preflush_suspend_features(struct r600_common_context *ctx)
  57 {
  58         /* Disable render condition. */
  59         ctx->saved_render_cond = NULL;
  60         ctx->saved_render_cond_cond = FALSE;
  61         ctx->saved_render_cond_mode = 0;
  62         if (ctx->current_render_cond) {
  63                 ctx->saved_render_cond = ctx->current_render_cond;
  64                 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
  65                 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
  66                 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
  67         }
  68
  69         /* suspend queries */
  70         ctx->nontimer_queries_suspended = false;
  71         if (ctx->num_cs_dw_nontimer_queries_suspend) {
  72                 r600_suspend_nontimer_queries(ctx);
  73                 ctx->nontimer_queries_suspended = true;
  74         }
  75
  76         ctx->streamout.suspended = false;
  77         if (ctx->streamout.begin_emitted) {
  78                 r600_emit_streamout_end(ctx);
  79                 ctx->streamout.suspended = true;
  80         }
  81 }
  82
  83 void r600_postflush_resume_features(struct r600_common_context *ctx)
  84 {
  85         if (ctx->streamout.suspended) {
  86                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
  87                 r600_streamout_buffers_dirty(ctx);
  88         }
  89
  90         /* resume queries */
  91         if (ctx->nontimer_queries_suspended) {
  92                 r600_resume_nontimer_queries(ctx);
  93         }
  94
  95         /* Re-enable render condition. */
  96         if (ctx->saved_render_cond) {
  97                 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
  98                                           ctx->saved_render_cond_cond,
  99                                           ctx->saved_render_cond_mode);
 100         }
 101 }
 102
 103 static void r600_flush_from_st(struct pipe_context *ctx,
 104                                struct pipe_fence_handle **fence,
 105                                unsigned flags)
 106 {
 107         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 108         unsigned rflags = 0;
 109
 110         if (flags & PIPE_FLUSH_END_OF_FRAME)
 111                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 112
 113         if (rctx->rings.dma.cs) {
 114                 rctx->rings.dma.flush(rctx, rflags, NULL);
 115         }
 116         rctx->rings.gfx.flush(rctx, rflags, fence);
 117 }
 118
 119 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 120                                 struct pipe_fence_handle **fence)
 121 {
 122         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 123         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 124
 125         if (!cs->cdw) {
 126                 return;
 127         }
 128
 129         rctx->rings.dma.flushing = true;
 130         rctx->ws->cs_flush(cs, flags, fence, 0);
 131         rctx->rings.dma.flushing = false;
 132 }
 133
 134 bool r600_common_context_init(struct r600_common_context *rctx,
 135                               struct r600_common_screen *rscreen)
 136 {
 137         util_slab_create(&rctx->pool_transfers,
 138                          sizeof(struct r600_transfer), 64,
 139                          UTIL_SLAB_SINGLETHREADED);
 140
 141         rctx->screen = rscreen;
 142         rctx->ws = rscreen->ws;
 143         rctx->family = rscreen->family;
 144         rctx->chip_class = rscreen->chip_class;
 145
 146         if (rscreen->family == CHIP_HAWAII)
 147                 rctx->max_db = 16;
 148         else if (rscreen->chip_class >= EVERGREEN)
 149                 rctx->max_db = 8;
 150         else
 151                 rctx->max_db = 4;
 152
 153         rctx->b.transfer_map = u_transfer_map_vtbl;
 154         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
 155         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 156         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 157         rctx->b.memory_barrier = r600_memory_barrier;
 158         rctx->b.flush = r600_flush_from_st;
 159
 160         LIST_INITHEAD(&rctx->texture_buffers);
 161
 162         r600_init_context_texture_functions(rctx);
 163         r600_streamout_init(rctx);
 164         r600_query_init(rctx);
 165         cayman_init_msaa(&rctx->b);
 166
 167         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 168                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 169         if (!rctx->allocator_so_filled_size)
 170                 return false;
 171
 172         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 173                                         PIPE_BIND_INDEX_BUFFER |
 174                                         PIPE_BIND_CONSTANT_BUFFER);
 175         if (!rctx->uploader)
 176                 return false;
 177
 178         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 179                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 180                                                          r600_flush_dma_ring,
 181                                                          rctx, NULL);
 182                 rctx->rings.dma.flush = r600_flush_dma_ring;
 183         }
 184
 185         return true;
 186 }
 187
 188 void r600_common_context_cleanup(struct r600_common_context *rctx)
 189 {
 190         if (rctx->rings.gfx.cs) {
 191                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 192         }
 193         if (rctx->rings.dma.cs) {
 194                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 195         }
 196
 197         if (rctx->uploader) {
 198                 u_upload_destroy(rctx->uploader);
 199         }
 200
 201         util_slab_destroy(&rctx->pool_transfers);
 202
 203         if (rctx->allocator_so_filled_size) {
 204                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 205         }
 206 }
 207
 208 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 209 {
 210         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 211         struct r600_resource *rr = (struct r600_resource *)r;
 212
 213         if (r == NULL) {
 214                 return;
 215         }
 216
 217         /*
 218          * The idea is to compute a gross estimate of memory requirement of
 219          * each draw call. After each draw call, memory will be precisely
 220          * accounted. So the uncertainty is only on the current draw call.
 221          * In practice this gave very good estimate (+/- 10% of the target
 222          * memory limit).
 223          */
 224         if (rr->domains & RADEON_DOMAIN_GTT) {
 225                 rctx->gtt += rr->buf->size;
 226         }
 227         if (rr->domains & RADEON_DOMAIN_VRAM) {
 228                 rctx->vram += rr->buf->size;
 229         }
 230 }
 231
 232 /*
 233  * pipe_screen
 234  */
 235
 236 static const struct debug_named_value common_debug_options[] = {
 237         /* logging */
 238         { "tex", DBG_TEX, "Print texture info" },
 239         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 240         { "compute", DBG_COMPUTE, "Print compute info" },
 241         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 242         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 243
 244         /* shaders */
 245         { "fs", DBG_FS, "Print fetch shaders" },
 246         { "vs", DBG_VS, "Print vertex shaders" },
 247         { "gs", DBG_GS, "Print geometry shaders" },
 248         { "ps", DBG_PS, "Print pixel shaders" },
 249         { "cs", DBG_CS, "Print compute shaders" },
 250
 251         /* features */
 252         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 253         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 254         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 255         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 256         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 257         { "notiling", DBG_NO_TILING, "Disable tiling" },
 258         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 259
 260         DEBUG_NAMED_VALUE_END /* must be last */
 261 };
 262
 263 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 264 {
 265         return "X.Org";
 266 }
 267
 268 static const char* r600_get_name(struct pipe_screen* pscreen)
 269 {
 270         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 271
 272         switch (rscreen->family) {
 273         case CHIP_R600: return "AMD R600";
 274         case CHIP_RV610: return "AMD RV610";
 275         case CHIP_RV630: return "AMD RV630";
 276         case CHIP_RV670: return "AMD RV670";
 277         case CHIP_RV620: return "AMD RV620";
 278         case CHIP_RV635: return "AMD RV635";
 279         case CHIP_RS780: return "AMD RS780";
 280         case CHIP_RS880: return "AMD RS880";
 281         case CHIP_RV770: return "AMD RV770";
 282         case CHIP_RV730: return "AMD RV730";
 283         case CHIP_RV710: return "AMD RV710";
 284         case CHIP_RV740: return "AMD RV740";
 285         case CHIP_CEDAR: return "AMD CEDAR";
 286         case CHIP_REDWOOD: return "AMD REDWOOD";
 287         case CHIP_JUNIPER: return "AMD JUNIPER";
 288         case CHIP_CYPRESS: return "AMD CYPRESS";
 289         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 290         case CHIP_PALM: return "AMD PALM";
 291         case CHIP_SUMO: return "AMD SUMO";
 292         case CHIP_SUMO2: return "AMD SUMO2";
 293         case CHIP_BARTS: return "AMD BARTS";
 294         case CHIP_TURKS: return "AMD TURKS";
 295         case CHIP_CAICOS: return "AMD CAICOS";
 296         case CHIP_CAYMAN: return "AMD CAYMAN";
 297         case CHIP_ARUBA: return "AMD ARUBA";
 298         case CHIP_TAHITI: return "AMD TAHITI";
 299         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 300         case CHIP_VERDE: return "AMD CAPE VERDE";
 301         case CHIP_OLAND: return "AMD OLAND";
 302         case CHIP_HAINAN: return "AMD HAINAN";
 303         case CHIP_BONAIRE: return "AMD BONAIRE";
 304         case CHIP_KAVERI: return "AMD KAVERI";
 305         case CHIP_KABINI: return "AMD KABINI";
 306         case CHIP_HAWAII: return "AMD HAWAII";
 307         case CHIP_MULLINS: return "AMD MULLINS";
 308         default: return "AMD unknown";
 309         }
 310 }
 311
 312 static float r600_get_paramf(struct pipe_screen* pscreen,
 313                              enum pipe_capf param)
 314 {
 315         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 316
 317         switch (param) {
 318         case PIPE_CAPF_MAX_LINE_WIDTH:
 319         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 320         case PIPE_CAPF_MAX_POINT_WIDTH:
 321         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 322                 if (rscreen->family >= CHIP_CEDAR)
 323                         return 16384.0f;
 324                 else
 325                         return 8192.0f;
 326         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 327                 return 16.0f;
 328         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 329                 return 16.0f;
 330         case PIPE_CAPF_GUARD_BAND_LEFT:
 331         case PIPE_CAPF_GUARD_BAND_TOP:
 332         case PIPE_CAPF_GUARD_BAND_RIGHT:
 333         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 334                 return 0.0f;
 335         }
 336         return 0.0f;
 337 }
 338
 339 static int r600_get_video_param(struct pipe_screen *screen,
 340                                 enum pipe_video_profile profile,
 341                                 enum pipe_video_entrypoint entrypoint,
 342                                 enum pipe_video_cap param)
 343 {
 344         switch (param) {
 345         case PIPE_VIDEO_CAP_SUPPORTED:
 346                 return vl_profile_supported(screen, profile, entrypoint);
 347         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 348                 return 1;
 349         case PIPE_VIDEO_CAP_MAX_WIDTH:
 350         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 351                 return vl_video_buffer_max_size(screen);
 352         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 353                 return PIPE_FORMAT_NV12;
 354         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 355                 return false;
 356         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 357                 return false;
 358         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 359                 return true;
 360         case PIPE_VIDEO_CAP_MAX_LEVEL:
 361                 return vl_level_supported(screen, profile);
 362         default:
 363                 return 0;
 364         }
 365 }
 366
 367 const char *r600_get_llvm_processor_name(enum radeon_family family)
 368 {
 369         switch (family) {
 370         case CHIP_R600:
 371         case CHIP_RV630:
 372         case CHIP_RV635:
 373         case CHIP_RV670:
 374                 return "r600";
 375         case CHIP_RV610:
 376         case CHIP_RV620:
 377         case CHIP_RS780:
 378         case CHIP_RS880:
 379                 return "rs880";
 380         case CHIP_RV710:
 381                 return "rv710";
 382         case CHIP_RV730:
 383                 return "rv730";
 384         case CHIP_RV740:
 385         case CHIP_RV770:
 386                 return "rv770";
 387         case CHIP_PALM:
 388         case CHIP_CEDAR:
 389                 return "cedar";
 390         case CHIP_SUMO:
 391         case CHIP_SUMO2:
 392                 return "sumo";
 393         case CHIP_REDWOOD:
 394                 return "redwood";
 395         case CHIP_JUNIPER:
 396                 return "juniper";
 397         case CHIP_HEMLOCK:
 398         case CHIP_CYPRESS:
 399                 return "cypress";
 400         case CHIP_BARTS:
 401                 return "barts";
 402         case CHIP_TURKS:
 403                 return "turks";
 404         case CHIP_CAICOS:
 405                 return "caicos";
 406         case CHIP_CAYMAN:
 407         case CHIP_ARUBA:
 408                 return "cayman";
 409
 410         case CHIP_TAHITI: return "tahiti";
 411         case CHIP_PITCAIRN: return "pitcairn";
 412         case CHIP_VERDE: return "verde";
 413         case CHIP_OLAND: return "oland";
 414         case CHIP_HAINAN: return "hainan";
 415         case CHIP_BONAIRE: return "bonaire";
 416         case CHIP_KABINI: return "kabini";
 417         case CHIP_KAVERI: return "kaveri";
 418         case CHIP_HAWAII: return "hawaii";
 419         case CHIP_MULLINS:
 420 #if HAVE_LLVM >= 0x0305
 421                 return "mullins";
 422 #else
 423                 return "kabini";
 424 #endif
 425         default: return "";
 426         }
 427 }
 428
 429 static int r600_get_compute_param(struct pipe_screen *screen,
 430         enum pipe_compute_cap param,
 431         void *ret)
 432 {
 433         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 434
 435         //TODO: select these params by asic
 436         switch (param) {
 437         case PIPE_COMPUTE_CAP_IR_TARGET: {
 438                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 439                 if (ret) {
 440                         sprintf(ret, "%s-r600--", gpu);
 441                 }
 442                 return (8 + strlen(gpu)) * sizeof(char);
 443         }
 444         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 445                 if (ret) {
 446                         uint64_t *grid_dimension = ret;
 447                         grid_dimension[0] = 3;
 448                 }
 449                 return 1 * sizeof(uint64_t);
 450
 451         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 452                 if (ret) {
 453                         uint64_t *grid_size = ret;
 454                         grid_size[0] = 65535;
 455                         grid_size[1] = 65535;
 456                         grid_size[2] = 1;
 457                 }
 458                 return 3 * sizeof(uint64_t) ;
 459
 460         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 461                 if (ret) {
 462                         uint64_t *block_size = ret;
 463                         block_size[0] = 256;
 464                         block_size[1] = 256;
 465                         block_size[2] = 256;
 466                 }
 467                 return 3 * sizeof(uint64_t);
 468
 469         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 470                 if (ret) {
 471                         uint64_t *max_threads_per_block = ret;
 472                         *max_threads_per_block = 256;
 473                 }
 474                 return sizeof(uint64_t);
 475
 476         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 477                 if (ret) {
 478                         uint64_t *max_global_size = ret;
 479                         uint64_t max_mem_alloc_size;
 480
 481                         r600_get_compute_param(screen,
 482                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 483                                 &max_mem_alloc_size);
 484
 485                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 486                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 487                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 488                          * make sure we never report more than
 489                          * 4 * MAX_MEM_ALLOC_SIZE.
 490                          */
 491                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 492                                 rscreen->info.gart_size +
 493                                 rscreen->info.vram_size);
 494                 }
 495                 return sizeof(uint64_t);
 496
 497         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 498                 if (ret) {
 499                         uint64_t *max_local_size = ret;
 500                         /* Value reported by the closed source driver. */
 501                         *max_local_size = 32768;
 502                 }
 503                 return sizeof(uint64_t);
 504
 505         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 506                 if (ret) {
 507                         uint64_t *max_input_size = ret;
 508                         /* Value reported by the closed source driver. */
 509                         *max_input_size = 1024;
 510                 }
 511                 return sizeof(uint64_t);
 512
 513         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 514                 if (ret) {
 515                         uint64_t max_global_size;
 516                         uint64_t *max_mem_alloc_size = ret;
 517
 518                         /* XXX: The limit in older kernels is 256 MB.  We
 519                          * should add a query here for newer kernels.
 520                          */
 521                         *max_mem_alloc_size = 256 * 1024 * 1024;
 522                 }
 523                 return sizeof(uint64_t);
 524
 525         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 526                 if (ret) {
 527                         uint32_t *max_clock_frequency = ret;
 528                         *max_clock_frequency = rscreen->info.max_sclk;
 529                 }
 530                 return sizeof(uint32_t);
 531
 532         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 533                 if (ret) {
 534                         uint32_t *max_compute_units = ret;
 535                         *max_compute_units = MAX2(rscreen->info.max_compute_units, 1);
 536                 }
 537                 return sizeof(uint32_t);
 538
 539         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 540                 if (ret) {
 541                         uint32_t *images_supported = ret;
 542                         *images_supported = 0;
 543                 }
 544                 return sizeof(uint32_t);
 545         }
 546
 547         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 548         return 0;
 549 }
 550
 551 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 552 {
 553         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 554
 555         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 556                         rscreen->info.r600_clock_crystal_freq;
 557 }
 558
 559 static int r600_get_driver_query_info(struct pipe_screen *screen,
 560                                       unsigned index,
 561                                       struct pipe_driver_query_info *info)
 562 {
 563         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 564         struct pipe_driver_query_info list[] = {
 565                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 566                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 567                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 568                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 569                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 570                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 571                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 572                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 573         };
 574
 575         if (!info)
 576                 return Elements(list);
 577
 578         if (index >= Elements(list))
 579                 return 0;
 580
 581         *info = list[index];
 582         return 1;
 583 }
 584
 585 static void r600_fence_reference(struct pipe_screen *screen,
 586                                  struct pipe_fence_handle **ptr,
 587                                  struct pipe_fence_handle *fence)
 588 {
 589         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 590
 591         rws->fence_reference(ptr, fence);
 592 }
 593
 594 static boolean r600_fence_signalled(struct pipe_screen *screen,
 595                                     struct pipe_fence_handle *fence)
 596 {
 597         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 598
 599         return rws->fence_wait(rws, fence, 0);
 600 }
 601
 602 static boolean r600_fence_finish(struct pipe_screen *screen,
 603                                  struct pipe_fence_handle *fence,
 604                                  uint64_t timeout)
 605 {
 606         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 607
 608         return rws->fence_wait(rws, fence, timeout);
 609 }
 610
 611 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 612                                   uint32_t tiling_config)
 613 {
 614         switch ((tiling_config & 0xe) >> 1) {
 615         case 0:
 616                 rscreen->tiling_info.num_channels = 1;
 617                 break;
 618         case 1:
 619                 rscreen->tiling_info.num_channels = 2;
 620                 break;
 621         case 2:
 622                 rscreen->tiling_info.num_channels = 4;
 623                 break;
 624         case 3:
 625                 rscreen->tiling_info.num_channels = 8;
 626                 break;
 627         default:
 628                 return false;
 629         }
 630
 631         switch ((tiling_config & 0x30) >> 4) {
 632         case 0:
 633                 rscreen->tiling_info.num_banks = 4;
 634                 break;
 635         case 1:
 636                 rscreen->tiling_info.num_banks = 8;
 637                 break;
 638         default:
 639                 return false;
 640
 641         }
 642         switch ((tiling_config & 0xc0) >> 6) {
 643         case 0:
 644                 rscreen->tiling_info.group_bytes = 256;
 645                 break;
 646         case 1:
 647                 rscreen->tiling_info.group_bytes = 512;
 648                 break;
 649         default:
 650                 return false;
 651         }
 652         return true;
 653 }
 654
 655 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 656                                        uint32_t tiling_config)
 657 {
 658         switch (tiling_config & 0xf) {
 659         case 0:
 660                 rscreen->tiling_info.num_channels = 1;
 661                 break;
 662         case 1:
 663                 rscreen->tiling_info.num_channels = 2;
 664                 break;
 665         case 2:
 666                 rscreen->tiling_info.num_channels = 4;
 667                 break;
 668         case 3:
 669                 rscreen->tiling_info.num_channels = 8;
 670                 break;
 671         default:
 672                 return false;
 673         }
 674
 675         switch ((tiling_config & 0xf0) >> 4) {
 676         case 0:
 677                 rscreen->tiling_info.num_banks = 4;
 678                 break;
 679         case 1:
 680                 rscreen->tiling_info.num_banks = 8;
 681                 break;
 682         case 2:
 683                 rscreen->tiling_info.num_banks = 16;
 684                 break;
 685         default:
 686                 return false;
 687         }
 688
 689         switch ((tiling_config & 0xf00) >> 8) {
 690         case 0:
 691                 rscreen->tiling_info.group_bytes = 256;
 692                 break;
 693         case 1:
 694                 rscreen->tiling_info.group_bytes = 512;
 695                 break;
 696         default:
 697                 return false;
 698         }
 699         return true;
 700 }
 701
 702 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 703 {
 704         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 705
 706         /* set default group bytes, overridden by tiling info ioctl */
 707         if (rscreen->chip_class <= R700) {
 708                 rscreen->tiling_info.group_bytes = 256;
 709         } else {
 710                 rscreen->tiling_info.group_bytes = 512;
 711         }
 712
 713         if (!tiling_config)
 714                 return true;
 715
 716         if (rscreen->chip_class <= R700) {
 717                 return r600_interpret_tiling(rscreen, tiling_config);
 718         } else {
 719                 return evergreen_interpret_tiling(rscreen, tiling_config);
 720         }
 721 }
 722
 723 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 724                                                   const struct pipe_resource *templ)
 725 {
 726         if (templ->target == PIPE_BUFFER) {
 727                 return r600_buffer_create(screen, templ, 4096);
 728         } else {
 729                 return r600_texture_create(screen, templ);
 730         }
 731 }
 732
 733 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 734                              struct radeon_winsys *ws)
 735 {
 736         ws->query_info(ws, &rscreen->info);
 737
 738         rscreen->b.get_name = r600_get_name;
 739         rscreen->b.get_vendor = r600_get_vendor;
 740         rscreen->b.get_compute_param = r600_get_compute_param;
 741         rscreen->b.get_paramf = r600_get_paramf;
 742         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 743         rscreen->b.get_timestamp = r600_get_timestamp;
 744         rscreen->b.fence_finish = r600_fence_finish;
 745         rscreen->b.fence_reference = r600_fence_reference;
 746         rscreen->b.fence_signalled = r600_fence_signalled;
 747         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 748
 749         if (rscreen->info.has_uvd) {
 750                 rscreen->b.get_video_param = rvid_get_video_param;
 751                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 752         } else {
 753                 rscreen->b.get_video_param = r600_get_video_param;
 754                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 755         }
 756
 757         r600_init_screen_texture_functions(rscreen);
 758
 759         rscreen->ws = ws;
 760         rscreen->family = rscreen->info.family;
 761         rscreen->chip_class = rscreen->info.chip_class;
 762         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 763
 764         if (!r600_init_tiling(rscreen)) {
 765                 return false;
 766         }
 767         util_format_s3tc_init();
 768         pipe_mutex_init(rscreen->aux_context_lock);
 769
 770         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 771                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 772                                                                                 PIPE_BIND_CUSTOM,
 773                                                                                 PIPE_USAGE_STAGING,
 774                                                                                 4096);
 775                 if (rscreen->trace_bo) {
 776                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 777                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 778                 }
 779         }
 780
 781         return true;
 782 }
 783
 784 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 785 {
 786         pipe_mutex_destroy(rscreen->aux_context_lock);
 787         rscreen->aux_context->destroy(rscreen->aux_context);
 788
 789         if (rscreen->trace_bo) {
 790                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 791                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 792         }
 793
 794         rscreen->ws->destroy(rscreen->ws);
 795         FREE(rscreen);
 796 }
 797
 798 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 799 {
 800         struct tgsi_parse_context parse;
 801
 802         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 803                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 804                 return ~0;
 805         }
 806         return parse.FullHeader.Processor.Processor;
 807 }
 808
 809 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 810                           const struct tgsi_token *tokens)
 811 {
 812         /* Compute shader don't have tgsi_tokens */
 813         if (!tokens)
 814                 return (rscreen->debug_flags & DBG_CS) != 0;
 815
 816         switch (tgsi_get_processor_type(tokens)) {
 817         case TGSI_PROCESSOR_VERTEX:
 818                 return (rscreen->debug_flags & DBG_VS) != 0;
 819         case TGSI_PROCESSOR_GEOMETRY:
 820                 return (rscreen->debug_flags & DBG_GS) != 0;
 821         case TGSI_PROCESSOR_FRAGMENT:
 822                 return (rscreen->debug_flags & DBG_PS) != 0;
 823         case TGSI_PROCESSOR_COMPUTE:
 824                 return (rscreen->debug_flags & DBG_CS) != 0;
 825         default:
 826                 return false;
 827         }
 828 }
 829
 830 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 831                               unsigned offset, unsigned size, unsigned value)
 832 {
 833         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 834
 835         pipe_mutex_lock(rscreen->aux_context_lock);
 836         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 837         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 838         pipe_mutex_unlock(rscreen->aux_context_lock);
 839 }