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gallium/u_blitter: add new union blitter_attrib to replace pipe_color_union
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112 unsigned sel = EOP_DATA_SEL(data_sel);
113
114 /* Wait for write confirmation before writing data, but don't send
115 * an interrupt. */
116 if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
117 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
118
119 if (ctx->chip_class >= GFX9) {
120 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
121 * counters) must immediately precede every timestamp event to
122 * prevent a GPU hang on GFX9.
123 *
124 * Occlusion queries don't need to do it here, because they
125 * always do ZPASS_DONE before the timestamp.
126 */
127 if (ctx->chip_class == GFX9 &&
128 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
129 query_type != PIPE_QUERY_OCCLUSION_PREDICATE) {
130 struct r600_resource *scratch = ctx->eop_bug_scratch;
131
132 assert(16 * ctx->screen->info.num_render_backends <=
133 scratch->b.b.width0);
134 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
135 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
136 radeon_emit(cs, scratch->gpu_address);
137 radeon_emit(cs, scratch->gpu_address >> 32);
138
139 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
140 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
141 }
142
143 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
144 radeon_emit(cs, op);
145 radeon_emit(cs, sel);
146 radeon_emit(cs, va); /* address lo */
147 radeon_emit(cs, va >> 32); /* address hi */
148 radeon_emit(cs, new_fence); /* immediate data lo */
149 radeon_emit(cs, 0); /* immediate data hi */
150 radeon_emit(cs, 0); /* unused */
151 } else {
152 if (ctx->chip_class == CIK ||
153 ctx->chip_class == VI) {
154 struct r600_resource *scratch = ctx->eop_bug_scratch;
155 uint64_t va = scratch->gpu_address;
156
157 /* Two EOP events are required to make all engines go idle
158 * (and optional cache flushes executed) before the timestamp
159 * is written.
160 */
161 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
162 radeon_emit(cs, op);
163 radeon_emit(cs, va);
164 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
165 radeon_emit(cs, 0); /* immediate data */
166 radeon_emit(cs, 0); /* unused */
167
168 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
169 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
170 }
171
172 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
173 radeon_emit(cs, op);
174 radeon_emit(cs, va);
175 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
176 radeon_emit(cs, new_fence); /* immediate data */
177 radeon_emit(cs, 0); /* unused */
178 }
179
180 if (buf)
181 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
182 RADEON_PRIO_QUERY);
183 }
184
185 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
186 {
187 unsigned dwords = 6;
188
189 if (screen->chip_class == CIK ||
190 screen->chip_class == VI)
191 dwords *= 2;
192
193 if (!screen->info.has_virtual_memory)
194 dwords += 2;
195
196 return dwords;
197 }
198
199 void r600_gfx_wait_fence(struct r600_common_context *ctx,
200 uint64_t va, uint32_t ref, uint32_t mask)
201 {
202 struct radeon_winsys_cs *cs = ctx->gfx.cs;
203
204 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
205 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
206 radeon_emit(cs, va);
207 radeon_emit(cs, va >> 32);
208 radeon_emit(cs, ref); /* reference value */
209 radeon_emit(cs, mask); /* mask */
210 radeon_emit(cs, 4); /* poll interval */
211 }
212
213 void r600_draw_rectangle(struct blitter_context *blitter,
214 int x1, int y1, int x2, int y2, float depth,
215 enum blitter_attrib_type type,
216 const union blitter_attrib *attrib)
217 {
218 struct r600_common_context *rctx =
219 (struct r600_common_context*)util_blitter_get_pipe(blitter);
220 struct pipe_viewport_state viewport;
221 struct pipe_resource *buf = NULL;
222 unsigned offset = 0;
223 float *vb;
224
225 /* Some operations (like color resolve on r6xx) don't work
226 * with the conventional primitive types.
227 * One that works is PT_RECTLIST, which we use here. */
228
229 /* setup viewport */
230 viewport.scale[0] = 1.0f;
231 viewport.scale[1] = 1.0f;
232 viewport.scale[2] = 1.0f;
233 viewport.translate[0] = 0.0f;
234 viewport.translate[1] = 0.0f;
235 viewport.translate[2] = 0.0f;
236 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
237
238 /* Upload vertices. The hw rectangle has only 3 vertices,
239 * The 4th one is derived from the first 3.
240 * The vertex specification should match u_blitter's vertex element state. */
241 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
242 rctx->screen->info.tcc_cache_line_size,
243 &offset, &buf, (void**)&vb);
244 if (!buf)
245 return;
246
247 vb[0] = x1;
248 vb[1] = y1;
249 vb[2] = depth;
250 vb[3] = 1;
251
252 vb[8] = x1;
253 vb[9] = y2;
254 vb[10] = depth;
255 vb[11] = 1;
256
257 vb[16] = x2;
258 vb[17] = y1;
259 vb[18] = depth;
260 vb[19] = 1;
261
262 switch (type) {
263 case UTIL_BLITTER_ATTRIB_COLOR:
264 memcpy(vb+4, attrib->color, sizeof(float)*4);
265 memcpy(vb+12, attrib->color, sizeof(float)*4);
266 memcpy(vb+20, attrib->color, sizeof(float)*4);
267 break;
268 case UTIL_BLITTER_ATTRIB_TEXCOORD:
269 vb[4] = attrib->texcoord.x1;
270 vb[5] = attrib->texcoord.y1;
271 vb[12] = attrib->texcoord.x1;
272 vb[13] = attrib->texcoord.y2;
273 vb[20] = attrib->texcoord.x2;
274 vb[21] = attrib->texcoord.y1;
275 break;
276 default:; /* Nothing to do. */
277 }
278
279 /* draw */
280 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
281 R600_PRIM_RECTANGLE_LIST, 3, 2);
282 pipe_resource_reference(&buf, NULL);
283 }
284
285 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
286 {
287 struct radeon_winsys_cs *cs = rctx->dma.cs;
288
289 /* NOP waits for idle on Evergreen and later. */
290 if (rctx->chip_class >= CIK)
291 radeon_emit(cs, 0x00000000); /* NOP */
292 else if (rctx->chip_class >= EVERGREEN)
293 radeon_emit(cs, 0xf0000000); /* NOP */
294 else {
295 /* TODO: R600-R700 should use the FENCE packet.
296 * CS checker support is required. */
297 }
298 }
299
300 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
301 struct r600_resource *dst, struct r600_resource *src)
302 {
303 uint64_t vram = ctx->dma.cs->used_vram;
304 uint64_t gtt = ctx->dma.cs->used_gart;
305
306 if (dst) {
307 vram += dst->vram_usage;
308 gtt += dst->gart_usage;
309 }
310 if (src) {
311 vram += src->vram_usage;
312 gtt += src->gart_usage;
313 }
314
315 /* Flush the GFX IB if DMA depends on it. */
316 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
317 ((dst &&
318 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
319 RADEON_USAGE_READWRITE)) ||
320 (src &&
321 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
322 RADEON_USAGE_WRITE))))
323 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
324
325 /* Flush if there's not enough space, or if the memory usage per IB
326 * is too large.
327 *
328 * IBs using too little memory are limited by the IB submission overhead.
329 * IBs using too much memory are limited by the kernel/TTM overhead.
330 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
331 *
332 * This heuristic makes sure that DMA requests are executed
333 * very soon after the call is made and lowers memory usage.
334 * It improves texture upload performance by keeping the DMA
335 * engine busy while uploads are being submitted.
336 */
337 num_dw++; /* for emit_wait_idle below */
338 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
339 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
340 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
341 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
342 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
343 }
344
345 /* Wait for idle if either buffer has been used in the IB before to
346 * prevent read-after-write hazards.
347 */
348 if ((dst &&
349 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
350 RADEON_USAGE_READWRITE)) ||
351 (src &&
352 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
353 RADEON_USAGE_WRITE)))
354 r600_dma_emit_wait_idle(ctx);
355
356 /* If GPUVM is not supported, the CS checker needs 2 entries
357 * in the buffer list per packet, which has to be done manually.
358 */
359 if (ctx->screen->info.has_virtual_memory) {
360 if (dst)
361 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
362 RADEON_USAGE_WRITE,
363 RADEON_PRIO_SDMA_BUFFER);
364 if (src)
365 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
366 RADEON_USAGE_READ,
367 RADEON_PRIO_SDMA_BUFFER);
368 }
369
370 /* this function is called before all DMA calls, so increment this. */
371 ctx->num_dma_calls++;
372 }
373
374 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
375 {
376 }
377
378 void r600_preflush_suspend_features(struct r600_common_context *ctx)
379 {
380 /* suspend queries */
381 if (!LIST_IS_EMPTY(&ctx->active_queries))
382 r600_suspend_queries(ctx);
383
384 ctx->streamout.suspended = false;
385 if (ctx->streamout.begin_emitted) {
386 r600_emit_streamout_end(ctx);
387 ctx->streamout.suspended = true;
388 }
389 }
390
391 void r600_postflush_resume_features(struct r600_common_context *ctx)
392 {
393 if (ctx->streamout.suspended) {
394 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
395 r600_streamout_buffers_dirty(ctx);
396 }
397
398 /* resume queries */
399 if (!LIST_IS_EMPTY(&ctx->active_queries))
400 r600_resume_queries(ctx);
401 }
402
403 static void r600_flush_from_st(struct pipe_context *ctx,
404 struct pipe_fence_handle **fence,
405 unsigned flags)
406 {
407 struct pipe_screen *screen = ctx->screen;
408 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
409 struct radeon_winsys *ws = rctx->ws;
410 struct pipe_fence_handle *gfx_fence = NULL;
411 struct pipe_fence_handle *sdma_fence = NULL;
412 bool deferred_fence = false;
413 unsigned rflags = RADEON_FLUSH_ASYNC;
414
415 if (flags & PIPE_FLUSH_END_OF_FRAME)
416 rflags |= RADEON_FLUSH_END_OF_FRAME;
417
418 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
419 if (rctx->dma.cs)
420 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
421
422 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
423 if (fence)
424 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
425 if (!(flags & PIPE_FLUSH_DEFERRED))
426 ws->cs_sync_flush(rctx->gfx.cs);
427 } else {
428 /* Instead of flushing, create a deferred fence. Constraints:
429 * - The state tracker must allow a deferred flush.
430 * - The state tracker must request a fence.
431 * Thread safety in fence_finish must be ensured by the state tracker.
432 */
433 if (flags & PIPE_FLUSH_DEFERRED && fence) {
434 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
435 deferred_fence = true;
436 } else {
437 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
438 }
439 }
440
441 /* Both engines can signal out of order, so we need to keep both fences. */
442 if (fence) {
443 struct r600_multi_fence *multi_fence =
444 CALLOC_STRUCT(r600_multi_fence);
445 if (!multi_fence)
446 return;
447
448 multi_fence->reference.count = 1;
449 /* If both fences are NULL, fence_finish will always return true. */
450 multi_fence->gfx = gfx_fence;
451 multi_fence->sdma = sdma_fence;
452
453 if (deferred_fence) {
454 multi_fence->gfx_unflushed.ctx = rctx;
455 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
456 }
457
458 screen->fence_reference(screen, fence, NULL);
459 *fence = (struct pipe_fence_handle*)multi_fence;
460 }
461
462 if (!(flags & PIPE_FLUSH_DEFERRED)) {
463 if (rctx->dma.cs)
464 ws->cs_sync_flush(rctx->dma.cs);
465 ws->cs_sync_flush(rctx->gfx.cs);
466 }
467 }
468
469 static void r600_flush_dma_ring(void *ctx, unsigned flags,
470 struct pipe_fence_handle **fence)
471 {
472 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
473 struct radeon_winsys_cs *cs = rctx->dma.cs;
474 struct radeon_saved_cs saved;
475 bool check_vm =
476 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
477 rctx->check_vm_faults;
478
479 if (!radeon_emitted(cs, 0)) {
480 if (fence)
481 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
482 return;
483 }
484
485 if (check_vm)
486 radeon_save_cs(rctx->ws, cs, &saved, true);
487
488 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
489 if (fence)
490 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
491
492 if (check_vm) {
493 /* Use conservative timeout 800ms, after which we won't wait any
494 * longer and assume the GPU is hung.
495 */
496 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
497
498 rctx->check_vm_faults(rctx, &saved, RING_DMA);
499 radeon_clear_saved_cs(&saved);
500 }
501 }
502
503 /**
504 * Store a linearized copy of all chunks of \p cs together with the buffer
505 * list in \p saved.
506 */
507 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
508 struct radeon_saved_cs *saved, bool get_buffer_list)
509 {
510 uint32_t *buf;
511 unsigned i;
512
513 /* Save the IB chunks. */
514 saved->num_dw = cs->prev_dw + cs->current.cdw;
515 saved->ib = MALLOC(4 * saved->num_dw);
516 if (!saved->ib)
517 goto oom;
518
519 buf = saved->ib;
520 for (i = 0; i < cs->num_prev; ++i) {
521 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
522 buf += cs->prev[i].cdw;
523 }
524 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
525
526 if (!get_buffer_list)
527 return;
528
529 /* Save the buffer list. */
530 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
531 saved->bo_list = CALLOC(saved->bo_count,
532 sizeof(saved->bo_list[0]));
533 if (!saved->bo_list) {
534 FREE(saved->ib);
535 goto oom;
536 }
537 ws->cs_get_buffer_list(cs, saved->bo_list);
538
539 return;
540
541 oom:
542 fprintf(stderr, "%s: out of memory\n", __func__);
543 memset(saved, 0, sizeof(*saved));
544 }
545
546 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
547 {
548 FREE(saved->ib);
549 FREE(saved->bo_list);
550
551 memset(saved, 0, sizeof(*saved));
552 }
553
554 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
555 {
556 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
557 unsigned latest = rctx->ws->query_value(rctx->ws,
558 RADEON_GPU_RESET_COUNTER);
559
560 if (rctx->gpu_reset_counter == latest)
561 return PIPE_NO_RESET;
562
563 rctx->gpu_reset_counter = latest;
564 return PIPE_UNKNOWN_CONTEXT_RESET;
565 }
566
567 static void r600_set_debug_callback(struct pipe_context *ctx,
568 const struct pipe_debug_callback *cb)
569 {
570 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
571
572 if (cb)
573 rctx->debug = *cb;
574 else
575 memset(&rctx->debug, 0, sizeof(rctx->debug));
576 }
577
578 static void r600_set_device_reset_callback(struct pipe_context *ctx,
579 const struct pipe_device_reset_callback *cb)
580 {
581 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
582
583 if (cb)
584 rctx->device_reset_callback = *cb;
585 else
586 memset(&rctx->device_reset_callback, 0,
587 sizeof(rctx->device_reset_callback));
588 }
589
590 bool r600_check_device_reset(struct r600_common_context *rctx)
591 {
592 enum pipe_reset_status status;
593
594 if (!rctx->device_reset_callback.reset)
595 return false;
596
597 if (!rctx->b.get_device_reset_status)
598 return false;
599
600 status = rctx->b.get_device_reset_status(&rctx->b);
601 if (status == PIPE_NO_RESET)
602 return false;
603
604 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
605 return true;
606 }
607
608 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
609 struct pipe_resource *dst,
610 uint64_t offset, uint64_t size,
611 unsigned value)
612 {
613 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
614
615 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
616 }
617
618 static bool r600_resource_commit(struct pipe_context *pctx,
619 struct pipe_resource *resource,
620 unsigned level, struct pipe_box *box,
621 bool commit)
622 {
623 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
624 struct r600_resource *res = r600_resource(resource);
625
626 /*
627 * Since buffer commitment changes cannot be pipelined, we need to
628 * (a) flush any pending commands that refer to the buffer we're about
629 * to change, and
630 * (b) wait for threaded submit to finish, including those that were
631 * triggered by some other, earlier operation.
632 */
633 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
634 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
635 res->buf, RADEON_USAGE_READWRITE)) {
636 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
637 }
638 if (radeon_emitted(ctx->dma.cs, 0) &&
639 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
640 res->buf, RADEON_USAGE_READWRITE)) {
641 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
642 }
643
644 ctx->ws->cs_sync_flush(ctx->dma.cs);
645 ctx->ws->cs_sync_flush(ctx->gfx.cs);
646
647 assert(resource->target == PIPE_BUFFER);
648
649 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
650 }
651
652 bool r600_common_context_init(struct r600_common_context *rctx,
653 struct r600_common_screen *rscreen,
654 unsigned context_flags)
655 {
656 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
657 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
658
659 rctx->screen = rscreen;
660 rctx->ws = rscreen->ws;
661 rctx->family = rscreen->family;
662 rctx->chip_class = rscreen->chip_class;
663
664 rctx->b.invalidate_resource = r600_invalidate_resource;
665 rctx->b.resource_commit = r600_resource_commit;
666 rctx->b.transfer_map = u_transfer_map_vtbl;
667 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
668 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
669 rctx->b.texture_subdata = u_default_texture_subdata;
670 rctx->b.memory_barrier = r600_memory_barrier;
671 rctx->b.flush = r600_flush_from_st;
672 rctx->b.set_debug_callback = r600_set_debug_callback;
673 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
674
675 /* evergreen_compute.c has a special codepath for global buffers.
676 * Everything else can use the direct path.
677 */
678 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
679 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
680 rctx->b.buffer_subdata = u_default_buffer_subdata;
681 else
682 rctx->b.buffer_subdata = r600_buffer_subdata;
683
684 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
685 rctx->b.get_device_reset_status = r600_get_reset_status;
686 rctx->gpu_reset_counter =
687 rctx->ws->query_value(rctx->ws,
688 RADEON_GPU_RESET_COUNTER);
689 }
690
691 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
692
693 r600_init_context_texture_functions(rctx);
694 r600_init_viewport_functions(rctx);
695 r600_streamout_init(rctx);
696 r600_query_init(rctx);
697 cayman_init_msaa(&rctx->b);
698
699 if (rctx->chip_class == CIK ||
700 rctx->chip_class == VI ||
701 rctx->chip_class == GFX9) {
702 rctx->eop_bug_scratch = (struct r600_resource*)
703 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
704 16 * rscreen->info.num_render_backends);
705 if (!rctx->eop_bug_scratch)
706 return false;
707 }
708
709 rctx->allocator_zeroed_memory =
710 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
711 0, PIPE_USAGE_DEFAULT, 0, true);
712 if (!rctx->allocator_zeroed_memory)
713 return false;
714
715 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
716 0, PIPE_USAGE_STREAM);
717 if (!rctx->b.stream_uploader)
718 return false;
719
720 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
721 0, PIPE_USAGE_DEFAULT);
722 if (!rctx->b.const_uploader)
723 return false;
724
725 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
726 if (!rctx->ctx)
727 return false;
728
729 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
730 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
731 r600_flush_dma_ring,
732 rctx);
733 rctx->dma.flush = r600_flush_dma_ring;
734 }
735
736 return true;
737 }
738
739 void r600_common_context_cleanup(struct r600_common_context *rctx)
740 {
741 unsigned i,j;
742
743 /* Release DCC stats. */
744 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
745 assert(!rctx->dcc_stats[i].query_active);
746
747 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
748 if (rctx->dcc_stats[i].ps_stats[j])
749 rctx->b.destroy_query(&rctx->b,
750 rctx->dcc_stats[i].ps_stats[j]);
751
752 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
753 }
754
755 if (rctx->query_result_shader)
756 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
757
758 if (rctx->gfx.cs)
759 rctx->ws->cs_destroy(rctx->gfx.cs);
760 if (rctx->dma.cs)
761 rctx->ws->cs_destroy(rctx->dma.cs);
762 if (rctx->ctx)
763 rctx->ws->ctx_destroy(rctx->ctx);
764
765 if (rctx->b.stream_uploader)
766 u_upload_destroy(rctx->b.stream_uploader);
767 if (rctx->b.const_uploader)
768 u_upload_destroy(rctx->b.const_uploader);
769
770 slab_destroy_child(&rctx->pool_transfers);
771 slab_destroy_child(&rctx->pool_transfers_unsync);
772
773 if (rctx->allocator_zeroed_memory) {
774 u_suballocator_destroy(rctx->allocator_zeroed_memory);
775 }
776 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
777 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
778 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
779 }
780
781 /*
782 * pipe_screen
783 */
784
785 static const struct debug_named_value common_debug_options[] = {
786 /* logging */
787 { "tex", DBG_TEX, "Print texture info" },
788 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
789 { "compute", DBG_COMPUTE, "Print compute info" },
790 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
791 { "info", DBG_INFO, "Print driver information" },
792
793 /* shaders */
794 { "fs", DBG_FS, "Print fetch shaders" },
795 { "vs", DBG_VS, "Print vertex shaders" },
796 { "gs", DBG_GS, "Print geometry shaders" },
797 { "ps", DBG_PS, "Print pixel shaders" },
798 { "cs", DBG_CS, "Print compute shaders" },
799 { "tcs", DBG_TCS, "Print tessellation control shaders" },
800 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
801 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
802 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
803 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
804 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
805 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
806 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
807
808 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
809 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
810 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
811 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
812
813 /* features */
814 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
815 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
816 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
817 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
818 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
819 { "notiling", DBG_NO_TILING, "Disable tiling" },
820 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
821 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
822 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
823 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
824 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
825 { "nodcc", DBG_NO_DCC, "Disable DCC." },
826 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
827 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
828 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
829 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
830 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
831 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
832 { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
833 { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
834
835 DEBUG_NAMED_VALUE_END /* must be last */
836 };
837
838 static const char* r600_get_vendor(struct pipe_screen* pscreen)
839 {
840 return "X.Org";
841 }
842
843 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
844 {
845 return "AMD";
846 }
847
848 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
849 {
850 if (!ws->get_chip_name)
851 return NULL;
852 return ws->get_chip_name(ws);
853 }
854
855 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
856 {
857 switch (rscreen->info.family) {
858 case CHIP_R600: return "AMD R600";
859 case CHIP_RV610: return "AMD RV610";
860 case CHIP_RV630: return "AMD RV630";
861 case CHIP_RV670: return "AMD RV670";
862 case CHIP_RV620: return "AMD RV620";
863 case CHIP_RV635: return "AMD RV635";
864 case CHIP_RS780: return "AMD RS780";
865 case CHIP_RS880: return "AMD RS880";
866 case CHIP_RV770: return "AMD RV770";
867 case CHIP_RV730: return "AMD RV730";
868 case CHIP_RV710: return "AMD RV710";
869 case CHIP_RV740: return "AMD RV740";
870 case CHIP_CEDAR: return "AMD CEDAR";
871 case CHIP_REDWOOD: return "AMD REDWOOD";
872 case CHIP_JUNIPER: return "AMD JUNIPER";
873 case CHIP_CYPRESS: return "AMD CYPRESS";
874 case CHIP_HEMLOCK: return "AMD HEMLOCK";
875 case CHIP_PALM: return "AMD PALM";
876 case CHIP_SUMO: return "AMD SUMO";
877 case CHIP_SUMO2: return "AMD SUMO2";
878 case CHIP_BARTS: return "AMD BARTS";
879 case CHIP_TURKS: return "AMD TURKS";
880 case CHIP_CAICOS: return "AMD CAICOS";
881 case CHIP_CAYMAN: return "AMD CAYMAN";
882 case CHIP_ARUBA: return "AMD ARUBA";
883 case CHIP_TAHITI: return "AMD TAHITI";
884 case CHIP_PITCAIRN: return "AMD PITCAIRN";
885 case CHIP_VERDE: return "AMD CAPE VERDE";
886 case CHIP_OLAND: return "AMD OLAND";
887 case CHIP_HAINAN: return "AMD HAINAN";
888 case CHIP_BONAIRE: return "AMD BONAIRE";
889 case CHIP_KAVERI: return "AMD KAVERI";
890 case CHIP_KABINI: return "AMD KABINI";
891 case CHIP_HAWAII: return "AMD HAWAII";
892 case CHIP_MULLINS: return "AMD MULLINS";
893 case CHIP_TONGA: return "AMD TONGA";
894 case CHIP_ICELAND: return "AMD ICELAND";
895 case CHIP_CARRIZO: return "AMD CARRIZO";
896 case CHIP_FIJI: return "AMD FIJI";
897 case CHIP_POLARIS10: return "AMD POLARIS10";
898 case CHIP_POLARIS11: return "AMD POLARIS11";
899 case CHIP_POLARIS12: return "AMD POLARIS12";
900 case CHIP_STONEY: return "AMD STONEY";
901 case CHIP_VEGA10: return "AMD VEGA10";
902 case CHIP_RAVEN: return "AMD RAVEN";
903 default: return "AMD unknown";
904 }
905 }
906
907 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
908 {
909 /* Don't use the cache if shader dumping is enabled. */
910 if (rscreen->debug_flags & DBG_ALL_SHADERS)
911 return;
912
913 uint32_t mesa_timestamp;
914 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
915 &mesa_timestamp)) {
916 char *timestamp_str;
917 int res = -1;
918 if (rscreen->chip_class < SI) {
919 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
920 }
921 #if HAVE_LLVM
922 else {
923 uint32_t llvm_timestamp;
924 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
925 &llvm_timestamp)) {
926 res = asprintf(&timestamp_str, "%u_%u",
927 mesa_timestamp, llvm_timestamp);
928 }
929 }
930 #endif
931 if (res != -1) {
932 /* These flags affect shader compilation. */
933 uint64_t shader_debug_flags =
934 rscreen->debug_flags &
935 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
936 DBG_SI_SCHED |
937 DBG_UNSAFE_MATH);
938
939 rscreen->disk_shader_cache =
940 disk_cache_create(r600_get_family_name(rscreen),
941 timestamp_str,
942 shader_debug_flags);
943 free(timestamp_str);
944 }
945 }
946 }
947
948 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
949 {
950 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
951 return rscreen->disk_shader_cache;
952 }
953
954 static const char* r600_get_name(struct pipe_screen* pscreen)
955 {
956 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
957
958 return rscreen->renderer_string;
959 }
960
961 static float r600_get_paramf(struct pipe_screen* pscreen,
962 enum pipe_capf param)
963 {
964 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
965
966 switch (param) {
967 case PIPE_CAPF_MAX_LINE_WIDTH:
968 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
969 case PIPE_CAPF_MAX_POINT_WIDTH:
970 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
971 if (rscreen->family >= CHIP_CEDAR)
972 return 16384.0f;
973 else
974 return 8192.0f;
975 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
976 return 16.0f;
977 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
978 return 16.0f;
979 case PIPE_CAPF_GUARD_BAND_LEFT:
980 case PIPE_CAPF_GUARD_BAND_TOP:
981 case PIPE_CAPF_GUARD_BAND_RIGHT:
982 case PIPE_CAPF_GUARD_BAND_BOTTOM:
983 return 0.0f;
984 }
985 return 0.0f;
986 }
987
988 static int r600_get_video_param(struct pipe_screen *screen,
989 enum pipe_video_profile profile,
990 enum pipe_video_entrypoint entrypoint,
991 enum pipe_video_cap param)
992 {
993 switch (param) {
994 case PIPE_VIDEO_CAP_SUPPORTED:
995 return vl_profile_supported(screen, profile, entrypoint);
996 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
997 return 1;
998 case PIPE_VIDEO_CAP_MAX_WIDTH:
999 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1000 return vl_video_buffer_max_size(screen);
1001 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1002 return PIPE_FORMAT_NV12;
1003 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1004 return false;
1005 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1006 return false;
1007 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1008 return true;
1009 case PIPE_VIDEO_CAP_MAX_LEVEL:
1010 return vl_level_supported(screen, profile);
1011 default:
1012 return 0;
1013 }
1014 }
1015
1016 const char *r600_get_llvm_processor_name(enum radeon_family family)
1017 {
1018 switch (family) {
1019 case CHIP_R600:
1020 case CHIP_RV630:
1021 case CHIP_RV635:
1022 case CHIP_RV670:
1023 return "r600";
1024 case CHIP_RV610:
1025 case CHIP_RV620:
1026 case CHIP_RS780:
1027 case CHIP_RS880:
1028 return "rs880";
1029 case CHIP_RV710:
1030 return "rv710";
1031 case CHIP_RV730:
1032 return "rv730";
1033 case CHIP_RV740:
1034 case CHIP_RV770:
1035 return "rv770";
1036 case CHIP_PALM:
1037 case CHIP_CEDAR:
1038 return "cedar";
1039 case CHIP_SUMO:
1040 case CHIP_SUMO2:
1041 return "sumo";
1042 case CHIP_REDWOOD:
1043 return "redwood";
1044 case CHIP_JUNIPER:
1045 return "juniper";
1046 case CHIP_HEMLOCK:
1047 case CHIP_CYPRESS:
1048 return "cypress";
1049 case CHIP_BARTS:
1050 return "barts";
1051 case CHIP_TURKS:
1052 return "turks";
1053 case CHIP_CAICOS:
1054 return "caicos";
1055 case CHIP_CAYMAN:
1056 case CHIP_ARUBA:
1057 return "cayman";
1058
1059 case CHIP_TAHITI: return "tahiti";
1060 case CHIP_PITCAIRN: return "pitcairn";
1061 case CHIP_VERDE: return "verde";
1062 case CHIP_OLAND: return "oland";
1063 case CHIP_HAINAN: return "hainan";
1064 case CHIP_BONAIRE: return "bonaire";
1065 case CHIP_KABINI: return "kabini";
1066 case CHIP_KAVERI: return "kaveri";
1067 case CHIP_HAWAII: return "hawaii";
1068 case CHIP_MULLINS:
1069 return "mullins";
1070 case CHIP_TONGA: return "tonga";
1071 case CHIP_ICELAND: return "iceland";
1072 case CHIP_CARRIZO: return "carrizo";
1073 case CHIP_FIJI:
1074 return "fiji";
1075 case CHIP_STONEY:
1076 return "stoney";
1077 case CHIP_POLARIS10:
1078 return "polaris10";
1079 case CHIP_POLARIS11:
1080 case CHIP_POLARIS12: /* same as polaris11 */
1081 return "polaris11";
1082 case CHIP_VEGA10:
1083 case CHIP_RAVEN:
1084 return "gfx900";
1085 default:
1086 return "";
1087 }
1088 }
1089
1090 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1091 enum pipe_shader_ir ir_type)
1092 {
1093 if (ir_type != PIPE_SHADER_IR_TGSI)
1094 return 256;
1095
1096 /* Only 16 waves per thread-group on gfx9. */
1097 if (screen->chip_class >= GFX9)
1098 return 1024;
1099
1100 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1101 * round number.
1102 */
1103 if (screen->chip_class >= SI)
1104 return 2048;
1105
1106 return 256;
1107 }
1108
1109 static int r600_get_compute_param(struct pipe_screen *screen,
1110 enum pipe_shader_ir ir_type,
1111 enum pipe_compute_cap param,
1112 void *ret)
1113 {
1114 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1115
1116 //TODO: select these params by asic
1117 switch (param) {
1118 case PIPE_COMPUTE_CAP_IR_TARGET: {
1119 const char *gpu;
1120 const char *triple;
1121 if (rscreen->family <= CHIP_ARUBA) {
1122 triple = "r600--";
1123 } else {
1124 if (HAVE_LLVM < 0x0400) {
1125 triple = "amdgcn--";
1126 } else {
1127 triple = "amdgcn-mesa-mesa3d";
1128 }
1129 }
1130 switch(rscreen->family) {
1131 /* Clang < 3.6 is missing Hainan in its list of
1132 * GPUs, so we need to use the name of a similar GPU.
1133 */
1134 default:
1135 gpu = r600_get_llvm_processor_name(rscreen->family);
1136 break;
1137 }
1138 if (ret) {
1139 sprintf(ret, "%s-%s", gpu, triple);
1140 }
1141 /* +2 for dash and terminating NIL byte */
1142 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1143 }
1144 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1145 if (ret) {
1146 uint64_t *grid_dimension = ret;
1147 grid_dimension[0] = 3;
1148 }
1149 return 1 * sizeof(uint64_t);
1150
1151 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1152 if (ret) {
1153 uint64_t *grid_size = ret;
1154 grid_size[0] = 65535;
1155 grid_size[1] = 65535;
1156 grid_size[2] = 65535;
1157 }
1158 return 3 * sizeof(uint64_t) ;
1159
1160 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1161 if (ret) {
1162 uint64_t *block_size = ret;
1163 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1164 block_size[0] = threads_per_block;
1165 block_size[1] = threads_per_block;
1166 block_size[2] = threads_per_block;
1167 }
1168 return 3 * sizeof(uint64_t);
1169
1170 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1171 if (ret) {
1172 uint64_t *max_threads_per_block = ret;
1173 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1174 }
1175 return sizeof(uint64_t);
1176 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1177 if (ret) {
1178 uint32_t *address_bits = ret;
1179 address_bits[0] = 32;
1180 if (rscreen->chip_class >= SI)
1181 address_bits[0] = 64;
1182 }
1183 return 1 * sizeof(uint32_t);
1184
1185 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1186 if (ret) {
1187 uint64_t *max_global_size = ret;
1188 uint64_t max_mem_alloc_size;
1189
1190 r600_get_compute_param(screen, ir_type,
1191 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1192 &max_mem_alloc_size);
1193
1194 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1195 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1196 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1197 * make sure we never report more than
1198 * 4 * MAX_MEM_ALLOC_SIZE.
1199 */
1200 *max_global_size = MIN2(4 * max_mem_alloc_size,
1201 MAX2(rscreen->info.gart_size,
1202 rscreen->info.vram_size));
1203 }
1204 return sizeof(uint64_t);
1205
1206 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1207 if (ret) {
1208 uint64_t *max_local_size = ret;
1209 /* Value reported by the closed source driver. */
1210 *max_local_size = 32768;
1211 }
1212 return sizeof(uint64_t);
1213
1214 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1215 if (ret) {
1216 uint64_t *max_input_size = ret;
1217 /* Value reported by the closed source driver. */
1218 *max_input_size = 1024;
1219 }
1220 return sizeof(uint64_t);
1221
1222 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1223 if (ret) {
1224 uint64_t *max_mem_alloc_size = ret;
1225
1226 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1227 }
1228 return sizeof(uint64_t);
1229
1230 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1231 if (ret) {
1232 uint32_t *max_clock_frequency = ret;
1233 *max_clock_frequency = rscreen->info.max_shader_clock;
1234 }
1235 return sizeof(uint32_t);
1236
1237 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1238 if (ret) {
1239 uint32_t *max_compute_units = ret;
1240 *max_compute_units = rscreen->info.num_good_compute_units;
1241 }
1242 return sizeof(uint32_t);
1243
1244 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1245 if (ret) {
1246 uint32_t *images_supported = ret;
1247 *images_supported = 0;
1248 }
1249 return sizeof(uint32_t);
1250 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1251 break; /* unused */
1252 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1253 if (ret) {
1254 uint32_t *subgroup_size = ret;
1255 *subgroup_size = r600_wavefront_size(rscreen->family);
1256 }
1257 return sizeof(uint32_t);
1258 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1259 if (ret) {
1260 uint64_t *max_variable_threads_per_block = ret;
1261 if (rscreen->chip_class >= SI &&
1262 ir_type == PIPE_SHADER_IR_TGSI)
1263 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1264 else
1265 *max_variable_threads_per_block = 0;
1266 }
1267 return sizeof(uint64_t);
1268 }
1269
1270 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1271 return 0;
1272 }
1273
1274 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1275 {
1276 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1277
1278 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1279 rscreen->info.clock_crystal_freq;
1280 }
1281
1282 static void r600_fence_reference(struct pipe_screen *screen,
1283 struct pipe_fence_handle **dst,
1284 struct pipe_fence_handle *src)
1285 {
1286 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1287 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1288 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1289
1290 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1291 ws->fence_reference(&(*rdst)->gfx, NULL);
1292 ws->fence_reference(&(*rdst)->sdma, NULL);
1293 FREE(*rdst);
1294 }
1295 *rdst = rsrc;
1296 }
1297
1298 static boolean r600_fence_finish(struct pipe_screen *screen,
1299 struct pipe_context *ctx,
1300 struct pipe_fence_handle *fence,
1301 uint64_t timeout)
1302 {
1303 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1304 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1305 struct r600_common_context *rctx;
1306 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1307
1308 ctx = threaded_context_unwrap_sync(ctx);
1309 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1310
1311 if (rfence->sdma) {
1312 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1313 return false;
1314
1315 /* Recompute the timeout after waiting. */
1316 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1317 int64_t time = os_time_get_nano();
1318 timeout = abs_timeout > time ? abs_timeout - time : 0;
1319 }
1320 }
1321
1322 if (!rfence->gfx)
1323 return true;
1324
1325 /* Flush the gfx IB if it hasn't been flushed yet. */
1326 if (rctx &&
1327 rfence->gfx_unflushed.ctx == rctx &&
1328 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1329 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1330 rfence->gfx_unflushed.ctx = NULL;
1331
1332 if (!timeout)
1333 return false;
1334
1335 /* Recompute the timeout after all that. */
1336 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1337 int64_t time = os_time_get_nano();
1338 timeout = abs_timeout > time ? abs_timeout - time : 0;
1339 }
1340 }
1341
1342 return rws->fence_wait(rws, rfence->gfx, timeout);
1343 }
1344
1345 static void r600_query_memory_info(struct pipe_screen *screen,
1346 struct pipe_memory_info *info)
1347 {
1348 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1349 struct radeon_winsys *ws = rscreen->ws;
1350 unsigned vram_usage, gtt_usage;
1351
1352 info->total_device_memory = rscreen->info.vram_size / 1024;
1353 info->total_staging_memory = rscreen->info.gart_size / 1024;
1354
1355 /* The real TTM memory usage is somewhat random, because:
1356 *
1357 * 1) TTM delays freeing memory, because it can only free it after
1358 * fences expire.
1359 *
1360 * 2) The memory usage can be really low if big VRAM evictions are
1361 * taking place, but the real usage is well above the size of VRAM.
1362 *
1363 * Instead, return statistics of this process.
1364 */
1365 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1366 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1367
1368 info->avail_device_memory =
1369 vram_usage <= info->total_device_memory ?
1370 info->total_device_memory - vram_usage : 0;
1371 info->avail_staging_memory =
1372 gtt_usage <= info->total_staging_memory ?
1373 info->total_staging_memory - gtt_usage : 0;
1374
1375 info->device_memory_evicted =
1376 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1377
1378 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1379 info->nr_device_memory_evictions =
1380 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1381 else
1382 /* Just return the number of evicted 64KB pages. */
1383 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1384 }
1385
1386 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1387 const struct pipe_resource *templ)
1388 {
1389 if (templ->target == PIPE_BUFFER) {
1390 return r600_buffer_create(screen, templ, 256);
1391 } else {
1392 return r600_texture_create(screen, templ);
1393 }
1394 }
1395
1396 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1397 struct radeon_winsys *ws)
1398 {
1399 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1400 struct utsname uname_data;
1401 const char *chip_name;
1402
1403 ws->query_info(ws, &rscreen->info);
1404 rscreen->ws = ws;
1405
1406 if ((chip_name = r600_get_marketing_name(ws)))
1407 snprintf(family_name, sizeof(family_name), "%s / ",
1408 r600_get_family_name(rscreen) + 4);
1409 else
1410 chip_name = r600_get_family_name(rscreen);
1411
1412 if (uname(&uname_data) == 0)
1413 snprintf(kernel_version, sizeof(kernel_version),
1414 " / %s", uname_data.release);
1415
1416 if (HAVE_LLVM > 0) {
1417 snprintf(llvm_string, sizeof(llvm_string),
1418 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1419 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1420 }
1421
1422 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1423 "%s (%sDRM %i.%i.%i%s%s)",
1424 chip_name, family_name, rscreen->info.drm_major,
1425 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1426 kernel_version, llvm_string);
1427
1428 rscreen->b.get_name = r600_get_name;
1429 rscreen->b.get_vendor = r600_get_vendor;
1430 rscreen->b.get_device_vendor = r600_get_device_vendor;
1431 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1432 rscreen->b.get_compute_param = r600_get_compute_param;
1433 rscreen->b.get_paramf = r600_get_paramf;
1434 rscreen->b.get_timestamp = r600_get_timestamp;
1435 rscreen->b.fence_finish = r600_fence_finish;
1436 rscreen->b.fence_reference = r600_fence_reference;
1437 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1438 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1439 rscreen->b.query_memory_info = r600_query_memory_info;
1440
1441 if (rscreen->info.has_hw_decode) {
1442 rscreen->b.get_video_param = rvid_get_video_param;
1443 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1444 } else {
1445 rscreen->b.get_video_param = r600_get_video_param;
1446 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1447 }
1448
1449 r600_init_screen_texture_functions(rscreen);
1450 r600_init_screen_query_functions(rscreen);
1451
1452 rscreen->family = rscreen->info.family;
1453 rscreen->chip_class = rscreen->info.chip_class;
1454 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1455 rscreen->has_rbplus = false;
1456 rscreen->rbplus_allowed = false;
1457
1458 r600_disk_cache_create(rscreen);
1459
1460 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1461
1462 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1463 if (rscreen->force_aniso >= 0) {
1464 printf("radeon: Forcing anisotropy filter to %ix\n",
1465 /* round down to a power of two */
1466 1 << util_logbase2(rscreen->force_aniso));
1467 }
1468
1469 util_format_s3tc_init();
1470 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1471 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1472
1473 if (rscreen->debug_flags & DBG_INFO) {
1474 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1475 rscreen->info.pci_domain, rscreen->info.pci_bus,
1476 rscreen->info.pci_dev, rscreen->info.pci_func);
1477 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1478 printf("family = %i (%s)\n", rscreen->info.family,
1479 r600_get_family_name(rscreen));
1480 printf("chip_class = %i\n", rscreen->info.chip_class);
1481 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1482 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1483 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1484 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1485 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1486 printf("max_alloc_size = %i MB\n",
1487 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1488 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1489 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1490 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1491 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1492 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1493 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1494 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1495 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1496 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1497 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1498 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1499 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1500 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1501 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1502 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1503 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1504 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1505 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1506 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1507
1508 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1509 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1510 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1511 printf("max_se = %i\n", rscreen->info.max_se);
1512 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1513
1514 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1515 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1516 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1517 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1518 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1519 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1520 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1521 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1522 }
1523 return true;
1524 }
1525
1526 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1527 {
1528 r600_perfcounters_destroy(rscreen);
1529 r600_gpu_load_kill_thread(rscreen);
1530
1531 mtx_destroy(&rscreen->gpu_load_mutex);
1532 mtx_destroy(&rscreen->aux_context_lock);
1533 rscreen->aux_context->destroy(rscreen->aux_context);
1534
1535 slab_destroy_parent(&rscreen->pool_transfers);
1536
1537 disk_cache_destroy(rscreen->disk_shader_cache);
1538 rscreen->ws->destroy(rscreen->ws);
1539 FREE(rscreen);
1540 }
1541
1542 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1543 unsigned processor)
1544 {
1545 return rscreen->debug_flags & (1 << processor);
1546 }
1547
1548 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1549 {
1550 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1551 r600_can_dump_shader(rscreen, processor);
1552 }
1553
1554 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1555 uint64_t offset, uint64_t size, unsigned value)
1556 {
1557 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1558
1559 mtx_lock(&rscreen->aux_context_lock);
1560 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1561 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1562 mtx_unlock(&rscreen->aux_context_lock);
1563 }