src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_draw_quad.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_upload_mgr.h"
  34 #include "vl/vl_decoder.h"
  35 #include "vl/vl_video_buffer.h"
  36 #include "radeon/radeon_video.h"
  37 #include <inttypes.h>
  38
  39 /*
  40  * pipe_context
  41  */
  42
  43 void r600_draw_rectangle(struct blitter_context *blitter,
  44                          int x1, int y1, int x2, int y2, float depth,
  45                          enum blitter_attrib_type type,
  46                          const union pipe_color_union *attrib)
  47 {
  48         struct r600_common_context *rctx =
  49                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  50         struct pipe_viewport_state viewport;
  51         struct pipe_resource *buf = NULL;
  52         unsigned offset = 0;
  53         float *vb;
  54
  55         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  56                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  57                 return;
  58         }
  59
  60         /* Some operations (like color resolve on r6xx) don't work
  61          * with the conventional primitive types.
  62          * One that works is PT_RECTLIST, which we use here. */
  63
  64         /* setup viewport */
  65         viewport.scale[0] = 1.0f;
  66         viewport.scale[1] = 1.0f;
  67         viewport.scale[2] = 1.0f;
  68         viewport.scale[3] = 1.0f;
  69         viewport.translate[0] = 0.0f;
  70         viewport.translate[1] = 0.0f;
  71         viewport.translate[2] = 0.0f;
  72         viewport.translate[3] = 0.0f;
  73         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
  74
  75         /* Upload vertices. The hw rectangle has only 3 vertices,
  76          * I guess the 4th one is derived from the first 3.
  77          * The vertex specification should match u_blitter's vertex element state. */
  78         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
  79         vb[0] = x1;
  80         vb[1] = y1;
  81         vb[2] = depth;
  82         vb[3] = 1;
  83
  84         vb[8] = x1;
  85         vb[9] = y2;
  86         vb[10] = depth;
  87         vb[11] = 1;
  88
  89         vb[16] = x2;
  90         vb[17] = y1;
  91         vb[18] = depth;
  92         vb[19] = 1;
  93
  94         if (attrib) {
  95                 memcpy(vb+4, attrib->f, sizeof(float)*4);
  96                 memcpy(vb+12, attrib->f, sizeof(float)*4);
  97                 memcpy(vb+20, attrib->f, sizeof(float)*4);
  98         }
  99
 100         /* draw */
 101         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 102                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 103         pipe_resource_reference(&buf, NULL);
 104 }
 105
 106 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
 107 {
 108         /* The number of dwords we already used in the DMA so far. */
 109         num_dw += ctx->rings.dma.cs->cdw;
 110         /* Flush if there's not enough space. */
 111         if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
 112                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 113         }
 114 }
 115
 116 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 117 {
 118 }
 119
 120 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 121 {
 122         /* Disable render condition. */
 123         ctx->saved_render_cond = NULL;
 124         ctx->saved_render_cond_cond = FALSE;
 125         ctx->saved_render_cond_mode = 0;
 126         if (ctx->current_render_cond) {
 127                 ctx->saved_render_cond = ctx->current_render_cond;
 128                 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
 129                 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
 130                 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
 131         }
 132
 133         /* suspend queries */
 134         ctx->nontimer_queries_suspended = false;
 135         if (ctx->num_cs_dw_nontimer_queries_suspend) {
 136                 r600_suspend_nontimer_queries(ctx);
 137                 ctx->nontimer_queries_suspended = true;
 138         }
 139
 140         ctx->streamout.suspended = false;
 141         if (ctx->streamout.begin_emitted) {
 142                 r600_emit_streamout_end(ctx);
 143                 ctx->streamout.suspended = true;
 144         }
 145 }
 146
 147 void r600_postflush_resume_features(struct r600_common_context *ctx)
 148 {
 149         if (ctx->streamout.suspended) {
 150                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 151                 r600_streamout_buffers_dirty(ctx);
 152         }
 153
 154         /* resume queries */
 155         if (ctx->nontimer_queries_suspended) {
 156                 r600_resume_nontimer_queries(ctx);
 157         }
 158
 159         /* Re-enable render condition. */
 160         if (ctx->saved_render_cond) {
 161                 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
 162                                           ctx->saved_render_cond_cond,
 163                                           ctx->saved_render_cond_mode);
 164         }
 165 }
 166
 167 static void r600_flush_from_st(struct pipe_context *ctx,
 168                                struct pipe_fence_handle **fence,
 169                                unsigned flags)
 170 {
 171         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 172         unsigned rflags = 0;
 173
 174         if (flags & PIPE_FLUSH_END_OF_FRAME)
 175                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 176
 177         if (rctx->rings.dma.cs) {
 178                 rctx->rings.dma.flush(rctx, rflags, NULL);
 179         }
 180         rctx->rings.gfx.flush(rctx, rflags, fence);
 181 }
 182
 183 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 184                                 struct pipe_fence_handle **fence)
 185 {
 186         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 187         struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
 188
 189         if (!cs->cdw) {
 190                 return;
 191         }
 192
 193         rctx->rings.dma.flushing = true;
 194         rctx->ws->cs_flush(cs, flags, fence, 0);
 195         rctx->rings.dma.flushing = false;
 196 }
 197
 198 bool r600_common_context_init(struct r600_common_context *rctx,
 199                               struct r600_common_screen *rscreen)
 200 {
 201         util_slab_create(&rctx->pool_transfers,
 202                          sizeof(struct r600_transfer), 64,
 203                          UTIL_SLAB_SINGLETHREADED);
 204
 205         rctx->screen = rscreen;
 206         rctx->ws = rscreen->ws;
 207         rctx->family = rscreen->family;
 208         rctx->chip_class = rscreen->chip_class;
 209
 210         if (rscreen->family == CHIP_HAWAII)
 211                 rctx->max_db = 16;
 212         else if (rscreen->chip_class >= EVERGREEN)
 213                 rctx->max_db = 8;
 214         else
 215                 rctx->max_db = 4;
 216
 217         rctx->b.transfer_map = u_transfer_map_vtbl;
 218         rctx->b.transfer_flush_region = u_default_transfer_flush_region;
 219         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 220         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 221         rctx->b.memory_barrier = r600_memory_barrier;
 222         rctx->b.flush = r600_flush_from_st;
 223
 224         LIST_INITHEAD(&rctx->texture_buffers);
 225
 226         r600_init_context_texture_functions(rctx);
 227         r600_streamout_init(rctx);
 228         r600_query_init(rctx);
 229         cayman_init_msaa(&rctx->b);
 230
 231         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 232                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 233         if (!rctx->allocator_so_filled_size)
 234                 return false;
 235
 236         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 237                                         PIPE_BIND_INDEX_BUFFER |
 238                                         PIPE_BIND_CONSTANT_BUFFER);
 239         if (!rctx->uploader)
 240                 return false;
 241
 242         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 243                 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
 244                                                          r600_flush_dma_ring,
 245                                                          rctx, NULL);
 246                 rctx->rings.dma.flush = r600_flush_dma_ring;
 247         }
 248
 249         return true;
 250 }
 251
 252 void r600_common_context_cleanup(struct r600_common_context *rctx)
 253 {
 254         if (rctx->rings.gfx.cs) {
 255                 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
 256         }
 257         if (rctx->rings.dma.cs) {
 258                 rctx->ws->cs_destroy(rctx->rings.dma.cs);
 259         }
 260
 261         if (rctx->uploader) {
 262                 u_upload_destroy(rctx->uploader);
 263         }
 264
 265         util_slab_destroy(&rctx->pool_transfers);
 266
 267         if (rctx->allocator_so_filled_size) {
 268                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 269         }
 270 }
 271
 272 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 273 {
 274         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 275         struct r600_resource *rr = (struct r600_resource *)r;
 276
 277         if (r == NULL) {
 278                 return;
 279         }
 280
 281         /*
 282          * The idea is to compute a gross estimate of memory requirement of
 283          * each draw call. After each draw call, memory will be precisely
 284          * accounted. So the uncertainty is only on the current draw call.
 285          * In practice this gave very good estimate (+/- 10% of the target
 286          * memory limit).
 287          */
 288         if (rr->domains & RADEON_DOMAIN_GTT) {
 289                 rctx->gtt += rr->buf->size;
 290         }
 291         if (rr->domains & RADEON_DOMAIN_VRAM) {
 292                 rctx->vram += rr->buf->size;
 293         }
 294 }
 295
 296 /*
 297  * pipe_screen
 298  */
 299
 300 static const struct debug_named_value common_debug_options[] = {
 301         /* logging */
 302         { "tex", DBG_TEX, "Print texture info" },
 303         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 304         { "compute", DBG_COMPUTE, "Print compute info" },
 305         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 306         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 307
 308         /* shaders */
 309         { "fs", DBG_FS, "Print fetch shaders" },
 310         { "vs", DBG_VS, "Print vertex shaders" },
 311         { "gs", DBG_GS, "Print geometry shaders" },
 312         { "ps", DBG_PS, "Print pixel shaders" },
 313         { "cs", DBG_CS, "Print compute shaders" },
 314
 315         /* features */
 316         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 317         { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
 318         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 319         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 320         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 321         { "notiling", DBG_NO_TILING, "Disable tiling" },
 322         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 323
 324         DEBUG_NAMED_VALUE_END /* must be last */
 325 };
 326
 327 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 328 {
 329         return "X.Org";
 330 }
 331
 332 static const char* r600_get_name(struct pipe_screen* pscreen)
 333 {
 334         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 335
 336         switch (rscreen->family) {
 337         case CHIP_R600: return "AMD R600";
 338         case CHIP_RV610: return "AMD RV610";
 339         case CHIP_RV630: return "AMD RV630";
 340         case CHIP_RV670: return "AMD RV670";
 341         case CHIP_RV620: return "AMD RV620";
 342         case CHIP_RV635: return "AMD RV635";
 343         case CHIP_RS780: return "AMD RS780";
 344         case CHIP_RS880: return "AMD RS880";
 345         case CHIP_RV770: return "AMD RV770";
 346         case CHIP_RV730: return "AMD RV730";
 347         case CHIP_RV710: return "AMD RV710";
 348         case CHIP_RV740: return "AMD RV740";
 349         case CHIP_CEDAR: return "AMD CEDAR";
 350         case CHIP_REDWOOD: return "AMD REDWOOD";
 351         case CHIP_JUNIPER: return "AMD JUNIPER";
 352         case CHIP_CYPRESS: return "AMD CYPRESS";
 353         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 354         case CHIP_PALM: return "AMD PALM";
 355         case CHIP_SUMO: return "AMD SUMO";
 356         case CHIP_SUMO2: return "AMD SUMO2";
 357         case CHIP_BARTS: return "AMD BARTS";
 358         case CHIP_TURKS: return "AMD TURKS";
 359         case CHIP_CAICOS: return "AMD CAICOS";
 360         case CHIP_CAYMAN: return "AMD CAYMAN";
 361         case CHIP_ARUBA: return "AMD ARUBA";
 362         case CHIP_TAHITI: return "AMD TAHITI";
 363         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 364         case CHIP_VERDE: return "AMD CAPE VERDE";
 365         case CHIP_OLAND: return "AMD OLAND";
 366         case CHIP_HAINAN: return "AMD HAINAN";
 367         case CHIP_BONAIRE: return "AMD BONAIRE";
 368         case CHIP_KAVERI: return "AMD KAVERI";
 369         case CHIP_KABINI: return "AMD KABINI";
 370         case CHIP_HAWAII: return "AMD HAWAII";
 371         case CHIP_MULLINS: return "AMD MULLINS";
 372         default: return "AMD unknown";
 373         }
 374 }
 375
 376 static float r600_get_paramf(struct pipe_screen* pscreen,
 377                              enum pipe_capf param)
 378 {
 379         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 380
 381         switch (param) {
 382         case PIPE_CAPF_MAX_LINE_WIDTH:
 383         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 384         case PIPE_CAPF_MAX_POINT_WIDTH:
 385         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 386                 if (rscreen->family >= CHIP_CEDAR)
 387                         return 16384.0f;
 388                 else
 389                         return 8192.0f;
 390         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 391                 return 16.0f;
 392         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 393                 return 16.0f;
 394         case PIPE_CAPF_GUARD_BAND_LEFT:
 395         case PIPE_CAPF_GUARD_BAND_TOP:
 396         case PIPE_CAPF_GUARD_BAND_RIGHT:
 397         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 398                 return 0.0f;
 399         }
 400         return 0.0f;
 401 }
 402
 403 static int r600_get_video_param(struct pipe_screen *screen,
 404                                 enum pipe_video_profile profile,
 405                                 enum pipe_video_entrypoint entrypoint,
 406                                 enum pipe_video_cap param)
 407 {
 408         switch (param) {
 409         case PIPE_VIDEO_CAP_SUPPORTED:
 410                 return vl_profile_supported(screen, profile, entrypoint);
 411         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 412                 return 1;
 413         case PIPE_VIDEO_CAP_MAX_WIDTH:
 414         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 415                 return vl_video_buffer_max_size(screen);
 416         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 417                 return PIPE_FORMAT_NV12;
 418         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 419                 return false;
 420         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 421                 return false;
 422         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 423                 return true;
 424         case PIPE_VIDEO_CAP_MAX_LEVEL:
 425                 return vl_level_supported(screen, profile);
 426         default:
 427                 return 0;
 428         }
 429 }
 430
 431 const char *r600_get_llvm_processor_name(enum radeon_family family)
 432 {
 433         switch (family) {
 434         case CHIP_R600:
 435         case CHIP_RV630:
 436         case CHIP_RV635:
 437         case CHIP_RV670:
 438                 return "r600";
 439         case CHIP_RV610:
 440         case CHIP_RV620:
 441         case CHIP_RS780:
 442         case CHIP_RS880:
 443                 return "rs880";
 444         case CHIP_RV710:
 445                 return "rv710";
 446         case CHIP_RV730:
 447                 return "rv730";
 448         case CHIP_RV740:
 449         case CHIP_RV770:
 450                 return "rv770";
 451         case CHIP_PALM:
 452         case CHIP_CEDAR:
 453                 return "cedar";
 454         case CHIP_SUMO:
 455         case CHIP_SUMO2:
 456                 return "sumo";
 457         case CHIP_REDWOOD:
 458                 return "redwood";
 459         case CHIP_JUNIPER:
 460                 return "juniper";
 461         case CHIP_HEMLOCK:
 462         case CHIP_CYPRESS:
 463                 return "cypress";
 464         case CHIP_BARTS:
 465                 return "barts";
 466         case CHIP_TURKS:
 467                 return "turks";
 468         case CHIP_CAICOS:
 469                 return "caicos";
 470         case CHIP_CAYMAN:
 471         case CHIP_ARUBA:
 472                 return "cayman";
 473
 474         case CHIP_TAHITI: return "tahiti";
 475         case CHIP_PITCAIRN: return "pitcairn";
 476         case CHIP_VERDE: return "verde";
 477         case CHIP_OLAND: return "oland";
 478         case CHIP_HAINAN: return "hainan";
 479         case CHIP_BONAIRE: return "bonaire";
 480         case CHIP_KABINI: return "kabini";
 481         case CHIP_KAVERI: return "kaveri";
 482         case CHIP_HAWAII: return "hawaii";
 483         case CHIP_MULLINS:
 484 #if HAVE_LLVM >= 0x0305
 485                 return "mullins";
 486 #else
 487                 return "kabini";
 488 #endif
 489         default: return "";
 490         }
 491 }
 492
 493 static int r600_get_compute_param(struct pipe_screen *screen,
 494         enum pipe_compute_cap param,
 495         void *ret)
 496 {
 497         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 498
 499         //TODO: select these params by asic
 500         switch (param) {
 501         case PIPE_COMPUTE_CAP_IR_TARGET: {
 502                 const char *gpu;
 503                 switch(rscreen->family) {
 504                 /* Clang < 3.6 is missing Hainan in its list of
 505                  * GPUs, so we need to use the name of a similar GPU.
 506                  */
 507 #if HAVE_LLVM < 0x0306
 508                 case CHIP_HAINAN:
 509                         gpu = "oland";
 510                         break;
 511 #endif
 512                 default:
 513                         gpu = r600_get_llvm_processor_name(rscreen->family);
 514                         break;
 515                 }
 516                 if (ret) {
 517                         sprintf(ret, "%s-r600--", gpu);
 518                 }
 519                 return (8 + strlen(gpu)) * sizeof(char);
 520         }
 521         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 522                 if (ret) {
 523                         uint64_t *grid_dimension = ret;
 524                         grid_dimension[0] = 3;
 525                 }
 526                 return 1 * sizeof(uint64_t);
 527
 528         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 529                 if (ret) {
 530                         uint64_t *grid_size = ret;
 531                         grid_size[0] = 65535;
 532                         grid_size[1] = 65535;
 533                         grid_size[2] = 1;
 534                 }
 535                 return 3 * sizeof(uint64_t) ;
 536
 537         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 538                 if (ret) {
 539                         uint64_t *block_size = ret;
 540                         block_size[0] = 256;
 541                         block_size[1] = 256;
 542                         block_size[2] = 256;
 543                 }
 544                 return 3 * sizeof(uint64_t);
 545
 546         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 547                 if (ret) {
 548                         uint64_t *max_threads_per_block = ret;
 549                         *max_threads_per_block = 256;
 550                 }
 551                 return sizeof(uint64_t);
 552
 553         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 554                 if (ret) {
 555                         uint64_t *max_global_size = ret;
 556                         uint64_t max_mem_alloc_size;
 557
 558                         r600_get_compute_param(screen,
 559                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 560                                 &max_mem_alloc_size);
 561
 562                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 563                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 564                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 565                          * make sure we never report more than
 566                          * 4 * MAX_MEM_ALLOC_SIZE.
 567                          */
 568                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 569                                 rscreen->info.gart_size +
 570                                 rscreen->info.vram_size);
 571                 }
 572                 return sizeof(uint64_t);
 573
 574         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 575                 if (ret) {
 576                         uint64_t *max_local_size = ret;
 577                         /* Value reported by the closed source driver. */
 578                         *max_local_size = 32768;
 579                 }
 580                 return sizeof(uint64_t);
 581
 582         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 583                 if (ret) {
 584                         uint64_t *max_input_size = ret;
 585                         /* Value reported by the closed source driver. */
 586                         *max_input_size = 1024;
 587                 }
 588                 return sizeof(uint64_t);
 589
 590         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 591                 if (ret) {
 592                         uint64_t max_global_size;
 593                         uint64_t *max_mem_alloc_size = ret;
 594
 595                         /* XXX: The limit in older kernels is 256 MB.  We
 596                          * should add a query here for newer kernels.
 597                          */
 598                         *max_mem_alloc_size = 256 * 1024 * 1024;
 599                 }
 600                 return sizeof(uint64_t);
 601
 602         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 603                 if (ret) {
 604                         uint32_t *max_clock_frequency = ret;
 605                         *max_clock_frequency = rscreen->info.max_sclk;
 606                 }
 607                 return sizeof(uint32_t);
 608
 609         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 610                 if (ret) {
 611                         uint32_t *max_compute_units = ret;
 612                         *max_compute_units = MAX2(rscreen->info.max_compute_units, 1);
 613                 }
 614                 return sizeof(uint32_t);
 615
 616         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 617                 if (ret) {
 618                         uint32_t *images_supported = ret;
 619                         *images_supported = 0;
 620                 }
 621                 return sizeof(uint32_t);
 622         }
 623
 624         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 625         return 0;
 626 }
 627
 628 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 629 {
 630         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 631
 632         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 633                         rscreen->info.r600_clock_crystal_freq;
 634 }
 635
 636 static int r600_get_driver_query_info(struct pipe_screen *screen,
 637                                       unsigned index,
 638                                       struct pipe_driver_query_info *info)
 639 {
 640         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 641         struct pipe_driver_query_info list[] = {
 642                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 643                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->info.vram_size, TRUE},
 644                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->info.gart_size, TRUE},
 645                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE},
 646                 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, 0, FALSE},
 647                 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, 0, TRUE},
 648                 {"VRAM-usage", R600_QUERY_VRAM_USAGE, rscreen->info.vram_size, TRUE},
 649                 {"GTT-usage", R600_QUERY_GTT_USAGE, rscreen->info.gart_size, TRUE},
 650         };
 651
 652         if (!info)
 653                 return Elements(list);
 654
 655         if (index >= Elements(list))
 656                 return 0;
 657
 658         *info = list[index];
 659         return 1;
 660 }
 661
 662 static void r600_fence_reference(struct pipe_screen *screen,
 663                                  struct pipe_fence_handle **ptr,
 664                                  struct pipe_fence_handle *fence)
 665 {
 666         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 667
 668         rws->fence_reference(ptr, fence);
 669 }
 670
 671 static boolean r600_fence_signalled(struct pipe_screen *screen,
 672                                     struct pipe_fence_handle *fence)
 673 {
 674         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 675
 676         return rws->fence_wait(rws, fence, 0);
 677 }
 678
 679 static boolean r600_fence_finish(struct pipe_screen *screen,
 680                                  struct pipe_fence_handle *fence,
 681                                  uint64_t timeout)
 682 {
 683         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 684
 685         return rws->fence_wait(rws, fence, timeout);
 686 }
 687
 688 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 689                                   uint32_t tiling_config)
 690 {
 691         switch ((tiling_config & 0xe) >> 1) {
 692         case 0:
 693                 rscreen->tiling_info.num_channels = 1;
 694                 break;
 695         case 1:
 696                 rscreen->tiling_info.num_channels = 2;
 697                 break;
 698         case 2:
 699                 rscreen->tiling_info.num_channels = 4;
 700                 break;
 701         case 3:
 702                 rscreen->tiling_info.num_channels = 8;
 703                 break;
 704         default:
 705                 return false;
 706         }
 707
 708         switch ((tiling_config & 0x30) >> 4) {
 709         case 0:
 710                 rscreen->tiling_info.num_banks = 4;
 711                 break;
 712         case 1:
 713                 rscreen->tiling_info.num_banks = 8;
 714                 break;
 715         default:
 716                 return false;
 717
 718         }
 719         switch ((tiling_config & 0xc0) >> 6) {
 720         case 0:
 721                 rscreen->tiling_info.group_bytes = 256;
 722                 break;
 723         case 1:
 724                 rscreen->tiling_info.group_bytes = 512;
 725                 break;
 726         default:
 727                 return false;
 728         }
 729         return true;
 730 }
 731
 732 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 733                                        uint32_t tiling_config)
 734 {
 735         switch (tiling_config & 0xf) {
 736         case 0:
 737                 rscreen->tiling_info.num_channels = 1;
 738                 break;
 739         case 1:
 740                 rscreen->tiling_info.num_channels = 2;
 741                 break;
 742         case 2:
 743                 rscreen->tiling_info.num_channels = 4;
 744                 break;
 745         case 3:
 746                 rscreen->tiling_info.num_channels = 8;
 747                 break;
 748         default:
 749                 return false;
 750         }
 751
 752         switch ((tiling_config & 0xf0) >> 4) {
 753         case 0:
 754                 rscreen->tiling_info.num_banks = 4;
 755                 break;
 756         case 1:
 757                 rscreen->tiling_info.num_banks = 8;
 758                 break;
 759         case 2:
 760                 rscreen->tiling_info.num_banks = 16;
 761                 break;
 762         default:
 763                 return false;
 764         }
 765
 766         switch ((tiling_config & 0xf00) >> 8) {
 767         case 0:
 768                 rscreen->tiling_info.group_bytes = 256;
 769                 break;
 770         case 1:
 771                 rscreen->tiling_info.group_bytes = 512;
 772                 break;
 773         default:
 774                 return false;
 775         }
 776         return true;
 777 }
 778
 779 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 780 {
 781         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 782
 783         /* set default group bytes, overridden by tiling info ioctl */
 784         if (rscreen->chip_class <= R700) {
 785                 rscreen->tiling_info.group_bytes = 256;
 786         } else {
 787                 rscreen->tiling_info.group_bytes = 512;
 788         }
 789
 790         if (!tiling_config)
 791                 return true;
 792
 793         if (rscreen->chip_class <= R700) {
 794                 return r600_interpret_tiling(rscreen, tiling_config);
 795         } else {
 796                 return evergreen_interpret_tiling(rscreen, tiling_config);
 797         }
 798 }
 799
 800 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 801                                                   const struct pipe_resource *templ)
 802 {
 803         if (templ->target == PIPE_BUFFER) {
 804                 return r600_buffer_create(screen, templ, 4096);
 805         } else {
 806                 return r600_texture_create(screen, templ);
 807         }
 808 }
 809
 810 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 811                              struct radeon_winsys *ws)
 812 {
 813         ws->query_info(ws, &rscreen->info);
 814
 815         rscreen->b.get_name = r600_get_name;
 816         rscreen->b.get_vendor = r600_get_vendor;
 817         rscreen->b.get_compute_param = r600_get_compute_param;
 818         rscreen->b.get_paramf = r600_get_paramf;
 819         rscreen->b.get_driver_query_info = r600_get_driver_query_info;
 820         rscreen->b.get_timestamp = r600_get_timestamp;
 821         rscreen->b.fence_finish = r600_fence_finish;
 822         rscreen->b.fence_reference = r600_fence_reference;
 823         rscreen->b.fence_signalled = r600_fence_signalled;
 824         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 825
 826         if (rscreen->info.has_uvd) {
 827                 rscreen->b.get_video_param = rvid_get_video_param;
 828                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 829         } else {
 830                 rscreen->b.get_video_param = r600_get_video_param;
 831                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 832         }
 833
 834         r600_init_screen_texture_functions(rscreen);
 835
 836         rscreen->ws = ws;
 837         rscreen->family = rscreen->info.family;
 838         rscreen->chip_class = rscreen->info.chip_class;
 839         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 840
 841         if (!r600_init_tiling(rscreen)) {
 842                 return false;
 843         }
 844         util_format_s3tc_init();
 845         pipe_mutex_init(rscreen->aux_context_lock);
 846
 847         if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
 848                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 849                                                                                 PIPE_BIND_CUSTOM,
 850                                                                                 PIPE_USAGE_STAGING,
 851                                                                                 4096);
 852                 if (rscreen->trace_bo) {
 853                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 854                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 855                 }
 856         }
 857
 858         return true;
 859 }
 860
 861 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 862 {
 863         pipe_mutex_destroy(rscreen->aux_context_lock);
 864         rscreen->aux_context->destroy(rscreen->aux_context);
 865
 866         if (rscreen->trace_bo) {
 867                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 868                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 869         }
 870
 871         rscreen->ws->destroy(rscreen->ws);
 872         FREE(rscreen);
 873 }
 874
 875 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 876 {
 877         struct tgsi_parse_context parse;
 878
 879         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 880                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 881                 return ~0;
 882         }
 883         return parse.FullHeader.Processor.Processor;
 884 }
 885
 886 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 887                           const struct tgsi_token *tokens)
 888 {
 889         /* Compute shader don't have tgsi_tokens */
 890         if (!tokens)
 891                 return (rscreen->debug_flags & DBG_CS) != 0;
 892
 893         switch (tgsi_get_processor_type(tokens)) {
 894         case TGSI_PROCESSOR_VERTEX:
 895                 return (rscreen->debug_flags & DBG_VS) != 0;
 896         case TGSI_PROCESSOR_GEOMETRY:
 897                 return (rscreen->debug_flags & DBG_GS) != 0;
 898         case TGSI_PROCESSOR_FRAGMENT:
 899                 return (rscreen->debug_flags & DBG_PS) != 0;
 900         case TGSI_PROCESSOR_COMPUTE:
 901                 return (rscreen->debug_flags & DBG_CS) != 0;
 902         default:
 903                 return false;
 904         }
 905 }
 906
 907 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 908                               unsigned offset, unsigned size, unsigned value)
 909 {
 910         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 911
 912         pipe_mutex_lock(rscreen->aux_context_lock);
 913         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 914         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 915         pipe_mutex_unlock(rscreen->aux_context_lock);
 916 }