projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: move GFX/DMA flushing from add_to_buffer_list to need_cs_space
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "os/os_time.h"
35 #include "vl/vl_decoder.h"
36 #include "vl/vl_video_buffer.h"
37 #include "radeon/radeon_video.h"
38 #include <inttypes.h>
39
40 #ifndef HAVE_LLVM
41 #define HAVE_LLVM 0
42 #endif
43
44 struct r600_multi_fence {
45 struct pipe_reference reference;
46 struct pipe_fence_handle *gfx;
47 struct pipe_fence_handle *sdma;
48 };
49
50 /*
51 * pipe_context
52 */
53
54 void r600_draw_rectangle(struct blitter_context *blitter,
55 int x1, int y1, int x2, int y2, float depth,
56 enum blitter_attrib_type type,
57 const union pipe_color_union *attrib)
58 {
59 struct r600_common_context *rctx =
60 (struct r600_common_context*)util_blitter_get_pipe(blitter);
61 struct pipe_viewport_state viewport;
62 struct pipe_resource *buf = NULL;
63 unsigned offset = 0;
64 float *vb;
65
66 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
67 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
68 return;
69 }
70
71 /* Some operations (like color resolve on r6xx) don't work
72 * with the conventional primitive types.
73 * One that works is PT_RECTLIST, which we use here. */
74
75 /* setup viewport */
76 viewport.scale[0] = 1.0f;
77 viewport.scale[1] = 1.0f;
78 viewport.scale[2] = 1.0f;
79 viewport.translate[0] = 0.0f;
80 viewport.translate[1] = 0.0f;
81 viewport.translate[2] = 0.0f;
82 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
83
84 /* Upload vertices. The hw rectangle has only 3 vertices,
85 * I guess the 4th one is derived from the first 3.
86 * The vertex specification should match u_blitter's vertex element state. */
87 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
88 if (!buf)
89 return;
90
91 vb[0] = x1;
92 vb[1] = y1;
93 vb[2] = depth;
94 vb[3] = 1;
95
96 vb[8] = x1;
97 vb[9] = y2;
98 vb[10] = depth;
99 vb[11] = 1;
100
101 vb[16] = x2;
102 vb[17] = y1;
103 vb[18] = depth;
104 vb[19] = 1;
105
106 if (attrib) {
107 memcpy(vb+4, attrib->f, sizeof(float)*4);
108 memcpy(vb+12, attrib->f, sizeof(float)*4);
109 memcpy(vb+20, attrib->f, sizeof(float)*4);
110 }
111
112 /* draw */
113 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
114 R600_PRIM_RECTANGLE_LIST, 3, 2);
115 pipe_resource_reference(&buf, NULL);
116 }
117
118 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
119 {
120 /* Flush the GFX IB if it's not empty. */
121 if (ctx->rings.gfx.cs->cdw > ctx->initial_gfx_cs_size)
122 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
123
124 /* Flush if there's not enough space. */
125 if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
126 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
127 assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
128 }
129 }
130
131 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
132 {
133 }
134
135 void r600_preflush_suspend_features(struct r600_common_context *ctx)
136 {
137 /* Disable render condition. */
138 ctx->saved_render_cond = NULL;
139 ctx->saved_render_cond_cond = FALSE;
140 ctx->saved_render_cond_mode = 0;
141 if (ctx->current_render_cond) {
142 ctx->saved_render_cond = ctx->current_render_cond;
143 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
144 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
145 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
146 }
147
148 /* suspend queries */
149 ctx->queries_suspended_for_flush = false;
150 if (ctx->num_cs_dw_nontimer_queries_suspend) {
151 r600_suspend_nontimer_queries(ctx);
152 r600_suspend_timer_queries(ctx);
153 ctx->queries_suspended_for_flush = true;
154 }
155
156 ctx->streamout.suspended = false;
157 if (ctx->streamout.begin_emitted) {
158 r600_emit_streamout_end(ctx);
159 ctx->streamout.suspended = true;
160 }
161 }
162
163 void r600_postflush_resume_features(struct r600_common_context *ctx)
164 {
165 if (ctx->streamout.suspended) {
166 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
167 r600_streamout_buffers_dirty(ctx);
168 }
169
170 /* resume queries */
171 if (ctx->queries_suspended_for_flush) {
172 r600_resume_nontimer_queries(ctx);
173 r600_resume_timer_queries(ctx);
174 }
175
176 /* Re-enable render condition. */
177 if (ctx->saved_render_cond) {
178 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
179 ctx->saved_render_cond_cond,
180 ctx->saved_render_cond_mode);
181 }
182 }
183
184 static void r600_flush_from_st(struct pipe_context *ctx,
185 struct pipe_fence_handle **fence,
186 unsigned flags)
187 {
188 struct pipe_screen *screen = ctx->screen;
189 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
190 unsigned rflags = 0;
191 struct pipe_fence_handle *gfx_fence = NULL;
192 struct pipe_fence_handle *sdma_fence = NULL;
193
194 if (flags & PIPE_FLUSH_END_OF_FRAME)
195 rflags |= RADEON_FLUSH_END_OF_FRAME;
196
197 if (rctx->rings.dma.cs) {
198 rctx->rings.dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
199 }
200 rctx->rings.gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
201
202 /* Both engines can signal out of order, so we need to keep both fences. */
203 if (gfx_fence || sdma_fence) {
204 struct r600_multi_fence *multi_fence =
205 CALLOC_STRUCT(r600_multi_fence);
206 if (!multi_fence)
207 return;
208
209 multi_fence->reference.count = 1;
210 multi_fence->gfx = gfx_fence;
211 multi_fence->sdma = sdma_fence;
212
213 screen->fence_reference(screen, fence, NULL);
214 *fence = (struct pipe_fence_handle*)multi_fence;
215 }
216 }
217
218 static void r600_flush_dma_ring(void *ctx, unsigned flags,
219 struct pipe_fence_handle **fence)
220 {
221 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
222 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
223
224 if (!cs->cdw)
225 goto done;
226
227 rctx->rings.dma.flushing = true;
228 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
229 rctx->rings.dma.flushing = false;
230 done:
231 if (fence)
232 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
233 }
234
235 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
236 {
237 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
238 unsigned latest = rctx->ws->query_value(rctx->ws,
239 RADEON_GPU_RESET_COUNTER);
240
241 if (rctx->gpu_reset_counter == latest)
242 return PIPE_NO_RESET;
243
244 rctx->gpu_reset_counter = latest;
245 return PIPE_UNKNOWN_CONTEXT_RESET;
246 }
247
248 bool r600_common_context_init(struct r600_common_context *rctx,
249 struct r600_common_screen *rscreen)
250 {
251 util_slab_create(&rctx->pool_transfers,
252 sizeof(struct r600_transfer), 64,
253 UTIL_SLAB_SINGLETHREADED);
254
255 rctx->screen = rscreen;
256 rctx->ws = rscreen->ws;
257 rctx->family = rscreen->family;
258 rctx->chip_class = rscreen->chip_class;
259
260 if (rscreen->family == CHIP_HAWAII)
261 rctx->max_db = 16;
262 else if (rscreen->chip_class >= EVERGREEN)
263 rctx->max_db = 8;
264 else
265 rctx->max_db = 4;
266
267 rctx->b.transfer_map = u_transfer_map_vtbl;
268 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
269 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
270 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
271 rctx->b.memory_barrier = r600_memory_barrier;
272 rctx->b.flush = r600_flush_from_st;
273
274 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
275 rctx->b.get_device_reset_status = r600_get_reset_status;
276 rctx->gpu_reset_counter =
277 rctx->ws->query_value(rctx->ws,
278 RADEON_GPU_RESET_COUNTER);
279 }
280
281 LIST_INITHEAD(&rctx->texture_buffers);
282
283 r600_init_context_texture_functions(rctx);
284 r600_streamout_init(rctx);
285 r600_query_init(rctx);
286 cayman_init_msaa(&rctx->b);
287
288 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
289 0, PIPE_USAGE_DEFAULT, TRUE);
290 if (!rctx->allocator_so_filled_size)
291 return false;
292
293 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
294 PIPE_BIND_INDEX_BUFFER |
295 PIPE_BIND_CONSTANT_BUFFER);
296 if (!rctx->uploader)
297 return false;
298
299 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
300 if (!rctx->ctx)
301 return false;
302
303 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
304 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
305 r600_flush_dma_ring,
306 rctx, NULL);
307 rctx->rings.dma.flush = r600_flush_dma_ring;
308 }
309
310 return true;
311 }
312
313 void r600_common_context_cleanup(struct r600_common_context *rctx)
314 {
315 if (rctx->rings.gfx.cs)
316 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
317 if (rctx->rings.dma.cs)
318 rctx->ws->cs_destroy(rctx->rings.dma.cs);
319 if (rctx->ctx)
320 rctx->ws->ctx_destroy(rctx->ctx);
321
322 if (rctx->uploader) {
323 u_upload_destroy(rctx->uploader);
324 }
325
326 util_slab_destroy(&rctx->pool_transfers);
327
328 if (rctx->allocator_so_filled_size) {
329 u_suballocator_destroy(rctx->allocator_so_filled_size);
330 }
331 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
332 }
333
334 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
335 {
336 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
337 struct r600_resource *rr = (struct r600_resource *)r;
338
339 if (r == NULL) {
340 return;
341 }
342
343 /*
344 * The idea is to compute a gross estimate of memory requirement of
345 * each draw call. After each draw call, memory will be precisely
346 * accounted. So the uncertainty is only on the current draw call.
347 * In practice this gave very good estimate (+/- 10% of the target
348 * memory limit).
349 */
350 if (rr->domains & RADEON_DOMAIN_GTT) {
351 rctx->gtt += rr->buf->size;
352 }
353 if (rr->domains & RADEON_DOMAIN_VRAM) {
354 rctx->vram += rr->buf->size;
355 }
356 }
357
358 /*
359 * pipe_screen
360 */
361
362 static const struct debug_named_value common_debug_options[] = {
363 /* logging */
364 { "tex", DBG_TEX, "Print texture info" },
365 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
366 { "compute", DBG_COMPUTE, "Print compute info" },
367 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
368 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
369 { "info", DBG_INFO, "Print driver information" },
370
371 /* shaders */
372 { "fs", DBG_FS, "Print fetch shaders" },
373 { "vs", DBG_VS, "Print vertex shaders" },
374 { "gs", DBG_GS, "Print geometry shaders" },
375 { "ps", DBG_PS, "Print pixel shaders" },
376 { "cs", DBG_CS, "Print compute shaders" },
377 { "tcs", DBG_TCS, "Print tessellation control shaders" },
378 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
379 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
380 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
381 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
382
383 /* features */
384 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
385 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
386 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
387 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
388 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
389 { "notiling", DBG_NO_TILING, "Disable tiling" },
390 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
391 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
392 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
393 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
394 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
395 { "nodcc", DBG_NO_DCC, "Disable DCC." },
396 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
397
398 DEBUG_NAMED_VALUE_END /* must be last */
399 };
400
401 static const char* r600_get_vendor(struct pipe_screen* pscreen)
402 {
403 return "X.Org";
404 }
405
406 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
407 {
408 return "AMD";
409 }
410
411 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
412 {
413 switch (rscreen->info.family) {
414 case CHIP_R600: return "AMD R600";
415 case CHIP_RV610: return "AMD RV610";
416 case CHIP_RV630: return "AMD RV630";
417 case CHIP_RV670: return "AMD RV670";
418 case CHIP_RV620: return "AMD RV620";
419 case CHIP_RV635: return "AMD RV635";
420 case CHIP_RS780: return "AMD RS780";
421 case CHIP_RS880: return "AMD RS880";
422 case CHIP_RV770: return "AMD RV770";
423 case CHIP_RV730: return "AMD RV730";
424 case CHIP_RV710: return "AMD RV710";
425 case CHIP_RV740: return "AMD RV740";
426 case CHIP_CEDAR: return "AMD CEDAR";
427 case CHIP_REDWOOD: return "AMD REDWOOD";
428 case CHIP_JUNIPER: return "AMD JUNIPER";
429 case CHIP_CYPRESS: return "AMD CYPRESS";
430 case CHIP_HEMLOCK: return "AMD HEMLOCK";
431 case CHIP_PALM: return "AMD PALM";
432 case CHIP_SUMO: return "AMD SUMO";
433 case CHIP_SUMO2: return "AMD SUMO2";
434 case CHIP_BARTS: return "AMD BARTS";
435 case CHIP_TURKS: return "AMD TURKS";
436 case CHIP_CAICOS: return "AMD CAICOS";
437 case CHIP_CAYMAN: return "AMD CAYMAN";
438 case CHIP_ARUBA: return "AMD ARUBA";
439 case CHIP_TAHITI: return "AMD TAHITI";
440 case CHIP_PITCAIRN: return "AMD PITCAIRN";
441 case CHIP_VERDE: return "AMD CAPE VERDE";
442 case CHIP_OLAND: return "AMD OLAND";
443 case CHIP_HAINAN: return "AMD HAINAN";
444 case CHIP_BONAIRE: return "AMD BONAIRE";
445 case CHIP_KAVERI: return "AMD KAVERI";
446 case CHIP_KABINI: return "AMD KABINI";
447 case CHIP_HAWAII: return "AMD HAWAII";
448 case CHIP_MULLINS: return "AMD MULLINS";
449 case CHIP_TONGA: return "AMD TONGA";
450 case CHIP_ICELAND: return "AMD ICELAND";
451 case CHIP_CARRIZO: return "AMD CARRIZO";
452 case CHIP_FIJI: return "AMD FIJI";
453 case CHIP_STONEY: return "AMD STONEY";
454 default: return "AMD unknown";
455 }
456 }
457
458 static const char* r600_get_name(struct pipe_screen* pscreen)
459 {
460 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
461
462 return rscreen->renderer_string;
463 }
464
465 static float r600_get_paramf(struct pipe_screen* pscreen,
466 enum pipe_capf param)
467 {
468 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
469
470 switch (param) {
471 case PIPE_CAPF_MAX_LINE_WIDTH:
472 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
473 case PIPE_CAPF_MAX_POINT_WIDTH:
474 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
475 if (rscreen->family >= CHIP_CEDAR)
476 return 16384.0f;
477 else
478 return 8192.0f;
479 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
480 return 16.0f;
481 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
482 return 16.0f;
483 case PIPE_CAPF_GUARD_BAND_LEFT:
484 case PIPE_CAPF_GUARD_BAND_TOP:
485 case PIPE_CAPF_GUARD_BAND_RIGHT:
486 case PIPE_CAPF_GUARD_BAND_BOTTOM:
487 return 0.0f;
488 }
489 return 0.0f;
490 }
491
492 static int r600_get_video_param(struct pipe_screen *screen,
493 enum pipe_video_profile profile,
494 enum pipe_video_entrypoint entrypoint,
495 enum pipe_video_cap param)
496 {
497 switch (param) {
498 case PIPE_VIDEO_CAP_SUPPORTED:
499 return vl_profile_supported(screen, profile, entrypoint);
500 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
501 return 1;
502 case PIPE_VIDEO_CAP_MAX_WIDTH:
503 case PIPE_VIDEO_CAP_MAX_HEIGHT:
504 return vl_video_buffer_max_size(screen);
505 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
506 return PIPE_FORMAT_NV12;
507 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
508 return false;
509 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
510 return false;
511 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
512 return true;
513 case PIPE_VIDEO_CAP_MAX_LEVEL:
514 return vl_level_supported(screen, profile);
515 default:
516 return 0;
517 }
518 }
519
520 const char *r600_get_llvm_processor_name(enum radeon_family family)
521 {
522 switch (family) {
523 case CHIP_R600:
524 case CHIP_RV630:
525 case CHIP_RV635:
526 case CHIP_RV670:
527 return "r600";
528 case CHIP_RV610:
529 case CHIP_RV620:
530 case CHIP_RS780:
531 case CHIP_RS880:
532 return "rs880";
533 case CHIP_RV710:
534 return "rv710";
535 case CHIP_RV730:
536 return "rv730";
537 case CHIP_RV740:
538 case CHIP_RV770:
539 return "rv770";
540 case CHIP_PALM:
541 case CHIP_CEDAR:
542 return "cedar";
543 case CHIP_SUMO:
544 case CHIP_SUMO2:
545 return "sumo";
546 case CHIP_REDWOOD:
547 return "redwood";
548 case CHIP_JUNIPER:
549 return "juniper";
550 case CHIP_HEMLOCK:
551 case CHIP_CYPRESS:
552 return "cypress";
553 case CHIP_BARTS:
554 return "barts";
555 case CHIP_TURKS:
556 return "turks";
557 case CHIP_CAICOS:
558 return "caicos";
559 case CHIP_CAYMAN:
560 case CHIP_ARUBA:
561 return "cayman";
562
563 case CHIP_TAHITI: return "tahiti";
564 case CHIP_PITCAIRN: return "pitcairn";
565 case CHIP_VERDE: return "verde";
566 case CHIP_OLAND: return "oland";
567 case CHIP_HAINAN: return "hainan";
568 case CHIP_BONAIRE: return "bonaire";
569 case CHIP_KABINI: return "kabini";
570 case CHIP_KAVERI: return "kaveri";
571 case CHIP_HAWAII: return "hawaii";
572 case CHIP_MULLINS:
573 return "mullins";
574 case CHIP_TONGA: return "tonga";
575 case CHIP_ICELAND: return "iceland";
576 case CHIP_CARRIZO: return "carrizo";
577 case CHIP_FIJI: return "fiji";
578 #if HAVE_LLVM <= 0x0307
579 case CHIP_STONEY: return "carrizo";
580 #else
581 case CHIP_STONEY: return "stoney";
582 #endif
583 default: return "";
584 }
585 }
586
587 static int r600_get_compute_param(struct pipe_screen *screen,
588 enum pipe_compute_cap param,
589 void *ret)
590 {
591 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
592
593 //TODO: select these params by asic
594 switch (param) {
595 case PIPE_COMPUTE_CAP_IR_TARGET: {
596 const char *gpu;
597 const char *triple;
598 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
599 triple = "r600--";
600 } else {
601 triple = "amdgcn--";
602 }
603 switch(rscreen->family) {
604 /* Clang < 3.6 is missing Hainan in its list of
605 * GPUs, so we need to use the name of a similar GPU.
606 */
607 #if HAVE_LLVM < 0x0306
608 case CHIP_HAINAN:
609 gpu = "oland";
610 break;
611 #endif
612 default:
613 gpu = r600_get_llvm_processor_name(rscreen->family);
614 break;
615 }
616 if (ret) {
617 sprintf(ret, "%s-%s", gpu, triple);
618 }
619 /* +2 for dash and terminating NIL byte */
620 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
621 }
622 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
623 if (ret) {
624 uint64_t *grid_dimension = ret;
625 grid_dimension[0] = 3;
626 }
627 return 1 * sizeof(uint64_t);
628
629 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
630 if (ret) {
631 uint64_t *grid_size = ret;
632 grid_size[0] = 65535;
633 grid_size[1] = 65535;
634 grid_size[2] = 1;
635 }
636 return 3 * sizeof(uint64_t) ;
637
638 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
639 if (ret) {
640 uint64_t *block_size = ret;
641 block_size[0] = 256;
642 block_size[1] = 256;
643 block_size[2] = 256;
644 }
645 return 3 * sizeof(uint64_t);
646
647 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
648 if (ret) {
649 uint64_t *max_threads_per_block = ret;
650 *max_threads_per_block = 256;
651 }
652 return sizeof(uint64_t);
653
654 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
655 if (ret) {
656 uint64_t *max_global_size = ret;
657 uint64_t max_mem_alloc_size;
658
659 r600_get_compute_param(screen,
660 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
661 &max_mem_alloc_size);
662
663 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
664 * 1/4 of the MAX_GLOBAL_SIZE. Since the
665 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
666 * make sure we never report more than
667 * 4 * MAX_MEM_ALLOC_SIZE.
668 */
669 *max_global_size = MIN2(4 * max_mem_alloc_size,
670 rscreen->info.gart_size +
671 rscreen->info.vram_size);
672 }
673 return sizeof(uint64_t);
674
675 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
676 if (ret) {
677 uint64_t *max_local_size = ret;
678 /* Value reported by the closed source driver. */
679 *max_local_size = 32768;
680 }
681 return sizeof(uint64_t);
682
683 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
684 if (ret) {
685 uint64_t *max_input_size = ret;
686 /* Value reported by the closed source driver. */
687 *max_input_size = 1024;
688 }
689 return sizeof(uint64_t);
690
691 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
692 if (ret) {
693 uint64_t *max_mem_alloc_size = ret;
694
695 /* XXX: The limit in older kernels is 256 MB. We
696 * should add a query here for newer kernels.
697 */
698 *max_mem_alloc_size = 256 * 1024 * 1024;
699 }
700 return sizeof(uint64_t);
701
702 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
703 if (ret) {
704 uint32_t *max_clock_frequency = ret;
705 *max_clock_frequency = rscreen->info.max_sclk;
706 }
707 return sizeof(uint32_t);
708
709 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
710 if (ret) {
711 uint32_t *max_compute_units = ret;
712 *max_compute_units = rscreen->info.max_compute_units;
713 }
714 return sizeof(uint32_t);
715
716 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
717 if (ret) {
718 uint32_t *images_supported = ret;
719 *images_supported = 0;
720 }
721 return sizeof(uint32_t);
722 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
723 break; /* unused */
724 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
725 if (ret) {
726 uint32_t *subgroup_size = ret;
727 *subgroup_size = r600_wavefront_size(rscreen->family);
728 }
729 return sizeof(uint32_t);
730 }
731
732 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
733 return 0;
734 }
735
736 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
737 {
738 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
739
740 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
741 rscreen->info.r600_clock_crystal_freq;
742 }
743
744 static int r600_get_driver_query_info(struct pipe_screen *screen,
745 unsigned index,
746 struct pipe_driver_query_info *info)
747 {
748 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
749 struct pipe_driver_query_info list[] = {
750 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
751 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
752 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
753 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
754 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
755 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
756 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
757 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
758 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
759 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
760 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
761 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
762 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
763 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
764 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
765 {"temperature", R600_QUERY_GPU_TEMPERATURE, {125}},
766 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
767 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
768 };
769 unsigned num_queries;
770
771 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
772 num_queries = Elements(list);
773 else if (rscreen->info.drm_major == 3)
774 num_queries = Elements(list) - 3;
775 else
776 num_queries = Elements(list) - 4;
777
778 if (!info)
779 return num_queries;
780
781 if (index >= num_queries)
782 return 0;
783
784 *info = list[index];
785 return 1;
786 }
787
788 static void r600_fence_reference(struct pipe_screen *screen,
789 struct pipe_fence_handle **dst,
790 struct pipe_fence_handle *src)
791 {
792 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
793 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
794 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
795
796 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
797 ws->fence_reference(&(*rdst)->gfx, NULL);
798 ws->fence_reference(&(*rdst)->sdma, NULL);
799 FREE(*rdst);
800 }
801 *rdst = rsrc;
802 }
803
804 static boolean r600_fence_finish(struct pipe_screen *screen,
805 struct pipe_fence_handle *fence,
806 uint64_t timeout)
807 {
808 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
809 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
810 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
811
812 if (rfence->sdma) {
813 if (!rws->fence_wait(rws, rfence->sdma, timeout))
814 return false;
815
816 /* Recompute the timeout after waiting. */
817 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
818 int64_t time = os_time_get_nano();
819 timeout = abs_timeout > time ? abs_timeout - time : 0;
820 }
821 }
822
823 if (!rfence->gfx)
824 return true;
825
826 return rws->fence_wait(rws, rfence->gfx, timeout);
827 }
828
829 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
830 uint32_t tiling_config)
831 {
832 switch ((tiling_config & 0xe) >> 1) {
833 case 0:
834 rscreen->tiling_info.num_channels = 1;
835 break;
836 case 1:
837 rscreen->tiling_info.num_channels = 2;
838 break;
839 case 2:
840 rscreen->tiling_info.num_channels = 4;
841 break;
842 case 3:
843 rscreen->tiling_info.num_channels = 8;
844 break;
845 default:
846 return false;
847 }
848
849 switch ((tiling_config & 0x30) >> 4) {
850 case 0:
851 rscreen->tiling_info.num_banks = 4;
852 break;
853 case 1:
854 rscreen->tiling_info.num_banks = 8;
855 break;
856 default:
857 return false;
858
859 }
860 switch ((tiling_config & 0xc0) >> 6) {
861 case 0:
862 rscreen->tiling_info.group_bytes = 256;
863 break;
864 case 1:
865 rscreen->tiling_info.group_bytes = 512;
866 break;
867 default:
868 return false;
869 }
870 return true;
871 }
872
873 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
874 uint32_t tiling_config)
875 {
876 switch (tiling_config & 0xf) {
877 case 0:
878 rscreen->tiling_info.num_channels = 1;
879 break;
880 case 1:
881 rscreen->tiling_info.num_channels = 2;
882 break;
883 case 2:
884 rscreen->tiling_info.num_channels = 4;
885 break;
886 case 3:
887 rscreen->tiling_info.num_channels = 8;
888 break;
889 default:
890 return false;
891 }
892
893 switch ((tiling_config & 0xf0) >> 4) {
894 case 0:
895 rscreen->tiling_info.num_banks = 4;
896 break;
897 case 1:
898 rscreen->tiling_info.num_banks = 8;
899 break;
900 case 2:
901 rscreen->tiling_info.num_banks = 16;
902 break;
903 default:
904 return false;
905 }
906
907 switch ((tiling_config & 0xf00) >> 8) {
908 case 0:
909 rscreen->tiling_info.group_bytes = 256;
910 break;
911 case 1:
912 rscreen->tiling_info.group_bytes = 512;
913 break;
914 default:
915 return false;
916 }
917 return true;
918 }
919
920 static bool r600_init_tiling(struct r600_common_screen *rscreen)
921 {
922 uint32_t tiling_config = rscreen->info.r600_tiling_config;
923
924 /* set default group bytes, overridden by tiling info ioctl */
925 if (rscreen->chip_class <= R700) {
926 rscreen->tiling_info.group_bytes = 256;
927 } else {
928 rscreen->tiling_info.group_bytes = 512;
929 }
930
931 if (!tiling_config)
932 return true;
933
934 if (rscreen->chip_class <= R700) {
935 return r600_interpret_tiling(rscreen, tiling_config);
936 } else {
937 return evergreen_interpret_tiling(rscreen, tiling_config);
938 }
939 }
940
941 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
942 const struct pipe_resource *templ)
943 {
944 if (templ->target == PIPE_BUFFER) {
945 return r600_buffer_create(screen, templ, 4096);
946 } else {
947 return r600_texture_create(screen, templ);
948 }
949 }
950
951 bool r600_common_screen_init(struct r600_common_screen *rscreen,
952 struct radeon_winsys *ws)
953 {
954 char llvm_string[32] = {};
955
956 ws->query_info(ws, &rscreen->info);
957
958 #if HAVE_LLVM
959 snprintf(llvm_string, sizeof(llvm_string),
960 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
961 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
962 #endif
963
964 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
965 "%s (DRM %i.%i.%i%s)",
966 r600_get_chip_name(rscreen), rscreen->info.drm_major,
967 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
968 llvm_string);
969
970 rscreen->b.get_name = r600_get_name;
971 rscreen->b.get_vendor = r600_get_vendor;
972 rscreen->b.get_device_vendor = r600_get_device_vendor;
973 rscreen->b.get_compute_param = r600_get_compute_param;
974 rscreen->b.get_paramf = r600_get_paramf;
975 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
976 rscreen->b.get_timestamp = r600_get_timestamp;
977 rscreen->b.fence_finish = r600_fence_finish;
978 rscreen->b.fence_reference = r600_fence_reference;
979 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
980 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
981
982 if (rscreen->info.has_uvd) {
983 rscreen->b.get_video_param = rvid_get_video_param;
984 rscreen->b.is_video_format_supported = rvid_is_format_supported;
985 } else {
986 rscreen->b.get_video_param = r600_get_video_param;
987 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
988 }
989
990 r600_init_screen_texture_functions(rscreen);
991
992 rscreen->ws = ws;
993 rscreen->family = rscreen->info.family;
994 rscreen->chip_class = rscreen->info.chip_class;
995 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
996
997 if (!r600_init_tiling(rscreen)) {
998 return false;
999 }
1000 util_format_s3tc_init();
1001 pipe_mutex_init(rscreen->aux_context_lock);
1002 pipe_mutex_init(rscreen->gpu_load_mutex);
1003
1004 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
1005 rscreen->info.drm_major == 3) &&
1006 (rscreen->debug_flags & DBG_TRACE_CS)) {
1007 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
1008 PIPE_BIND_CUSTOM,
1009 PIPE_USAGE_STAGING,
1010 4096);
1011 if (rscreen->trace_bo) {
1012 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
1013 PIPE_TRANSFER_UNSYNCHRONIZED);
1014 }
1015 }
1016
1017 if (rscreen->debug_flags & DBG_INFO) {
1018 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1019 printf("family = %i\n", rscreen->info.family);
1020 printf("chip_class = %i\n", rscreen->info.chip_class);
1021 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
1022 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
1023 printf("max_sclk = %i\n", rscreen->info.max_sclk);
1024 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
1025 printf("max_se = %i\n", rscreen->info.max_se);
1026 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1027 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1028 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1029 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1030 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1031 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
1032 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
1033 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
1034 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
1035 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
1036 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
1037 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
1038 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
1039 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
1040 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
1041 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
1042 }
1043 return true;
1044 }
1045
1046 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1047 {
1048 r600_gpu_load_kill_thread(rscreen);
1049
1050 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1051 pipe_mutex_destroy(rscreen->aux_context_lock);
1052 rscreen->aux_context->destroy(rscreen->aux_context);
1053
1054 if (rscreen->trace_bo)
1055 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
1056
1057 rscreen->ws->destroy(rscreen->ws);
1058 FREE(rscreen);
1059 }
1060
1061 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1062 const struct tgsi_token *tokens)
1063 {
1064 /* Compute shader don't have tgsi_tokens */
1065 if (!tokens)
1066 return (rscreen->debug_flags & DBG_CS) != 0;
1067
1068 switch (tgsi_get_processor_type(tokens)) {
1069 case TGSI_PROCESSOR_VERTEX:
1070 return (rscreen->debug_flags & DBG_VS) != 0;
1071 case TGSI_PROCESSOR_TESS_CTRL:
1072 return (rscreen->debug_flags & DBG_TCS) != 0;
1073 case TGSI_PROCESSOR_TESS_EVAL:
1074 return (rscreen->debug_flags & DBG_TES) != 0;
1075 case TGSI_PROCESSOR_GEOMETRY:
1076 return (rscreen->debug_flags & DBG_GS) != 0;
1077 case TGSI_PROCESSOR_FRAGMENT:
1078 return (rscreen->debug_flags & DBG_PS) != 0;
1079 case TGSI_PROCESSOR_COMPUTE:
1080 return (rscreen->debug_flags & DBG_CS) != 0;
1081 default:
1082 return false;
1083 }
1084 }
1085
1086 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1087 unsigned offset, unsigned size, unsigned value,
1088 bool is_framebuffer)
1089 {
1090 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1091
1092 pipe_mutex_lock(rscreen->aux_context_lock);
1093 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1094 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1095 pipe_mutex_unlock(rscreen->aux_context_lock);
1096 }