2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
40 #include <sys/utsname.h>
46 struct r600_multi_fence
{
47 struct pipe_reference reference
;
48 struct pipe_fence_handle
*gfx
;
49 struct pipe_fence_handle
*sdma
;
53 * shader binary helpers.
55 void radeon_shader_binary_init(struct radeon_shader_binary
*b
)
57 memset(b
, 0, sizeof(*b
));
60 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
)
67 FREE(b
->global_symbol_offsets
);
69 FREE(b
->disasm_string
);
76 void r600_draw_rectangle(struct blitter_context
*blitter
,
77 int x1
, int y1
, int x2
, int y2
, float depth
,
78 enum blitter_attrib_type type
,
79 const union pipe_color_union
*attrib
)
81 struct r600_common_context
*rctx
=
82 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
83 struct pipe_viewport_state viewport
;
84 struct pipe_resource
*buf
= NULL
;
88 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
89 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
93 /* Some operations (like color resolve on r6xx) don't work
94 * with the conventional primitive types.
95 * One that works is PT_RECTLIST, which we use here. */
98 viewport
.scale
[0] = 1.0f
;
99 viewport
.scale
[1] = 1.0f
;
100 viewport
.scale
[2] = 1.0f
;
101 viewport
.translate
[0] = 0.0f
;
102 viewport
.translate
[1] = 0.0f
;
103 viewport
.translate
[2] = 0.0f
;
104 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
106 /* Upload vertices. The hw rectangle has only 3 vertices,
107 * I guess the 4th one is derived from the first 3.
108 * The vertex specification should match u_blitter's vertex element state. */
109 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, 256, &offset
, &buf
, (void**)&vb
);
129 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
130 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
131 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
135 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
136 R600_PRIM_RECTANGLE_LIST
, 3, 2);
137 pipe_resource_reference(&buf
, NULL
);
140 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
141 struct r600_resource
*dst
, struct r600_resource
*src
)
143 uint64_t vram
= 0, gtt
= 0;
146 if (dst
->domains
& RADEON_DOMAIN_VRAM
)
147 vram
+= dst
->buf
->size
;
148 else if (dst
->domains
& RADEON_DOMAIN_GTT
)
149 gtt
+= dst
->buf
->size
;
152 if (src
->domains
& RADEON_DOMAIN_VRAM
)
153 vram
+= src
->buf
->size
;
154 else if (src
->domains
& RADEON_DOMAIN_GTT
)
155 gtt
+= src
->buf
->size
;
158 /* Flush the GFX IB if DMA depends on it. */
159 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
161 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
162 RADEON_USAGE_READWRITE
)) ||
164 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
165 RADEON_USAGE_WRITE
))))
166 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
168 /* Flush if there's not enough space, or if the memory usage per IB
171 if ((num_dw
+ ctx
->dma
.cs
->cdw
) > ctx
->dma
.cs
->max_dw
||
172 !ctx
->ws
->cs_memory_below_limit(ctx
->dma
.cs
, vram
, gtt
)) {
173 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
174 assert((num_dw
+ ctx
->dma
.cs
->cdw
) <= ctx
->dma
.cs
->max_dw
);
177 /* If GPUVM is not supported, the CS checker needs 2 entries
178 * in the buffer list per packet, which has to be done manually.
180 if (ctx
->screen
->info
.has_virtual_memory
) {
182 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
184 RADEON_PRIO_SDMA_BUFFER
);
186 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
188 RADEON_PRIO_SDMA_BUFFER
);
192 /* This is required to prevent read-after-write hazards. */
193 void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
195 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
197 /* done at the end of DMA calls, so increment this. */
198 rctx
->num_dma_calls
++;
200 /* IBs using too little memory are limited by the IB submission overhead.
201 * IBs using too much memory are limited by the kernel/TTM overhead.
202 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
204 * This heuristic makes sure that DMA requests are executed
205 * very soon after the call is made and lowers memory usage.
206 * It improves texture upload performance by keeping the DMA
207 * engine busy while uploads are being submitted.
209 if (rctx
->ws
->cs_query_memory_usage(rctx
->dma
.cs
) > 64 * 1024 * 1024) {
210 rctx
->dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
214 r600_need_dma_space(rctx
, 1, NULL
, NULL
);
216 if (!radeon_emitted(cs
, 0)) /* empty queue */
219 /* NOP waits for idle on Evergreen and later. */
220 if (rctx
->chip_class
>= CIK
)
221 radeon_emit(cs
, 0x00000000); /* NOP */
222 else if (rctx
->chip_class
>= EVERGREEN
)
223 radeon_emit(cs
, 0xf0000000); /* NOP */
225 /* TODO: R600-R700 should use the FENCE packet.
226 * CS checker support is required. */
230 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
234 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
236 /* suspend queries */
237 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
238 r600_suspend_queries(ctx
);
240 ctx
->streamout
.suspended
= false;
241 if (ctx
->streamout
.begin_emitted
) {
242 r600_emit_streamout_end(ctx
);
243 ctx
->streamout
.suspended
= true;
247 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
249 if (ctx
->streamout
.suspended
) {
250 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
251 r600_streamout_buffers_dirty(ctx
);
255 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
256 r600_resume_queries(ctx
);
259 static void r600_flush_from_st(struct pipe_context
*ctx
,
260 struct pipe_fence_handle
**fence
,
263 struct pipe_screen
*screen
= ctx
->screen
;
264 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
266 struct pipe_fence_handle
*gfx_fence
= NULL
;
267 struct pipe_fence_handle
*sdma_fence
= NULL
;
269 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
270 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
273 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
275 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
277 /* Both engines can signal out of order, so we need to keep both fences. */
278 if (gfx_fence
|| sdma_fence
) {
279 struct r600_multi_fence
*multi_fence
=
280 CALLOC_STRUCT(r600_multi_fence
);
284 multi_fence
->reference
.count
= 1;
285 multi_fence
->gfx
= gfx_fence
;
286 multi_fence
->sdma
= sdma_fence
;
288 screen
->fence_reference(screen
, fence
, NULL
);
289 *fence
= (struct pipe_fence_handle
*)multi_fence
;
293 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
294 struct pipe_fence_handle
**fence
)
296 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
297 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
299 if (radeon_emitted(cs
, 0))
300 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
302 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
305 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
307 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
308 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
309 RADEON_GPU_RESET_COUNTER
);
311 if (rctx
->gpu_reset_counter
== latest
)
312 return PIPE_NO_RESET
;
314 rctx
->gpu_reset_counter
= latest
;
315 return PIPE_UNKNOWN_CONTEXT_RESET
;
318 static void r600_set_debug_callback(struct pipe_context
*ctx
,
319 const struct pipe_debug_callback
*cb
)
321 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
326 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
329 bool r600_common_context_init(struct r600_common_context
*rctx
,
330 struct r600_common_screen
*rscreen
)
332 util_slab_create(&rctx
->pool_transfers
,
333 sizeof(struct r600_transfer
), 64,
334 UTIL_SLAB_SINGLETHREADED
);
336 rctx
->screen
= rscreen
;
337 rctx
->ws
= rscreen
->ws
;
338 rctx
->family
= rscreen
->family
;
339 rctx
->chip_class
= rscreen
->chip_class
;
341 if (rscreen
->chip_class
>= CIK
)
342 rctx
->max_db
= MAX2(8, rscreen
->info
.num_render_backends
);
343 else if (rscreen
->chip_class
>= EVERGREEN
)
348 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
349 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
350 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
351 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
352 rctx
->b
.transfer_inline_write
= u_default_transfer_inline_write
;
353 rctx
->b
.memory_barrier
= r600_memory_barrier
;
354 rctx
->b
.flush
= r600_flush_from_st
;
355 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
357 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
358 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
359 rctx
->gpu_reset_counter
=
360 rctx
->ws
->query_value(rctx
->ws
,
361 RADEON_GPU_RESET_COUNTER
);
364 LIST_INITHEAD(&rctx
->texture_buffers
);
366 r600_init_context_texture_functions(rctx
);
367 r600_init_viewport_functions(rctx
);
368 r600_streamout_init(rctx
);
369 r600_query_init(rctx
);
370 cayman_init_msaa(&rctx
->b
);
372 rctx
->allocator_so_filled_size
=
373 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
374 4, 0, PIPE_USAGE_DEFAULT
, TRUE
);
375 if (!rctx
->allocator_so_filled_size
)
378 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
379 PIPE_BIND_INDEX_BUFFER
|
380 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
);
384 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
388 if (rscreen
->info
.has_sdma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
389 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
392 rctx
->dma
.flush
= r600_flush_dma_ring
;
398 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
401 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
403 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
405 rctx
->ws
->ctx_destroy(rctx
->ctx
);
407 if (rctx
->uploader
) {
408 u_upload_destroy(rctx
->uploader
);
411 util_slab_destroy(&rctx
->pool_transfers
);
413 if (rctx
->allocator_so_filled_size
) {
414 u_suballocator_destroy(rctx
->allocator_so_filled_size
);
416 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
419 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
421 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
422 struct r600_resource
*rr
= (struct r600_resource
*)r
;
429 * The idea is to compute a gross estimate of memory requirement of
430 * each draw call. After each draw call, memory will be precisely
431 * accounted. So the uncertainty is only on the current draw call.
432 * In practice this gave very good estimate (+/- 10% of the target
435 if (rr
->domains
& RADEON_DOMAIN_VRAM
)
436 rctx
->vram
+= rr
->buf
->size
;
437 else if (rr
->domains
& RADEON_DOMAIN_GTT
)
438 rctx
->gtt
+= rr
->buf
->size
;
445 static const struct debug_named_value common_debug_options
[] = {
447 { "tex", DBG_TEX
, "Print texture info" },
448 { "compute", DBG_COMPUTE
, "Print compute info" },
449 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
450 { "info", DBG_INFO
, "Print driver information" },
453 { "fs", DBG_FS
, "Print fetch shaders" },
454 { "vs", DBG_VS
, "Print vertex shaders" },
455 { "gs", DBG_GS
, "Print geometry shaders" },
456 { "ps", DBG_PS
, "Print pixel shaders" },
457 { "cs", DBG_CS
, "Print compute shaders" },
458 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
459 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
460 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
461 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
462 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
463 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
465 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
468 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
469 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
470 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
471 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
472 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
473 { "notiling", DBG_NO_TILING
, "Disable tiling" },
474 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
475 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
476 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
477 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
478 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
479 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
480 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
481 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+ on Stoney." },
482 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
483 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
484 { "noce", DBG_NO_CE
, "Disable the constant engine"},
486 DEBUG_NAMED_VALUE_END
/* must be last */
489 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
494 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
499 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
501 switch (rscreen
->info
.family
) {
502 case CHIP_R600
: return "AMD R600";
503 case CHIP_RV610
: return "AMD RV610";
504 case CHIP_RV630
: return "AMD RV630";
505 case CHIP_RV670
: return "AMD RV670";
506 case CHIP_RV620
: return "AMD RV620";
507 case CHIP_RV635
: return "AMD RV635";
508 case CHIP_RS780
: return "AMD RS780";
509 case CHIP_RS880
: return "AMD RS880";
510 case CHIP_RV770
: return "AMD RV770";
511 case CHIP_RV730
: return "AMD RV730";
512 case CHIP_RV710
: return "AMD RV710";
513 case CHIP_RV740
: return "AMD RV740";
514 case CHIP_CEDAR
: return "AMD CEDAR";
515 case CHIP_REDWOOD
: return "AMD REDWOOD";
516 case CHIP_JUNIPER
: return "AMD JUNIPER";
517 case CHIP_CYPRESS
: return "AMD CYPRESS";
518 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
519 case CHIP_PALM
: return "AMD PALM";
520 case CHIP_SUMO
: return "AMD SUMO";
521 case CHIP_SUMO2
: return "AMD SUMO2";
522 case CHIP_BARTS
: return "AMD BARTS";
523 case CHIP_TURKS
: return "AMD TURKS";
524 case CHIP_CAICOS
: return "AMD CAICOS";
525 case CHIP_CAYMAN
: return "AMD CAYMAN";
526 case CHIP_ARUBA
: return "AMD ARUBA";
527 case CHIP_TAHITI
: return "AMD TAHITI";
528 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
529 case CHIP_VERDE
: return "AMD CAPE VERDE";
530 case CHIP_OLAND
: return "AMD OLAND";
531 case CHIP_HAINAN
: return "AMD HAINAN";
532 case CHIP_BONAIRE
: return "AMD BONAIRE";
533 case CHIP_KAVERI
: return "AMD KAVERI";
534 case CHIP_KABINI
: return "AMD KABINI";
535 case CHIP_HAWAII
: return "AMD HAWAII";
536 case CHIP_MULLINS
: return "AMD MULLINS";
537 case CHIP_TONGA
: return "AMD TONGA";
538 case CHIP_ICELAND
: return "AMD ICELAND";
539 case CHIP_CARRIZO
: return "AMD CARRIZO";
540 case CHIP_FIJI
: return "AMD FIJI";
541 case CHIP_POLARIS10
: return "AMD POLARIS10";
542 case CHIP_POLARIS11
: return "AMD POLARIS11";
543 case CHIP_STONEY
: return "AMD STONEY";
544 default: return "AMD unknown";
548 static const char* r600_get_name(struct pipe_screen
* pscreen
)
550 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
552 return rscreen
->renderer_string
;
555 static float r600_get_paramf(struct pipe_screen
* pscreen
,
556 enum pipe_capf param
)
558 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
561 case PIPE_CAPF_MAX_LINE_WIDTH
:
562 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
563 case PIPE_CAPF_MAX_POINT_WIDTH
:
564 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
565 if (rscreen
->family
>= CHIP_CEDAR
)
569 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
571 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
573 case PIPE_CAPF_GUARD_BAND_LEFT
:
574 case PIPE_CAPF_GUARD_BAND_TOP
:
575 case PIPE_CAPF_GUARD_BAND_RIGHT
:
576 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
582 static int r600_get_video_param(struct pipe_screen
*screen
,
583 enum pipe_video_profile profile
,
584 enum pipe_video_entrypoint entrypoint
,
585 enum pipe_video_cap param
)
588 case PIPE_VIDEO_CAP_SUPPORTED
:
589 return vl_profile_supported(screen
, profile
, entrypoint
);
590 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
592 case PIPE_VIDEO_CAP_MAX_WIDTH
:
593 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
594 return vl_video_buffer_max_size(screen
);
595 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
596 return PIPE_FORMAT_NV12
;
597 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
599 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
601 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
603 case PIPE_VIDEO_CAP_MAX_LEVEL
:
604 return vl_level_supported(screen
, profile
);
610 const char *r600_get_llvm_processor_name(enum radeon_family family
)
653 case CHIP_TAHITI
: return "tahiti";
654 case CHIP_PITCAIRN
: return "pitcairn";
655 case CHIP_VERDE
: return "verde";
656 case CHIP_OLAND
: return "oland";
657 case CHIP_HAINAN
: return "hainan";
658 case CHIP_BONAIRE
: return "bonaire";
659 case CHIP_KABINI
: return "kabini";
660 case CHIP_KAVERI
: return "kaveri";
661 case CHIP_HAWAII
: return "hawaii";
664 case CHIP_TONGA
: return "tonga";
665 case CHIP_ICELAND
: return "iceland";
666 case CHIP_CARRIZO
: return "carrizo";
667 #if HAVE_LLVM <= 0x0307
668 case CHIP_FIJI
: return "tonga";
669 case CHIP_STONEY
: return "carrizo";
671 case CHIP_FIJI
: return "fiji";
672 case CHIP_STONEY
: return "stoney";
674 #if HAVE_LLVM <= 0x0308
675 case CHIP_POLARIS10
: return "tonga";
676 case CHIP_POLARIS11
: return "tonga";
678 case CHIP_POLARIS10
: return "polaris10";
679 case CHIP_POLARIS11
: return "polaris11";
685 static int r600_get_compute_param(struct pipe_screen
*screen
,
686 enum pipe_shader_ir ir_type
,
687 enum pipe_compute_cap param
,
690 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
692 //TODO: select these params by asic
694 case PIPE_COMPUTE_CAP_IR_TARGET
: {
697 if (rscreen
->family
<= CHIP_ARUBA
) {
702 switch(rscreen
->family
) {
703 /* Clang < 3.6 is missing Hainan in its list of
704 * GPUs, so we need to use the name of a similar GPU.
707 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
711 sprintf(ret
, "%s-%s", gpu
, triple
);
713 /* +2 for dash and terminating NIL byte */
714 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
716 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
718 uint64_t *grid_dimension
= ret
;
719 grid_dimension
[0] = 3;
721 return 1 * sizeof(uint64_t);
723 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
725 uint64_t *grid_size
= ret
;
726 grid_size
[0] = 65535;
727 grid_size
[1] = 65535;
728 grid_size
[2] = 65535;
730 return 3 * sizeof(uint64_t) ;
732 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
734 uint64_t *block_size
= ret
;
735 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
736 ir_type
== PIPE_SHADER_IR_TGSI
) {
737 block_size
[0] = 2048;
738 block_size
[1] = 2048;
739 block_size
[2] = 2048;
746 return 3 * sizeof(uint64_t);
748 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
750 uint64_t *max_threads_per_block
= ret
;
751 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
752 ir_type
== PIPE_SHADER_IR_TGSI
)
753 *max_threads_per_block
= 2048;
755 *max_threads_per_block
= 256;
757 return sizeof(uint64_t);
759 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
761 uint64_t *max_global_size
= ret
;
762 uint64_t max_mem_alloc_size
;
764 r600_get_compute_param(screen
, ir_type
,
765 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
766 &max_mem_alloc_size
);
768 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
769 * 1/4 of the MAX_GLOBAL_SIZE. Since the
770 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
771 * make sure we never report more than
772 * 4 * MAX_MEM_ALLOC_SIZE.
774 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
775 rscreen
->info
.gart_size
+
776 rscreen
->info
.vram_size
);
778 return sizeof(uint64_t);
780 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
782 uint64_t *max_local_size
= ret
;
783 /* Value reported by the closed source driver. */
784 *max_local_size
= 32768;
786 return sizeof(uint64_t);
788 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
790 uint64_t *max_input_size
= ret
;
791 /* Value reported by the closed source driver. */
792 *max_input_size
= 1024;
794 return sizeof(uint64_t);
796 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
798 uint64_t *max_mem_alloc_size
= ret
;
800 /* XXX: The limit in older kernels is 256 MB. We
801 * should add a query here for newer kernels.
803 *max_mem_alloc_size
= 256 * 1024 * 1024;
805 return sizeof(uint64_t);
807 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
809 uint32_t *max_clock_frequency
= ret
;
810 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
812 return sizeof(uint32_t);
814 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
816 uint32_t *max_compute_units
= ret
;
817 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
819 return sizeof(uint32_t);
821 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
823 uint32_t *images_supported
= ret
;
824 *images_supported
= 0;
826 return sizeof(uint32_t);
827 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
829 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
831 uint32_t *subgroup_size
= ret
;
832 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
834 return sizeof(uint32_t);
837 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
841 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
843 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
845 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
846 rscreen
->info
.clock_crystal_freq
;
849 static void r600_fence_reference(struct pipe_screen
*screen
,
850 struct pipe_fence_handle
**dst
,
851 struct pipe_fence_handle
*src
)
853 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
854 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
855 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
857 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
858 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
859 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
865 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
866 struct pipe_fence_handle
*fence
,
869 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
870 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
871 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
874 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
877 /* Recompute the timeout after waiting. */
878 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
879 int64_t time
= os_time_get_nano();
880 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
887 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
890 static void r600_query_memory_info(struct pipe_screen
*screen
,
891 struct pipe_memory_info
*info
)
893 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
894 struct radeon_winsys
*ws
= rscreen
->ws
;
895 unsigned vram_usage
, gtt_usage
;
897 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
898 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
900 /* The real TTM memory usage is somewhat random, because:
902 * 1) TTM delays freeing memory, because it can only free it after
905 * 2) The memory usage can be really low if big VRAM evictions are
906 * taking place, but the real usage is well above the size of VRAM.
908 * Instead, return statistics of this process.
910 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
911 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
913 info
->avail_device_memory
=
914 vram_usage
<= info
->total_device_memory
?
915 info
->total_device_memory
- vram_usage
: 0;
916 info
->avail_staging_memory
=
917 gtt_usage
<= info
->total_staging_memory
?
918 info
->total_staging_memory
- gtt_usage
: 0;
920 info
->device_memory_evicted
=
921 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
922 /* Just return the number of evicted 64KB pages. */
923 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
926 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
927 const struct pipe_resource
*templ
)
929 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
931 if (templ
->target
== PIPE_BUFFER
) {
932 return r600_buffer_create(screen
, templ
,
933 rscreen
->info
.gart_page_size
);
935 return r600_texture_create(screen
, templ
);
939 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
940 struct radeon_winsys
*ws
)
942 char llvm_string
[32] = {}, kernel_version
[128] = {};
943 struct utsname uname_data
;
945 ws
->query_info(ws
, &rscreen
->info
);
947 if (uname(&uname_data
) == 0)
948 snprintf(kernel_version
, sizeof(kernel_version
),
949 " / %s", uname_data
.release
);
952 snprintf(llvm_string
, sizeof(llvm_string
),
953 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
954 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
957 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
958 "%s (DRM %i.%i.%i%s%s)",
959 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
960 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
961 kernel_version
, llvm_string
);
963 rscreen
->b
.get_name
= r600_get_name
;
964 rscreen
->b
.get_vendor
= r600_get_vendor
;
965 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
966 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
967 rscreen
->b
.get_paramf
= r600_get_paramf
;
968 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
969 rscreen
->b
.fence_finish
= r600_fence_finish
;
970 rscreen
->b
.fence_reference
= r600_fence_reference
;
971 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
972 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
973 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
975 if (rscreen
->info
.has_uvd
) {
976 rscreen
->b
.get_video_param
= rvid_get_video_param
;
977 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
979 rscreen
->b
.get_video_param
= r600_get_video_param
;
980 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
983 r600_init_screen_texture_functions(rscreen
);
984 r600_init_screen_query_functions(rscreen
);
987 rscreen
->family
= rscreen
->info
.family
;
988 rscreen
->chip_class
= rscreen
->info
.chip_class
;
989 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
991 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
992 if (rscreen
->force_aniso
>= 0) {
993 printf("radeon: Forcing anisotropy filter to %ix\n",
994 /* round down to a power of two */
995 1 << util_logbase2(rscreen
->force_aniso
));
998 util_format_s3tc_init();
999 pipe_mutex_init(rscreen
->aux_context_lock
);
1000 pipe_mutex_init(rscreen
->gpu_load_mutex
);
1002 if (rscreen
->debug_flags
& DBG_INFO
) {
1003 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1004 printf("family = %i (%s)\n", rscreen
->info
.family
,
1005 r600_get_chip_name(rscreen
));
1006 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1007 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1008 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1009 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1010 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1011 printf("has_sdma = %i\n", rscreen
->info
.has_sdma
);
1012 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
1013 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
1014 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1015 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1016 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1017 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1018 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1020 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1021 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1022 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1023 printf("max_se = %i\n", rscreen
->info
.max_se
);
1024 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1026 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1027 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1028 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1029 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1030 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1031 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1036 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1038 r600_perfcounters_destroy(rscreen
);
1039 r600_gpu_load_kill_thread(rscreen
);
1041 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
1042 pipe_mutex_destroy(rscreen
->aux_context_lock
);
1043 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1045 rscreen
->ws
->destroy(rscreen
->ws
);
1049 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1052 switch (processor
) {
1053 case PIPE_SHADER_VERTEX
:
1054 return (rscreen
->debug_flags
& DBG_VS
) != 0;
1055 case PIPE_SHADER_TESS_CTRL
:
1056 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
1057 case PIPE_SHADER_TESS_EVAL
:
1058 return (rscreen
->debug_flags
& DBG_TES
) != 0;
1059 case PIPE_SHADER_GEOMETRY
:
1060 return (rscreen
->debug_flags
& DBG_GS
) != 0;
1061 case PIPE_SHADER_FRAGMENT
:
1062 return (rscreen
->debug_flags
& DBG_PS
) != 0;
1063 case PIPE_SHADER_COMPUTE
:
1064 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1070 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1071 uint64_t offset
, uint64_t size
, unsigned value
,
1072 enum r600_coherency coher
)
1074 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1076 pipe_mutex_lock(rscreen
->aux_context_lock
);
1077 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, coher
);
1078 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1079 pipe_mutex_unlock(rscreen
->aux_context_lock
);