src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/list.h"
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format_s3tc.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "os/os_time.h"
  36 #include "vl/vl_decoder.h"
  37 #include "vl/vl_video_buffer.h"
  38 #include "radeon/radeon_video.h"
  39 #include <inttypes.h>
  40
  41 #ifndef HAVE_LLVM
  42 #define HAVE_LLVM 0
  43 #endif
  44
  45 struct r600_multi_fence {
  46         struct pipe_reference reference;
  47         struct pipe_fence_handle *gfx;
  48         struct pipe_fence_handle *sdma;
  49 };
  50
  51 /*
  52  * pipe_context
  53  */
  54
  55 void r600_draw_rectangle(struct blitter_context *blitter,
  56                          int x1, int y1, int x2, int y2, float depth,
  57                          enum blitter_attrib_type type,
  58                          const union pipe_color_union *attrib)
  59 {
  60         struct r600_common_context *rctx =
  61                 (struct r600_common_context*)util_blitter_get_pipe(blitter);
  62         struct pipe_viewport_state viewport;
  63         struct pipe_resource *buf = NULL;
  64         unsigned offset = 0;
  65         float *vb;
  66
  67         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
  68                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
  69                 return;
  70         }
  71
  72         /* Some operations (like color resolve on r6xx) don't work
  73          * with the conventional primitive types.
  74          * One that works is PT_RECTLIST, which we use here. */
  75
  76         /* setup viewport */
  77         viewport.scale[0] = 1.0f;
  78         viewport.scale[1] = 1.0f;
  79         viewport.scale[2] = 1.0f;
  80         viewport.translate[0] = 0.0f;
  81         viewport.translate[1] = 0.0f;
  82         viewport.translate[2] = 0.0f;
  83         rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
  84
  85         /* Upload vertices. The hw rectangle has only 3 vertices,
  86          * I guess the 4th one is derived from the first 3.
  87          * The vertex specification should match u_blitter's vertex element state. */
  88         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
  89         if (!buf)
  90                 return;
  91
  92         vb[0] = x1;
  93         vb[1] = y1;
  94         vb[2] = depth;
  95         vb[3] = 1;
  96
  97         vb[8] = x1;
  98         vb[9] = y2;
  99         vb[10] = depth;
 100         vb[11] = 1;
 101
 102         vb[16] = x2;
 103         vb[17] = y1;
 104         vb[18] = depth;
 105         vb[19] = 1;
 106
 107         if (attrib) {
 108                 memcpy(vb+4, attrib->f, sizeof(float)*4);
 109                 memcpy(vb+12, attrib->f, sizeof(float)*4);
 110                 memcpy(vb+20, attrib->f, sizeof(float)*4);
 111         }
 112
 113         /* draw */
 114         util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
 115                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
 116         pipe_resource_reference(&buf, NULL);
 117 }
 118
 119 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
 120 {
 121         /* Flush the GFX IB if it's not empty. */
 122         if (ctx->gfx.cs->cdw > ctx->initial_gfx_cs_size)
 123                 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 124
 125         /* Flush if there's not enough space. */
 126         if ((num_dw + ctx->dma.cs->cdw) > ctx->dma.cs->max_dw) {
 127                 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
 128                 assert((num_dw + ctx->dma.cs->cdw) <= ctx->dma.cs->max_dw);
 129         }
 130 }
 131
 132 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
 133 {
 134 }
 135
 136 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 137 {
 138         /* suspend queries */
 139         if (!LIST_IS_EMPTY(&ctx->active_nontimer_queries))
 140                 r600_suspend_nontimer_queries(ctx);
 141         if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
 142                 r600_suspend_timer_queries(ctx);
 143
 144         ctx->streamout.suspended = false;
 145         if (ctx->streamout.begin_emitted) {
 146                 r600_emit_streamout_end(ctx);
 147                 ctx->streamout.suspended = true;
 148         }
 149 }
 150
 151 void r600_postflush_resume_features(struct r600_common_context *ctx)
 152 {
 153         if (ctx->streamout.suspended) {
 154                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 155                 r600_streamout_buffers_dirty(ctx);
 156         }
 157
 158         /* resume queries */
 159         if (!LIST_IS_EMPTY(&ctx->active_timer_queries))
 160                 r600_resume_timer_queries(ctx);
 161         if (!LIST_IS_EMPTY(&ctx->active_nontimer_queries))
 162                 r600_resume_nontimer_queries(ctx);
 163 }
 164
 165 static void r600_flush_from_st(struct pipe_context *ctx,
 166                                struct pipe_fence_handle **fence,
 167                                unsigned flags)
 168 {
 169         struct pipe_screen *screen = ctx->screen;
 170         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 171         unsigned rflags = 0;
 172         struct pipe_fence_handle *gfx_fence = NULL;
 173         struct pipe_fence_handle *sdma_fence = NULL;
 174
 175         if (flags & PIPE_FLUSH_END_OF_FRAME)
 176                 rflags |= RADEON_FLUSH_END_OF_FRAME;
 177
 178         if (rctx->dma.cs) {
 179                 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
 180         }
 181         rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
 182
 183         /* Both engines can signal out of order, so we need to keep both fences. */
 184         if (gfx_fence || sdma_fence) {
 185                 struct r600_multi_fence *multi_fence =
 186                         CALLOC_STRUCT(r600_multi_fence);
 187                 if (!multi_fence)
 188                         return;
 189
 190                 multi_fence->reference.count = 1;
 191                 multi_fence->gfx = gfx_fence;
 192                 multi_fence->sdma = sdma_fence;
 193
 194                 screen->fence_reference(screen, fence, NULL);
 195                 *fence = (struct pipe_fence_handle*)multi_fence;
 196         }
 197 }
 198
 199 static void r600_flush_dma_ring(void *ctx, unsigned flags,
 200                                 struct pipe_fence_handle **fence)
 201 {
 202         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 203         struct radeon_winsys_cs *cs = rctx->dma.cs;
 204
 205         if (cs->cdw)
 206                 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
 207         if (fence)
 208                 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
 209 }
 210
 211 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
 212 {
 213         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 214         unsigned latest = rctx->ws->query_value(rctx->ws,
 215                                                 RADEON_GPU_RESET_COUNTER);
 216
 217         if (rctx->gpu_reset_counter == latest)
 218                 return PIPE_NO_RESET;
 219
 220         rctx->gpu_reset_counter = latest;
 221         return PIPE_UNKNOWN_CONTEXT_RESET;
 222 }
 223
 224 bool r600_common_context_init(struct r600_common_context *rctx,
 225                               struct r600_common_screen *rscreen)
 226 {
 227         util_slab_create(&rctx->pool_transfers,
 228                          sizeof(struct r600_transfer), 64,
 229                          UTIL_SLAB_SINGLETHREADED);
 230
 231         rctx->screen = rscreen;
 232         rctx->ws = rscreen->ws;
 233         rctx->family = rscreen->family;
 234         rctx->chip_class = rscreen->chip_class;
 235
 236         if (rscreen->family == CHIP_HAWAII)
 237                 rctx->max_db = 16;
 238         else if (rscreen->chip_class >= EVERGREEN)
 239                 rctx->max_db = 8;
 240         else
 241                 rctx->max_db = 4;
 242
 243         rctx->b.transfer_map = u_transfer_map_vtbl;
 244         rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
 245         rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
 246         rctx->b.transfer_inline_write = u_default_transfer_inline_write;
 247         rctx->b.memory_barrier = r600_memory_barrier;
 248         rctx->b.flush = r600_flush_from_st;
 249
 250         if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
 251                 rctx->b.get_device_reset_status = r600_get_reset_status;
 252                 rctx->gpu_reset_counter =
 253                         rctx->ws->query_value(rctx->ws,
 254                                               RADEON_GPU_RESET_COUNTER);
 255         }
 256
 257         LIST_INITHEAD(&rctx->texture_buffers);
 258
 259         r600_init_context_texture_functions(rctx);
 260         r600_streamout_init(rctx);
 261         r600_query_init(rctx);
 262         cayman_init_msaa(&rctx->b);
 263
 264         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 265                                                                0, PIPE_USAGE_DEFAULT, TRUE);
 266         if (!rctx->allocator_so_filled_size)
 267                 return false;
 268
 269         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 270                                         PIPE_BIND_INDEX_BUFFER |
 271                                         PIPE_BIND_CONSTANT_BUFFER);
 272         if (!rctx->uploader)
 273                 return false;
 274
 275         rctx->ctx = rctx->ws->ctx_create(rctx->ws);
 276         if (!rctx->ctx)
 277                 return false;
 278
 279         if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
 280                 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
 281                                                    r600_flush_dma_ring,
 282                                                    rctx, NULL);
 283                 rctx->dma.flush = r600_flush_dma_ring;
 284         }
 285
 286         return true;
 287 }
 288
 289 void r600_common_context_cleanup(struct r600_common_context *rctx)
 290 {
 291         if (rctx->gfx.cs)
 292                 rctx->ws->cs_destroy(rctx->gfx.cs);
 293         if (rctx->dma.cs)
 294                 rctx->ws->cs_destroy(rctx->dma.cs);
 295         if (rctx->ctx)
 296                 rctx->ws->ctx_destroy(rctx->ctx);
 297
 298         if (rctx->uploader) {
 299                 u_upload_destroy(rctx->uploader);
 300         }
 301
 302         util_slab_destroy(&rctx->pool_transfers);
 303
 304         if (rctx->allocator_so_filled_size) {
 305                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 306         }
 307         rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
 308 }
 309
 310 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 311 {
 312         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 313         struct r600_resource *rr = (struct r600_resource *)r;
 314
 315         if (r == NULL) {
 316                 return;
 317         }
 318
 319         /*
 320          * The idea is to compute a gross estimate of memory requirement of
 321          * each draw call. After each draw call, memory will be precisely
 322          * accounted. So the uncertainty is only on the current draw call.
 323          * In practice this gave very good estimate (+/- 10% of the target
 324          * memory limit).
 325          */
 326         if (rr->domains & RADEON_DOMAIN_GTT) {
 327                 rctx->gtt += rr->buf->size;
 328         }
 329         if (rr->domains & RADEON_DOMAIN_VRAM) {
 330                 rctx->vram += rr->buf->size;
 331         }
 332 }
 333
 334 /*
 335  * pipe_screen
 336  */
 337
 338 static const struct debug_named_value common_debug_options[] = {
 339         /* logging */
 340         { "tex", DBG_TEX, "Print texture info" },
 341         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
 342         { "compute", DBG_COMPUTE, "Print compute info" },
 343         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
 344         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
 345         { "info", DBG_INFO, "Print driver information" },
 346
 347         /* shaders */
 348         { "fs", DBG_FS, "Print fetch shaders" },
 349         { "vs", DBG_VS, "Print vertex shaders" },
 350         { "gs", DBG_GS, "Print geometry shaders" },
 351         { "ps", DBG_PS, "Print pixel shaders" },
 352         { "cs", DBG_CS, "Print compute shaders" },
 353         { "tcs", DBG_TCS, "Print tessellation control shaders" },
 354         { "tes", DBG_TES, "Print tessellation evaluation shaders" },
 355         { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
 356         { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
 357         { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
 358
 359         /* features */
 360         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
 361         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
 362         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
 363         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
 364         { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
 365         { "notiling", DBG_NO_TILING, "Disable tiling" },
 366         { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 367         { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 368         { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
 369         { "nowc", DBG_NO_WC, "Disable GTT write combining" },
 370         { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
 371         { "nodcc", DBG_NO_DCC, "Disable DCC." },
 372         { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
 373
 374         DEBUG_NAMED_VALUE_END /* must be last */
 375 };
 376
 377 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 378 {
 379         return "X.Org";
 380 }
 381
 382 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
 383 {
 384         return "AMD";
 385 }
 386
 387 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
 388 {
 389         switch (rscreen->info.family) {
 390         case CHIP_R600: return "AMD R600";
 391         case CHIP_RV610: return "AMD RV610";
 392         case CHIP_RV630: return "AMD RV630";
 393         case CHIP_RV670: return "AMD RV670";
 394         case CHIP_RV620: return "AMD RV620";
 395         case CHIP_RV635: return "AMD RV635";
 396         case CHIP_RS780: return "AMD RS780";
 397         case CHIP_RS880: return "AMD RS880";
 398         case CHIP_RV770: return "AMD RV770";
 399         case CHIP_RV730: return "AMD RV730";
 400         case CHIP_RV710: return "AMD RV710";
 401         case CHIP_RV740: return "AMD RV740";
 402         case CHIP_CEDAR: return "AMD CEDAR";
 403         case CHIP_REDWOOD: return "AMD REDWOOD";
 404         case CHIP_JUNIPER: return "AMD JUNIPER";
 405         case CHIP_CYPRESS: return "AMD CYPRESS";
 406         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 407         case CHIP_PALM: return "AMD PALM";
 408         case CHIP_SUMO: return "AMD SUMO";
 409         case CHIP_SUMO2: return "AMD SUMO2";
 410         case CHIP_BARTS: return "AMD BARTS";
 411         case CHIP_TURKS: return "AMD TURKS";
 412         case CHIP_CAICOS: return "AMD CAICOS";
 413         case CHIP_CAYMAN: return "AMD CAYMAN";
 414         case CHIP_ARUBA: return "AMD ARUBA";
 415         case CHIP_TAHITI: return "AMD TAHITI";
 416         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 417         case CHIP_VERDE: return "AMD CAPE VERDE";
 418         case CHIP_OLAND: return "AMD OLAND";
 419         case CHIP_HAINAN: return "AMD HAINAN";
 420         case CHIP_BONAIRE: return "AMD BONAIRE";
 421         case CHIP_KAVERI: return "AMD KAVERI";
 422         case CHIP_KABINI: return "AMD KABINI";
 423         case CHIP_HAWAII: return "AMD HAWAII";
 424         case CHIP_MULLINS: return "AMD MULLINS";
 425         case CHIP_TONGA: return "AMD TONGA";
 426         case CHIP_ICELAND: return "AMD ICELAND";
 427         case CHIP_CARRIZO: return "AMD CARRIZO";
 428         case CHIP_FIJI: return "AMD FIJI";
 429         case CHIP_STONEY: return "AMD STONEY";
 430         default: return "AMD unknown";
 431         }
 432 }
 433
 434 static const char* r600_get_name(struct pipe_screen* pscreen)
 435 {
 436         struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
 437
 438         return rscreen->renderer_string;
 439 }
 440
 441 static float r600_get_paramf(struct pipe_screen* pscreen,
 442                              enum pipe_capf param)
 443 {
 444         struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
 445
 446         switch (param) {
 447         case PIPE_CAPF_MAX_LINE_WIDTH:
 448         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 449         case PIPE_CAPF_MAX_POINT_WIDTH:
 450         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 451                 if (rscreen->family >= CHIP_CEDAR)
 452                         return 16384.0f;
 453                 else
 454                         return 8192.0f;
 455         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 456                 return 16.0f;
 457         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 458                 return 16.0f;
 459         case PIPE_CAPF_GUARD_BAND_LEFT:
 460         case PIPE_CAPF_GUARD_BAND_TOP:
 461         case PIPE_CAPF_GUARD_BAND_RIGHT:
 462         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 463                 return 0.0f;
 464         }
 465         return 0.0f;
 466 }
 467
 468 static int r600_get_video_param(struct pipe_screen *screen,
 469                                 enum pipe_video_profile profile,
 470                                 enum pipe_video_entrypoint entrypoint,
 471                                 enum pipe_video_cap param)
 472 {
 473         switch (param) {
 474         case PIPE_VIDEO_CAP_SUPPORTED:
 475                 return vl_profile_supported(screen, profile, entrypoint);
 476         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 477                 return 1;
 478         case PIPE_VIDEO_CAP_MAX_WIDTH:
 479         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 480                 return vl_video_buffer_max_size(screen);
 481         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 482                 return PIPE_FORMAT_NV12;
 483         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 484                 return false;
 485         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 486                 return false;
 487         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 488                 return true;
 489         case PIPE_VIDEO_CAP_MAX_LEVEL:
 490                 return vl_level_supported(screen, profile);
 491         default:
 492                 return 0;
 493         }
 494 }
 495
 496 const char *r600_get_llvm_processor_name(enum radeon_family family)
 497 {
 498         switch (family) {
 499         case CHIP_R600:
 500         case CHIP_RV630:
 501         case CHIP_RV635:
 502         case CHIP_RV670:
 503                 return "r600";
 504         case CHIP_RV610:
 505         case CHIP_RV620:
 506         case CHIP_RS780:
 507         case CHIP_RS880:
 508                 return "rs880";
 509         case CHIP_RV710:
 510                 return "rv710";
 511         case CHIP_RV730:
 512                 return "rv730";
 513         case CHIP_RV740:
 514         case CHIP_RV770:
 515                 return "rv770";
 516         case CHIP_PALM:
 517         case CHIP_CEDAR:
 518                 return "cedar";
 519         case CHIP_SUMO:
 520         case CHIP_SUMO2:
 521                 return "sumo";
 522         case CHIP_REDWOOD:
 523                 return "redwood";
 524         case CHIP_JUNIPER:
 525                 return "juniper";
 526         case CHIP_HEMLOCK:
 527         case CHIP_CYPRESS:
 528                 return "cypress";
 529         case CHIP_BARTS:
 530                 return "barts";
 531         case CHIP_TURKS:
 532                 return "turks";
 533         case CHIP_CAICOS:
 534                 return "caicos";
 535         case CHIP_CAYMAN:
 536         case CHIP_ARUBA:
 537                 return "cayman";
 538
 539         case CHIP_TAHITI: return "tahiti";
 540         case CHIP_PITCAIRN: return "pitcairn";
 541         case CHIP_VERDE: return "verde";
 542         case CHIP_OLAND: return "oland";
 543         case CHIP_HAINAN: return "hainan";
 544         case CHIP_BONAIRE: return "bonaire";
 545         case CHIP_KABINI: return "kabini";
 546         case CHIP_KAVERI: return "kaveri";
 547         case CHIP_HAWAII: return "hawaii";
 548         case CHIP_MULLINS:
 549                 return "mullins";
 550         case CHIP_TONGA: return "tonga";
 551         case CHIP_ICELAND: return "iceland";
 552         case CHIP_CARRIZO: return "carrizo";
 553         case CHIP_FIJI: return "fiji";
 554 #if HAVE_LLVM <= 0x0307
 555         case CHIP_STONEY: return "carrizo";
 556 #else
 557         case CHIP_STONEY: return "stoney";
 558 #endif
 559         default: return "";
 560         }
 561 }
 562
 563 static int r600_get_compute_param(struct pipe_screen *screen,
 564         enum pipe_compute_cap param,
 565         void *ret)
 566 {
 567         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 568
 569         //TODO: select these params by asic
 570         switch (param) {
 571         case PIPE_COMPUTE_CAP_IR_TARGET: {
 572                 const char *gpu;
 573                 const char *triple;
 574                 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
 575                         triple = "r600--";
 576                 } else {
 577                         triple = "amdgcn--";
 578                 }
 579                 switch(rscreen->family) {
 580                 /* Clang < 3.6 is missing Hainan in its list of
 581                  * GPUs, so we need to use the name of a similar GPU.
 582                  */
 583 #if HAVE_LLVM < 0x0306
 584                 case CHIP_HAINAN:
 585                         gpu = "oland";
 586                         break;
 587 #endif
 588                 default:
 589                         gpu = r600_get_llvm_processor_name(rscreen->family);
 590                         break;
 591                 }
 592                 if (ret) {
 593                         sprintf(ret, "%s-%s", gpu, triple);
 594                 }
 595                 /* +2 for dash and terminating NIL byte */
 596                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 597         }
 598         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 599                 if (ret) {
 600                         uint64_t *grid_dimension = ret;
 601                         grid_dimension[0] = 3;
 602                 }
 603                 return 1 * sizeof(uint64_t);
 604
 605         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 606                 if (ret) {
 607                         uint64_t *grid_size = ret;
 608                         grid_size[0] = 65535;
 609                         grid_size[1] = 65535;
 610                         grid_size[2] = 1;
 611                 }
 612                 return 3 * sizeof(uint64_t) ;
 613
 614         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 615                 if (ret) {
 616                         uint64_t *block_size = ret;
 617                         block_size[0] = 256;
 618                         block_size[1] = 256;
 619                         block_size[2] = 256;
 620                 }
 621                 return 3 * sizeof(uint64_t);
 622
 623         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 624                 if (ret) {
 625                         uint64_t *max_threads_per_block = ret;
 626                         *max_threads_per_block = 256;
 627                 }
 628                 return sizeof(uint64_t);
 629
 630         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 631                 if (ret) {
 632                         uint64_t *max_global_size = ret;
 633                         uint64_t max_mem_alloc_size;
 634
 635                         r600_get_compute_param(screen,
 636                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 637                                 &max_mem_alloc_size);
 638
 639                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 640                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 641                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 642                          * make sure we never report more than
 643                          * 4 * MAX_MEM_ALLOC_SIZE.
 644                          */
 645                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 646                                 rscreen->info.gart_size +
 647                                 rscreen->info.vram_size);
 648                 }
 649                 return sizeof(uint64_t);
 650
 651         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 652                 if (ret) {
 653                         uint64_t *max_local_size = ret;
 654                         /* Value reported by the closed source driver. */
 655                         *max_local_size = 32768;
 656                 }
 657                 return sizeof(uint64_t);
 658
 659         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 660                 if (ret) {
 661                         uint64_t *max_input_size = ret;
 662                         /* Value reported by the closed source driver. */
 663                         *max_input_size = 1024;
 664                 }
 665                 return sizeof(uint64_t);
 666
 667         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 668                 if (ret) {
 669                         uint64_t *max_mem_alloc_size = ret;
 670
 671                         /* XXX: The limit in older kernels is 256 MB.  We
 672                          * should add a query here for newer kernels.
 673                          */
 674                         *max_mem_alloc_size = 256 * 1024 * 1024;
 675                 }
 676                 return sizeof(uint64_t);
 677
 678         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 679                 if (ret) {
 680                         uint32_t *max_clock_frequency = ret;
 681                         *max_clock_frequency = rscreen->info.max_sclk;
 682                 }
 683                 return sizeof(uint32_t);
 684
 685         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 686                 if (ret) {
 687                         uint32_t *max_compute_units = ret;
 688                         *max_compute_units = rscreen->info.max_compute_units;
 689                 }
 690                 return sizeof(uint32_t);
 691
 692         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 693                 if (ret) {
 694                         uint32_t *images_supported = ret;
 695                         *images_supported = 0;
 696                 }
 697                 return sizeof(uint32_t);
 698         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 699                 break; /* unused */
 700         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 701                 if (ret) {
 702                         uint32_t *subgroup_size = ret;
 703                         *subgroup_size = r600_wavefront_size(rscreen->family);
 704                 }
 705                 return sizeof(uint32_t);
 706         }
 707
 708         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 709         return 0;
 710 }
 711
 712 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 713 {
 714         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 715
 716         return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
 717                         rscreen->info.r600_clock_crystal_freq;
 718 }
 719
 720 static void r600_fence_reference(struct pipe_screen *screen,
 721                                  struct pipe_fence_handle **dst,
 722                                  struct pipe_fence_handle *src)
 723 {
 724         struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
 725         struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
 726         struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
 727
 728         if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
 729                 ws->fence_reference(&(*rdst)->gfx, NULL);
 730                 ws->fence_reference(&(*rdst)->sdma, NULL);
 731                 FREE(*rdst);
 732         }
 733         *rdst = rsrc;
 734 }
 735
 736 static boolean r600_fence_finish(struct pipe_screen *screen,
 737                                  struct pipe_fence_handle *fence,
 738                                  uint64_t timeout)
 739 {
 740         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
 741         struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
 742         int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 743
 744         if (rfence->sdma) {
 745                 if (!rws->fence_wait(rws, rfence->sdma, timeout))
 746                         return false;
 747
 748                 /* Recompute the timeout after waiting. */
 749                 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
 750                         int64_t time = os_time_get_nano();
 751                         timeout = abs_timeout > time ? abs_timeout - time : 0;
 752                 }
 753         }
 754
 755         if (!rfence->gfx)
 756                 return true;
 757
 758         return rws->fence_wait(rws, rfence->gfx, timeout);
 759 }
 760
 761 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 762                                   uint32_t tiling_config)
 763 {
 764         switch ((tiling_config & 0xe) >> 1) {
 765         case 0:
 766                 rscreen->tiling_info.num_channels = 1;
 767                 break;
 768         case 1:
 769                 rscreen->tiling_info.num_channels = 2;
 770                 break;
 771         case 2:
 772                 rscreen->tiling_info.num_channels = 4;
 773                 break;
 774         case 3:
 775                 rscreen->tiling_info.num_channels = 8;
 776                 break;
 777         default:
 778                 return false;
 779         }
 780
 781         switch ((tiling_config & 0x30) >> 4) {
 782         case 0:
 783                 rscreen->tiling_info.num_banks = 4;
 784                 break;
 785         case 1:
 786                 rscreen->tiling_info.num_banks = 8;
 787                 break;
 788         default:
 789                 return false;
 790
 791         }
 792         switch ((tiling_config & 0xc0) >> 6) {
 793         case 0:
 794                 rscreen->tiling_info.group_bytes = 256;
 795                 break;
 796         case 1:
 797                 rscreen->tiling_info.group_bytes = 512;
 798                 break;
 799         default:
 800                 return false;
 801         }
 802         return true;
 803 }
 804
 805 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 806                                        uint32_t tiling_config)
 807 {
 808         switch (tiling_config & 0xf) {
 809         case 0:
 810                 rscreen->tiling_info.num_channels = 1;
 811                 break;
 812         case 1:
 813                 rscreen->tiling_info.num_channels = 2;
 814                 break;
 815         case 2:
 816                 rscreen->tiling_info.num_channels = 4;
 817                 break;
 818         case 3:
 819                 rscreen->tiling_info.num_channels = 8;
 820                 break;
 821         default:
 822                 return false;
 823         }
 824
 825         switch ((tiling_config & 0xf0) >> 4) {
 826         case 0:
 827                 rscreen->tiling_info.num_banks = 4;
 828                 break;
 829         case 1:
 830                 rscreen->tiling_info.num_banks = 8;
 831                 break;
 832         case 2:
 833                 rscreen->tiling_info.num_banks = 16;
 834                 break;
 835         default:
 836                 return false;
 837         }
 838
 839         switch ((tiling_config & 0xf00) >> 8) {
 840         case 0:
 841                 rscreen->tiling_info.group_bytes = 256;
 842                 break;
 843         case 1:
 844                 rscreen->tiling_info.group_bytes = 512;
 845                 break;
 846         default:
 847                 return false;
 848         }
 849         return true;
 850 }
 851
 852 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 853 {
 854         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 855
 856         /* set default group bytes, overridden by tiling info ioctl */
 857         if (rscreen->chip_class <= R700) {
 858                 rscreen->tiling_info.group_bytes = 256;
 859         } else {
 860                 rscreen->tiling_info.group_bytes = 512;
 861         }
 862
 863         if (!tiling_config)
 864                 return true;
 865
 866         if (rscreen->chip_class <= R700) {
 867                 return r600_interpret_tiling(rscreen, tiling_config);
 868         } else {
 869                 return evergreen_interpret_tiling(rscreen, tiling_config);
 870         }
 871 }
 872
 873 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 874                                                   const struct pipe_resource *templ)
 875 {
 876         if (templ->target == PIPE_BUFFER) {
 877                 return r600_buffer_create(screen, templ, 4096);
 878         } else {
 879                 return r600_texture_create(screen, templ);
 880         }
 881 }
 882
 883 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 884                              struct radeon_winsys *ws)
 885 {
 886         char llvm_string[32] = {};
 887
 888         ws->query_info(ws, &rscreen->info);
 889
 890 #if HAVE_LLVM
 891         snprintf(llvm_string, sizeof(llvm_string),
 892                  ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 893                  HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 894 #endif
 895
 896         snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
 897                  "%s (DRM %i.%i.%i%s)",
 898                  r600_get_chip_name(rscreen), rscreen->info.drm_major,
 899                  rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
 900                  llvm_string);
 901
 902         rscreen->b.get_name = r600_get_name;
 903         rscreen->b.get_vendor = r600_get_vendor;
 904         rscreen->b.get_device_vendor = r600_get_device_vendor;
 905         rscreen->b.get_compute_param = r600_get_compute_param;
 906         rscreen->b.get_paramf = r600_get_paramf;
 907         rscreen->b.get_timestamp = r600_get_timestamp;
 908         rscreen->b.fence_finish = r600_fence_finish;
 909         rscreen->b.fence_reference = r600_fence_reference;
 910         rscreen->b.resource_destroy = u_resource_destroy_vtbl;
 911         rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
 912
 913         if (rscreen->info.has_uvd) {
 914                 rscreen->b.get_video_param = rvid_get_video_param;
 915                 rscreen->b.is_video_format_supported = rvid_is_format_supported;
 916         } else {
 917                 rscreen->b.get_video_param = r600_get_video_param;
 918                 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 919         }
 920
 921         r600_init_screen_texture_functions(rscreen);
 922         r600_init_screen_query_functions(rscreen);
 923
 924         rscreen->ws = ws;
 925         rscreen->family = rscreen->info.family;
 926         rscreen->chip_class = rscreen->info.chip_class;
 927         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 928
 929         if (!r600_init_tiling(rscreen)) {
 930                 return false;
 931         }
 932         util_format_s3tc_init();
 933         pipe_mutex_init(rscreen->aux_context_lock);
 934         pipe_mutex_init(rscreen->gpu_load_mutex);
 935
 936         if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
 937              rscreen->info.drm_major == 3) &&
 938             (rscreen->debug_flags & DBG_TRACE_CS)) {
 939                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
 940                                                                                 PIPE_BIND_CUSTOM,
 941                                                                                 PIPE_USAGE_STAGING,
 942                                                                                 4096);
 943                 if (rscreen->trace_bo) {
 944                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 945                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 946                 }
 947         }
 948
 949         if (rscreen->debug_flags & DBG_INFO) {
 950                 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
 951                 printf("family = %i\n", rscreen->info.family);
 952                 printf("chip_class = %i\n", rscreen->info.chip_class);
 953                 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
 954                 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
 955                 printf("max_sclk = %i\n", rscreen->info.max_sclk);
 956                 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
 957                 printf("max_se = %i\n", rscreen->info.max_se);
 958                 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
 959                 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
 960                        rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
 961                 printf("has_uvd = %i\n", rscreen->info.has_uvd);
 962                 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
 963                 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
 964                 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
 965                 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
 966                 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
 967                 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
 968                 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
 969                 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
 970                 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
 971                 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
 972                 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
 973                 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
 974         }
 975         return true;
 976 }
 977
 978 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
 979 {
 980         r600_gpu_load_kill_thread(rscreen);
 981
 982         pipe_mutex_destroy(rscreen->gpu_load_mutex);
 983         pipe_mutex_destroy(rscreen->aux_context_lock);
 984         rscreen->aux_context->destroy(rscreen->aux_context);
 985
 986         if (rscreen->trace_bo)
 987                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 988
 989         rscreen->ws->destroy(rscreen->ws);
 990         FREE(rscreen);
 991 }
 992
 993 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 994                           const struct tgsi_token *tokens)
 995 {
 996         /* Compute shader don't have tgsi_tokens */
 997         if (!tokens)
 998                 return (rscreen->debug_flags & DBG_CS) != 0;
 999
1000         switch (tgsi_get_processor_type(tokens)) {
1001         case TGSI_PROCESSOR_VERTEX:
1002                 return (rscreen->debug_flags & DBG_VS) != 0;
1003         case TGSI_PROCESSOR_TESS_CTRL:
1004                 return (rscreen->debug_flags & DBG_TCS) != 0;
1005         case TGSI_PROCESSOR_TESS_EVAL:
1006                 return (rscreen->debug_flags & DBG_TES) != 0;
1007         case TGSI_PROCESSOR_GEOMETRY:
1008                 return (rscreen->debug_flags & DBG_GS) != 0;
1009         case TGSI_PROCESSOR_FRAGMENT:
1010                 return (rscreen->debug_flags & DBG_PS) != 0;
1011         case TGSI_PROCESSOR_COMPUTE:
1012                 return (rscreen->debug_flags & DBG_CS) != 0;
1013         default:
1014                 return false;
1015         }
1016 }
1017
1018 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1019                               unsigned offset, unsigned size, unsigned value,
1020                               bool is_framebuffer)
1021 {
1022         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1023
1024         pipe_mutex_lock(rscreen->aux_context_lock);
1025         rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1026         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1027         pipe_mutex_unlock(rscreen->aux_context_lock);
1028 }