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r600g,radeonsi: implement get_device_reset_status
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= RADEON_MAX_CMDBUF_DWORDS);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->nontimer_queries_suspended = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 ctx->nontimer_queries_suspended = true;
139 }
140
141 ctx->streamout.suspended = false;
142 if (ctx->streamout.begin_emitted) {
143 r600_emit_streamout_end(ctx);
144 ctx->streamout.suspended = true;
145 }
146 }
147
148 void r600_postflush_resume_features(struct r600_common_context *ctx)
149 {
150 if (ctx->streamout.suspended) {
151 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
152 r600_streamout_buffers_dirty(ctx);
153 }
154
155 /* resume queries */
156 if (ctx->nontimer_queries_suspended) {
157 r600_resume_nontimer_queries(ctx);
158 }
159
160 /* Re-enable render condition. */
161 if (ctx->saved_render_cond) {
162 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
163 ctx->saved_render_cond_cond,
164 ctx->saved_render_cond_mode);
165 }
166 }
167
168 static void r600_flush_from_st(struct pipe_context *ctx,
169 struct pipe_fence_handle **fence,
170 unsigned flags)
171 {
172 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
173 unsigned rflags = 0;
174
175 if (flags & PIPE_FLUSH_END_OF_FRAME)
176 rflags |= RADEON_FLUSH_END_OF_FRAME;
177
178 if (rctx->rings.dma.cs) {
179 rctx->rings.dma.flush(rctx, rflags, NULL);
180 }
181 rctx->rings.gfx.flush(rctx, rflags, fence);
182 }
183
184 static void r600_flush_dma_ring(void *ctx, unsigned flags,
185 struct pipe_fence_handle **fence)
186 {
187 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
188 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
189
190 if (!cs->cdw) {
191 return;
192 }
193
194 rctx->rings.dma.flushing = true;
195 rctx->ws->cs_flush(cs, flags, fence, 0);
196 rctx->rings.dma.flushing = false;
197 }
198
199 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
200 {
201 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
202 unsigned latest = rctx->ws->query_value(rctx->ws,
203 RADEON_GPU_RESET_COUNTER);
204
205 if (rctx->gpu_reset_counter == latest)
206 return PIPE_NO_RESET;
207
208 rctx->gpu_reset_counter = latest;
209 return PIPE_UNKNOWN_CONTEXT_RESET;
210 }
211
212 bool r600_common_context_init(struct r600_common_context *rctx,
213 struct r600_common_screen *rscreen)
214 {
215 util_slab_create(&rctx->pool_transfers,
216 sizeof(struct r600_transfer), 64,
217 UTIL_SLAB_SINGLETHREADED);
218
219 rctx->screen = rscreen;
220 rctx->ws = rscreen->ws;
221 rctx->family = rscreen->family;
222 rctx->chip_class = rscreen->chip_class;
223
224 if (rscreen->family == CHIP_HAWAII)
225 rctx->max_db = 16;
226 else if (rscreen->chip_class >= EVERGREEN)
227 rctx->max_db = 8;
228 else
229 rctx->max_db = 4;
230
231 rctx->b.transfer_map = u_transfer_map_vtbl;
232 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
233 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
234 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
235 rctx->b.memory_barrier = r600_memory_barrier;
236 rctx->b.flush = r600_flush_from_st;
237
238 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
239 rctx->b.get_device_reset_status = r600_get_reset_status;
240 rctx->gpu_reset_counter =
241 rctx->ws->query_value(rctx->ws,
242 RADEON_GPU_RESET_COUNTER);
243 }
244
245 LIST_INITHEAD(&rctx->texture_buffers);
246
247 r600_init_context_texture_functions(rctx);
248 r600_streamout_init(rctx);
249 r600_query_init(rctx);
250 cayman_init_msaa(&rctx->b);
251
252 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
253 0, PIPE_USAGE_DEFAULT, TRUE);
254 if (!rctx->allocator_so_filled_size)
255 return false;
256
257 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
258 PIPE_BIND_INDEX_BUFFER |
259 PIPE_BIND_CONSTANT_BUFFER);
260 if (!rctx->uploader)
261 return false;
262
263 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
264 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
265 r600_flush_dma_ring,
266 rctx, NULL);
267 rctx->rings.dma.flush = r600_flush_dma_ring;
268 }
269
270 return true;
271 }
272
273 void r600_common_context_cleanup(struct r600_common_context *rctx)
274 {
275 if (rctx->rings.gfx.cs) {
276 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
277 }
278 if (rctx->rings.dma.cs) {
279 rctx->ws->cs_destroy(rctx->rings.dma.cs);
280 }
281
282 if (rctx->uploader) {
283 u_upload_destroy(rctx->uploader);
284 }
285
286 util_slab_destroy(&rctx->pool_transfers);
287
288 if (rctx->allocator_so_filled_size) {
289 u_suballocator_destroy(rctx->allocator_so_filled_size);
290 }
291 }
292
293 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
294 {
295 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
296 struct r600_resource *rr = (struct r600_resource *)r;
297
298 if (r == NULL) {
299 return;
300 }
301
302 /*
303 * The idea is to compute a gross estimate of memory requirement of
304 * each draw call. After each draw call, memory will be precisely
305 * accounted. So the uncertainty is only on the current draw call.
306 * In practice this gave very good estimate (+/- 10% of the target
307 * memory limit).
308 */
309 if (rr->domains & RADEON_DOMAIN_GTT) {
310 rctx->gtt += rr->buf->size;
311 }
312 if (rr->domains & RADEON_DOMAIN_VRAM) {
313 rctx->vram += rr->buf->size;
314 }
315 }
316
317 /*
318 * pipe_screen
319 */
320
321 static const struct debug_named_value common_debug_options[] = {
322 /* logging */
323 { "tex", DBG_TEX, "Print texture info" },
324 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
325 { "compute", DBG_COMPUTE, "Print compute info" },
326 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
327 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
328 { "info", DBG_INFO, "Print driver information" },
329
330 /* shaders */
331 { "fs", DBG_FS, "Print fetch shaders" },
332 { "vs", DBG_VS, "Print vertex shaders" },
333 { "gs", DBG_GS, "Print geometry shaders" },
334 { "ps", DBG_PS, "Print pixel shaders" },
335 { "cs", DBG_CS, "Print compute shaders" },
336
337 /* features */
338 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
339 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
340 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
341 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
342 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
343 { "notiling", DBG_NO_TILING, "Disable tiling" },
344 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
345 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
346 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
347
348 DEBUG_NAMED_VALUE_END /* must be last */
349 };
350
351 static const char* r600_get_vendor(struct pipe_screen* pscreen)
352 {
353 return "X.Org";
354 }
355
356 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
357 {
358 return "AMD";
359 }
360
361 static const char* r600_get_name(struct pipe_screen* pscreen)
362 {
363 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
364
365 switch (rscreen->family) {
366 case CHIP_R600: return "AMD R600";
367 case CHIP_RV610: return "AMD RV610";
368 case CHIP_RV630: return "AMD RV630";
369 case CHIP_RV670: return "AMD RV670";
370 case CHIP_RV620: return "AMD RV620";
371 case CHIP_RV635: return "AMD RV635";
372 case CHIP_RS780: return "AMD RS780";
373 case CHIP_RS880: return "AMD RS880";
374 case CHIP_RV770: return "AMD RV770";
375 case CHIP_RV730: return "AMD RV730";
376 case CHIP_RV710: return "AMD RV710";
377 case CHIP_RV740: return "AMD RV740";
378 case CHIP_CEDAR: return "AMD CEDAR";
379 case CHIP_REDWOOD: return "AMD REDWOOD";
380 case CHIP_JUNIPER: return "AMD JUNIPER";
381 case CHIP_CYPRESS: return "AMD CYPRESS";
382 case CHIP_HEMLOCK: return "AMD HEMLOCK";
383 case CHIP_PALM: return "AMD PALM";
384 case CHIP_SUMO: return "AMD SUMO";
385 case CHIP_SUMO2: return "AMD SUMO2";
386 case CHIP_BARTS: return "AMD BARTS";
387 case CHIP_TURKS: return "AMD TURKS";
388 case CHIP_CAICOS: return "AMD CAICOS";
389 case CHIP_CAYMAN: return "AMD CAYMAN";
390 case CHIP_ARUBA: return "AMD ARUBA";
391 case CHIP_TAHITI: return "AMD TAHITI";
392 case CHIP_PITCAIRN: return "AMD PITCAIRN";
393 case CHIP_VERDE: return "AMD CAPE VERDE";
394 case CHIP_OLAND: return "AMD OLAND";
395 case CHIP_HAINAN: return "AMD HAINAN";
396 case CHIP_BONAIRE: return "AMD BONAIRE";
397 case CHIP_KAVERI: return "AMD KAVERI";
398 case CHIP_KABINI: return "AMD KABINI";
399 case CHIP_HAWAII: return "AMD HAWAII";
400 case CHIP_MULLINS: return "AMD MULLINS";
401 default: return "AMD unknown";
402 }
403 }
404
405 static float r600_get_paramf(struct pipe_screen* pscreen,
406 enum pipe_capf param)
407 {
408 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
409
410 switch (param) {
411 case PIPE_CAPF_MAX_LINE_WIDTH:
412 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
413 case PIPE_CAPF_MAX_POINT_WIDTH:
414 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
415 if (rscreen->family >= CHIP_CEDAR)
416 return 16384.0f;
417 else
418 return 8192.0f;
419 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
420 return 16.0f;
421 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
422 return 16.0f;
423 case PIPE_CAPF_GUARD_BAND_LEFT:
424 case PIPE_CAPF_GUARD_BAND_TOP:
425 case PIPE_CAPF_GUARD_BAND_RIGHT:
426 case PIPE_CAPF_GUARD_BAND_BOTTOM:
427 return 0.0f;
428 }
429 return 0.0f;
430 }
431
432 static int r600_get_video_param(struct pipe_screen *screen,
433 enum pipe_video_profile profile,
434 enum pipe_video_entrypoint entrypoint,
435 enum pipe_video_cap param)
436 {
437 switch (param) {
438 case PIPE_VIDEO_CAP_SUPPORTED:
439 return vl_profile_supported(screen, profile, entrypoint);
440 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
441 return 1;
442 case PIPE_VIDEO_CAP_MAX_WIDTH:
443 case PIPE_VIDEO_CAP_MAX_HEIGHT:
444 return vl_video_buffer_max_size(screen);
445 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
446 return PIPE_FORMAT_NV12;
447 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
448 return false;
449 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
450 return false;
451 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
452 return true;
453 case PIPE_VIDEO_CAP_MAX_LEVEL:
454 return vl_level_supported(screen, profile);
455 default:
456 return 0;
457 }
458 }
459
460 const char *r600_get_llvm_processor_name(enum radeon_family family)
461 {
462 switch (family) {
463 case CHIP_R600:
464 case CHIP_RV630:
465 case CHIP_RV635:
466 case CHIP_RV670:
467 return "r600";
468 case CHIP_RV610:
469 case CHIP_RV620:
470 case CHIP_RS780:
471 case CHIP_RS880:
472 return "rs880";
473 case CHIP_RV710:
474 return "rv710";
475 case CHIP_RV730:
476 return "rv730";
477 case CHIP_RV740:
478 case CHIP_RV770:
479 return "rv770";
480 case CHIP_PALM:
481 case CHIP_CEDAR:
482 return "cedar";
483 case CHIP_SUMO:
484 case CHIP_SUMO2:
485 return "sumo";
486 case CHIP_REDWOOD:
487 return "redwood";
488 case CHIP_JUNIPER:
489 return "juniper";
490 case CHIP_HEMLOCK:
491 case CHIP_CYPRESS:
492 return "cypress";
493 case CHIP_BARTS:
494 return "barts";
495 case CHIP_TURKS:
496 return "turks";
497 case CHIP_CAICOS:
498 return "caicos";
499 case CHIP_CAYMAN:
500 case CHIP_ARUBA:
501 return "cayman";
502
503 case CHIP_TAHITI: return "tahiti";
504 case CHIP_PITCAIRN: return "pitcairn";
505 case CHIP_VERDE: return "verde";
506 case CHIP_OLAND: return "oland";
507 case CHIP_HAINAN: return "hainan";
508 case CHIP_BONAIRE: return "bonaire";
509 case CHIP_KABINI: return "kabini";
510 case CHIP_KAVERI: return "kaveri";
511 case CHIP_HAWAII: return "hawaii";
512 case CHIP_MULLINS:
513 #if HAVE_LLVM >= 0x0305
514 return "mullins";
515 #else
516 return "kabini";
517 #endif
518 default: return "";
519 }
520 }
521
522 static int r600_get_compute_param(struct pipe_screen *screen,
523 enum pipe_compute_cap param,
524 void *ret)
525 {
526 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
527
528 //TODO: select these params by asic
529 switch (param) {
530 case PIPE_COMPUTE_CAP_IR_TARGET: {
531 const char *gpu;
532 const char *triple;
533 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
534 triple = "r600--";
535 } else {
536 triple = "amdgcn--";
537 }
538 switch(rscreen->family) {
539 /* Clang < 3.6 is missing Hainan in its list of
540 * GPUs, so we need to use the name of a similar GPU.
541 */
542 #if HAVE_LLVM < 0x0306
543 case CHIP_HAINAN:
544 gpu = "oland";
545 break;
546 #endif
547 default:
548 gpu = r600_get_llvm_processor_name(rscreen->family);
549 break;
550 }
551 if (ret) {
552 sprintf(ret, "%s-%s", gpu, triple);
553 }
554 /* +2 for dash and terminating NIL byte */
555 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
556 }
557 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
558 if (ret) {
559 uint64_t *grid_dimension = ret;
560 grid_dimension[0] = 3;
561 }
562 return 1 * sizeof(uint64_t);
563
564 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
565 if (ret) {
566 uint64_t *grid_size = ret;
567 grid_size[0] = 65535;
568 grid_size[1] = 65535;
569 grid_size[2] = 1;
570 }
571 return 3 * sizeof(uint64_t) ;
572
573 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
574 if (ret) {
575 uint64_t *block_size = ret;
576 block_size[0] = 256;
577 block_size[1] = 256;
578 block_size[2] = 256;
579 }
580 return 3 * sizeof(uint64_t);
581
582 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
583 if (ret) {
584 uint64_t *max_threads_per_block = ret;
585 *max_threads_per_block = 256;
586 }
587 return sizeof(uint64_t);
588
589 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
590 if (ret) {
591 uint64_t *max_global_size = ret;
592 uint64_t max_mem_alloc_size;
593
594 r600_get_compute_param(screen,
595 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
596 &max_mem_alloc_size);
597
598 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
599 * 1/4 of the MAX_GLOBAL_SIZE. Since the
600 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
601 * make sure we never report more than
602 * 4 * MAX_MEM_ALLOC_SIZE.
603 */
604 *max_global_size = MIN2(4 * max_mem_alloc_size,
605 rscreen->info.gart_size +
606 rscreen->info.vram_size);
607 }
608 return sizeof(uint64_t);
609
610 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
611 if (ret) {
612 uint64_t *max_local_size = ret;
613 /* Value reported by the closed source driver. */
614 *max_local_size = 32768;
615 }
616 return sizeof(uint64_t);
617
618 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
619 if (ret) {
620 uint64_t *max_input_size = ret;
621 /* Value reported by the closed source driver. */
622 *max_input_size = 1024;
623 }
624 return sizeof(uint64_t);
625
626 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
627 if (ret) {
628 uint64_t *max_mem_alloc_size = ret;
629
630 /* XXX: The limit in older kernels is 256 MB. We
631 * should add a query here for newer kernels.
632 */
633 *max_mem_alloc_size = 256 * 1024 * 1024;
634 }
635 return sizeof(uint64_t);
636
637 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
638 if (ret) {
639 uint32_t *max_clock_frequency = ret;
640 *max_clock_frequency = rscreen->info.max_sclk;
641 }
642 return sizeof(uint32_t);
643
644 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
645 if (ret) {
646 uint32_t *max_compute_units = ret;
647 *max_compute_units = rscreen->info.max_compute_units;
648 }
649 return sizeof(uint32_t);
650
651 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
652 if (ret) {
653 uint32_t *images_supported = ret;
654 *images_supported = 0;
655 }
656 return sizeof(uint32_t);
657 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
658 break; /* unused */
659 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
660 if (ret) {
661 uint32_t *subgroup_size = ret;
662 *subgroup_size = r600_wavefront_size(rscreen->family);
663 }
664 return sizeof(uint32_t);
665 }
666
667 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
668 return 0;
669 }
670
671 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
672 {
673 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
674
675 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
676 rscreen->info.r600_clock_crystal_freq;
677 }
678
679 static int r600_get_driver_query_info(struct pipe_screen *screen,
680 unsigned index,
681 struct pipe_driver_query_info *info)
682 {
683 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
684 struct pipe_driver_query_info list[] = {
685 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
686 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
687 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
688 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}},
689 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
690 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES},
691 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
692 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
693 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
694 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}},
695 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}},
696 {"GPU-load", R600_QUERY_GPU_LOAD, {100}}
697 };
698 unsigned num_queries;
699
700 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
701 num_queries = Elements(list);
702 else
703 num_queries = 8;
704
705 if (!info)
706 return num_queries;
707
708 if (index >= num_queries)
709 return 0;
710
711 *info = list[index];
712 return 1;
713 }
714
715 static void r600_fence_reference(struct pipe_screen *screen,
716 struct pipe_fence_handle **ptr,
717 struct pipe_fence_handle *fence)
718 {
719 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
720
721 rws->fence_reference(ptr, fence);
722 }
723
724 static boolean r600_fence_signalled(struct pipe_screen *screen,
725 struct pipe_fence_handle *fence)
726 {
727 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
728
729 return rws->fence_wait(rws, fence, 0);
730 }
731
732 static boolean r600_fence_finish(struct pipe_screen *screen,
733 struct pipe_fence_handle *fence,
734 uint64_t timeout)
735 {
736 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
737
738 return rws->fence_wait(rws, fence, timeout);
739 }
740
741 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
742 uint32_t tiling_config)
743 {
744 switch ((tiling_config & 0xe) >> 1) {
745 case 0:
746 rscreen->tiling_info.num_channels = 1;
747 break;
748 case 1:
749 rscreen->tiling_info.num_channels = 2;
750 break;
751 case 2:
752 rscreen->tiling_info.num_channels = 4;
753 break;
754 case 3:
755 rscreen->tiling_info.num_channels = 8;
756 break;
757 default:
758 return false;
759 }
760
761 switch ((tiling_config & 0x30) >> 4) {
762 case 0:
763 rscreen->tiling_info.num_banks = 4;
764 break;
765 case 1:
766 rscreen->tiling_info.num_banks = 8;
767 break;
768 default:
769 return false;
770
771 }
772 switch ((tiling_config & 0xc0) >> 6) {
773 case 0:
774 rscreen->tiling_info.group_bytes = 256;
775 break;
776 case 1:
777 rscreen->tiling_info.group_bytes = 512;
778 break;
779 default:
780 return false;
781 }
782 return true;
783 }
784
785 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
786 uint32_t tiling_config)
787 {
788 switch (tiling_config & 0xf) {
789 case 0:
790 rscreen->tiling_info.num_channels = 1;
791 break;
792 case 1:
793 rscreen->tiling_info.num_channels = 2;
794 break;
795 case 2:
796 rscreen->tiling_info.num_channels = 4;
797 break;
798 case 3:
799 rscreen->tiling_info.num_channels = 8;
800 break;
801 default:
802 return false;
803 }
804
805 switch ((tiling_config & 0xf0) >> 4) {
806 case 0:
807 rscreen->tiling_info.num_banks = 4;
808 break;
809 case 1:
810 rscreen->tiling_info.num_banks = 8;
811 break;
812 case 2:
813 rscreen->tiling_info.num_banks = 16;
814 break;
815 default:
816 return false;
817 }
818
819 switch ((tiling_config & 0xf00) >> 8) {
820 case 0:
821 rscreen->tiling_info.group_bytes = 256;
822 break;
823 case 1:
824 rscreen->tiling_info.group_bytes = 512;
825 break;
826 default:
827 return false;
828 }
829 return true;
830 }
831
832 static bool r600_init_tiling(struct r600_common_screen *rscreen)
833 {
834 uint32_t tiling_config = rscreen->info.r600_tiling_config;
835
836 /* set default group bytes, overridden by tiling info ioctl */
837 if (rscreen->chip_class <= R700) {
838 rscreen->tiling_info.group_bytes = 256;
839 } else {
840 rscreen->tiling_info.group_bytes = 512;
841 }
842
843 if (!tiling_config)
844 return true;
845
846 if (rscreen->chip_class <= R700) {
847 return r600_interpret_tiling(rscreen, tiling_config);
848 } else {
849 return evergreen_interpret_tiling(rscreen, tiling_config);
850 }
851 }
852
853 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
854 const struct pipe_resource *templ)
855 {
856 if (templ->target == PIPE_BUFFER) {
857 return r600_buffer_create(screen, templ, 4096);
858 } else {
859 return r600_texture_create(screen, templ);
860 }
861 }
862
863 bool r600_common_screen_init(struct r600_common_screen *rscreen,
864 struct radeon_winsys *ws)
865 {
866 ws->query_info(ws, &rscreen->info);
867
868 rscreen->b.get_name = r600_get_name;
869 rscreen->b.get_vendor = r600_get_vendor;
870 rscreen->b.get_device_vendor = r600_get_device_vendor;
871 rscreen->b.get_compute_param = r600_get_compute_param;
872 rscreen->b.get_paramf = r600_get_paramf;
873 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
874 rscreen->b.get_timestamp = r600_get_timestamp;
875 rscreen->b.fence_finish = r600_fence_finish;
876 rscreen->b.fence_reference = r600_fence_reference;
877 rscreen->b.fence_signalled = r600_fence_signalled;
878 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
879 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
880
881 if (rscreen->info.has_uvd) {
882 rscreen->b.get_video_param = rvid_get_video_param;
883 rscreen->b.is_video_format_supported = rvid_is_format_supported;
884 } else {
885 rscreen->b.get_video_param = r600_get_video_param;
886 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
887 }
888
889 r600_init_screen_texture_functions(rscreen);
890
891 rscreen->ws = ws;
892 rscreen->family = rscreen->info.family;
893 rscreen->chip_class = rscreen->info.chip_class;
894 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
895
896 if (!r600_init_tiling(rscreen)) {
897 return false;
898 }
899 util_format_s3tc_init();
900 pipe_mutex_init(rscreen->aux_context_lock);
901 pipe_mutex_init(rscreen->gpu_load_mutex);
902
903 if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
904 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
905 PIPE_BIND_CUSTOM,
906 PIPE_USAGE_STAGING,
907 4096);
908 if (rscreen->trace_bo) {
909 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
910 PIPE_TRANSFER_UNSYNCHRONIZED);
911 }
912 }
913
914 if (rscreen->debug_flags & DBG_INFO) {
915 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
916 printf("family = %i\n", rscreen->info.family);
917 printf("chip_class = %i\n", rscreen->info.chip_class);
918 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
919 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
920 printf("max_sclk = %i\n", rscreen->info.max_sclk);
921 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
922 printf("max_se = %i\n", rscreen->info.max_se);
923 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
924 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
925 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
926 printf("has_uvd = %i\n", rscreen->info.has_uvd);
927 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
928 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
929 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
930 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
931 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
932 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
933 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
934 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
935 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
936 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
937 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
938 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
939 }
940 return true;
941 }
942
943 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
944 {
945 r600_gpu_load_kill_thread(rscreen);
946
947 pipe_mutex_destroy(rscreen->gpu_load_mutex);
948 pipe_mutex_destroy(rscreen->aux_context_lock);
949 rscreen->aux_context->destroy(rscreen->aux_context);
950
951 if (rscreen->trace_bo) {
952 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
953 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
954 }
955
956 rscreen->ws->destroy(rscreen->ws);
957 FREE(rscreen);
958 }
959
960 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
961 const struct tgsi_token *tokens)
962 {
963 /* Compute shader don't have tgsi_tokens */
964 if (!tokens)
965 return (rscreen->debug_flags & DBG_CS) != 0;
966
967 switch (tgsi_get_processor_type(tokens)) {
968 case TGSI_PROCESSOR_VERTEX:
969 return (rscreen->debug_flags & DBG_VS) != 0;
970 case TGSI_PROCESSOR_GEOMETRY:
971 return (rscreen->debug_flags & DBG_GS) != 0;
972 case TGSI_PROCESSOR_FRAGMENT:
973 return (rscreen->debug_flags & DBG_PS) != 0;
974 case TGSI_PROCESSOR_COMPUTE:
975 return (rscreen->debug_flags & DBG_CS) != 0;
976 default:
977 return false;
978 }
979 }
980
981 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
982 unsigned offset, unsigned size, unsigned value,
983 bool is_framebuffer)
984 {
985 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
986
987 pipe_mutex_lock(rscreen->aux_context_lock);
988 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
989 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
990 pipe_mutex_unlock(rscreen->aux_context_lock);
991 }