src/gallium/drivers/radeon/r600_pipe_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "util/u_upload_mgr.h"
  32 #include <inttypes.h>
  33
  34 static const struct debug_named_value common_debug_options[] = {
  35         /* logging */
  36         { "tex", DBG_TEX, "Print texture info" },
  37         { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
  38         { "compute", DBG_COMPUTE, "Print compute info" },
  39         { "vm", DBG_VM, "Print virtual addresses when creating resources" },
  40         { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
  41
  42         /* shaders */
  43         { "fs", DBG_FS, "Print fetch shaders" },
  44         { "vs", DBG_VS, "Print vertex shaders" },
  45         { "gs", DBG_GS, "Print geometry shaders" },
  46         { "ps", DBG_PS, "Print pixel shaders" },
  47         { "cs", DBG_CS, "Print compute shaders" },
  48
  49         { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
  50         /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
  51         { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
  52
  53         DEBUG_NAMED_VALUE_END /* must be last */
  54 };
  55
  56 static void r600_fence_reference(struct pipe_screen *screen,
  57                                  struct pipe_fence_handle **ptr,
  58                                  struct pipe_fence_handle *fence)
  59 {
  60         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
  61
  62         rws->fence_reference(ptr, fence);
  63 }
  64
  65 static boolean r600_fence_signalled(struct pipe_screen *screen,
  66                                     struct pipe_fence_handle *fence)
  67 {
  68         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
  69
  70         return rws->fence_wait(rws, fence, 0);
  71 }
  72
  73 static boolean r600_fence_finish(struct pipe_screen *screen,
  74                                  struct pipe_fence_handle *fence,
  75                                  uint64_t timeout)
  76 {
  77         struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
  78
  79         return rws->fence_wait(rws, fence, timeout);
  80 }
  81
  82 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
  83                                   uint32_t tiling_config)
  84 {
  85         switch ((tiling_config & 0xe) >> 1) {
  86         case 0:
  87                 rscreen->tiling_info.num_channels = 1;
  88                 break;
  89         case 1:
  90                 rscreen->tiling_info.num_channels = 2;
  91                 break;
  92         case 2:
  93                 rscreen->tiling_info.num_channels = 4;
  94                 break;
  95         case 3:
  96                 rscreen->tiling_info.num_channels = 8;
  97                 break;
  98         default:
  99                 return false;
 100         }
 101
 102         switch ((tiling_config & 0x30) >> 4) {
 103         case 0:
 104                 rscreen->tiling_info.num_banks = 4;
 105                 break;
 106         case 1:
 107                 rscreen->tiling_info.num_banks = 8;
 108                 break;
 109         default:
 110                 return false;
 111
 112         }
 113         switch ((tiling_config & 0xc0) >> 6) {
 114         case 0:
 115                 rscreen->tiling_info.group_bytes = 256;
 116                 break;
 117         case 1:
 118                 rscreen->tiling_info.group_bytes = 512;
 119                 break;
 120         default:
 121                 return false;
 122         }
 123         return true;
 124 }
 125
 126 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
 127                                        uint32_t tiling_config)
 128 {
 129         switch (tiling_config & 0xf) {
 130         case 0:
 131                 rscreen->tiling_info.num_channels = 1;
 132                 break;
 133         case 1:
 134                 rscreen->tiling_info.num_channels = 2;
 135                 break;
 136         case 2:
 137                 rscreen->tiling_info.num_channels = 4;
 138                 break;
 139         case 3:
 140                 rscreen->tiling_info.num_channels = 8;
 141                 break;
 142         default:
 143                 return false;
 144         }
 145
 146         switch ((tiling_config & 0xf0) >> 4) {
 147         case 0:
 148                 rscreen->tiling_info.num_banks = 4;
 149                 break;
 150         case 1:
 151                 rscreen->tiling_info.num_banks = 8;
 152                 break;
 153         case 2:
 154                 rscreen->tiling_info.num_banks = 16;
 155                 break;
 156         default:
 157                 return false;
 158         }
 159
 160         switch ((tiling_config & 0xf00) >> 8) {
 161         case 0:
 162                 rscreen->tiling_info.group_bytes = 256;
 163                 break;
 164         case 1:
 165                 rscreen->tiling_info.group_bytes = 512;
 166                 break;
 167         default:
 168                 return false;
 169         }
 170         return true;
 171 }
 172
 173 static bool r600_init_tiling(struct r600_common_screen *rscreen)
 174 {
 175         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 176
 177         /* set default group bytes, overridden by tiling info ioctl */
 178         if (rscreen->chip_class <= R700) {
 179                 rscreen->tiling_info.group_bytes = 256;
 180         } else {
 181                 rscreen->tiling_info.group_bytes = 512;
 182         }
 183
 184         if (!tiling_config)
 185                 return true;
 186
 187         if (rscreen->chip_class <= R700) {
 188                 return r600_interpret_tiling(rscreen, tiling_config);
 189         } else {
 190                 return evergreen_interpret_tiling(rscreen, tiling_config);
 191         }
 192 }
 193
 194 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 195                              struct radeon_winsys *ws)
 196 {
 197         ws->query_info(ws, &rscreen->info);
 198
 199         rscreen->b.fence_finish = r600_fence_finish;
 200         rscreen->b.fence_reference = r600_fence_reference;
 201         rscreen->b.fence_signalled = r600_fence_signalled;
 202
 203         rscreen->ws = ws;
 204         rscreen->family = rscreen->info.family;
 205         rscreen->chip_class = rscreen->info.chip_class;
 206         rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 207
 208         if (!r600_init_tiling(rscreen)) {
 209                 return false;
 210         }
 211
 212         util_format_s3tc_init();
 213
 214         pipe_mutex_init(rscreen->aux_context_lock);
 215         return true;
 216 }
 217
 218 void r600_common_screen_cleanup(struct r600_common_screen *rscreen)
 219 {
 220         pipe_mutex_destroy(rscreen->aux_context_lock);
 221         rscreen->aux_context->destroy(rscreen->aux_context);
 222 }
 223
 224 bool r600_common_context_init(struct r600_common_context *rctx,
 225                               struct r600_common_screen *rscreen)
 226 {
 227         util_slab_create(&rctx->pool_transfers,
 228                          sizeof(struct r600_transfer), 64,
 229                          UTIL_SLAB_SINGLETHREADED);
 230
 231         rctx->ws = rscreen->ws;
 232         rctx->family = rscreen->family;
 233         rctx->chip_class = rscreen->chip_class;
 234
 235         r600_streamout_init(rctx);
 236
 237         rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
 238                                                                0, PIPE_USAGE_STATIC, TRUE);
 239         if (!rctx->allocator_so_filled_size)
 240                 return false;
 241
 242         rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
 243                                         PIPE_BIND_INDEX_BUFFER |
 244                                         PIPE_BIND_CONSTANT_BUFFER);
 245         if (!rctx->uploader)
 246                 return false;
 247
 248         return true;
 249 }
 250
 251 void r600_common_context_cleanup(struct r600_common_context *rctx)
 252 {
 253         if (rctx->uploader) {
 254                 u_upload_destroy(rctx->uploader);
 255         }
 256
 257         util_slab_destroy(&rctx->pool_transfers);
 258
 259         if (rctx->allocator_so_filled_size) {
 260                 u_suballocator_destroy(rctx->allocator_so_filled_size);
 261         }
 262 }
 263
 264 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 265 {
 266         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 267         struct r600_resource *rr = (struct r600_resource *)r;
 268
 269         if (r == NULL) {
 270                 return;
 271         }
 272
 273         /*
 274          * The idea is to compute a gross estimate of memory requirement of
 275          * each draw call. After each draw call, memory will be precisely
 276          * accounted. So the uncertainty is only on the current draw call.
 277          * In practice this gave very good estimate (+/- 10% of the target
 278          * memory limit).
 279          */
 280         if (rr->domains & RADEON_DOMAIN_GTT) {
 281                 rctx->gtt += rr->buf->size;
 282         }
 283         if (rr->domains & RADEON_DOMAIN_VRAM) {
 284                 rctx->vram += rr->buf->size;
 285         }
 286 }
 287
 288 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
 289 {
 290         struct tgsi_parse_context parse;
 291
 292         if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
 293                 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
 294                 return ~0;
 295         }
 296         return parse.FullHeader.Processor.Processor;
 297 }
 298
 299 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 300                           const struct tgsi_token *tokens)
 301 {
 302         /* Compute shader don't have tgsi_tokens */
 303         if (!tokens)
 304                 return (rscreen->debug_flags & DBG_CS) != 0;
 305
 306         switch (tgsi_get_processor_type(tokens)) {
 307         case TGSI_PROCESSOR_VERTEX:
 308                 return (rscreen->debug_flags & DBG_VS) != 0;
 309         case TGSI_PROCESSOR_GEOMETRY:
 310                 return (rscreen->debug_flags & DBG_GS) != 0;
 311         case TGSI_PROCESSOR_FRAGMENT:
 312                 return (rscreen->debug_flags & DBG_PS) != 0;
 313         case TGSI_PROCESSOR_COMPUTE:
 314                 return (rscreen->debug_flags & DBG_CS) != 0;
 315         default:
 316                 return false;
 317         }
 318 }
 319
 320 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 321                               unsigned offset, unsigned size, unsigned value)
 322 {
 323         struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
 324
 325         pipe_mutex_lock(rscreen->aux_context_lock);
 326         rctx->clear_buffer(&rctx->b, dst, offset, size, value);
 327         rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
 328         pipe_mutex_unlock(rscreen->aux_context_lock);
 329 }