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gallium/radeon: enable the GPU load query for amdgpu
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 vb[0] = x1;
82 vb[1] = y1;
83 vb[2] = depth;
84 vb[3] = 1;
85
86 vb[8] = x1;
87 vb[9] = y2;
88 vb[10] = depth;
89 vb[11] = 1;
90
91 vb[16] = x2;
92 vb[17] = y1;
93 vb[18] = depth;
94 vb[19] = 1;
95
96 if (attrib) {
97 memcpy(vb+4, attrib->f, sizeof(float)*4);
98 memcpy(vb+12, attrib->f, sizeof(float)*4);
99 memcpy(vb+20, attrib->f, sizeof(float)*4);
100 }
101
102 /* draw */
103 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
104 R600_PRIM_RECTANGLE_LIST, 3, 2);
105 pipe_resource_reference(&buf, NULL);
106 }
107
108 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
109 {
110 /* Flush if there's not enough space. */
111 if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
112 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
113 assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
114 }
115 }
116
117 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 }
120
121 void r600_preflush_suspend_features(struct r600_common_context *ctx)
122 {
123 /* Disable render condition. */
124 ctx->saved_render_cond = NULL;
125 ctx->saved_render_cond_cond = FALSE;
126 ctx->saved_render_cond_mode = 0;
127 if (ctx->current_render_cond) {
128 ctx->saved_render_cond = ctx->current_render_cond;
129 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
130 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
131 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
132 }
133
134 /* suspend queries */
135 ctx->queries_suspended_for_flush = false;
136 if (ctx->num_cs_dw_nontimer_queries_suspend) {
137 r600_suspend_nontimer_queries(ctx);
138 r600_suspend_timer_queries(ctx);
139 ctx->queries_suspended_for_flush = true;
140 }
141
142 ctx->streamout.suspended = false;
143 if (ctx->streamout.begin_emitted) {
144 r600_emit_streamout_end(ctx);
145 ctx->streamout.suspended = true;
146 }
147 }
148
149 void r600_postflush_resume_features(struct r600_common_context *ctx)
150 {
151 if (ctx->streamout.suspended) {
152 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
153 r600_streamout_buffers_dirty(ctx);
154 }
155
156 /* resume queries */
157 if (ctx->queries_suspended_for_flush) {
158 r600_resume_nontimer_queries(ctx);
159 r600_resume_timer_queries(ctx);
160 }
161
162 /* Re-enable render condition. */
163 if (ctx->saved_render_cond) {
164 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
165 ctx->saved_render_cond_cond,
166 ctx->saved_render_cond_mode);
167 }
168 }
169
170 static void r600_flush_from_st(struct pipe_context *ctx,
171 struct pipe_fence_handle **fence,
172 unsigned flags)
173 {
174 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
175 unsigned rflags = 0;
176
177 if (flags & PIPE_FLUSH_END_OF_FRAME)
178 rflags |= RADEON_FLUSH_END_OF_FRAME;
179
180 if (rctx->rings.dma.cs) {
181 rctx->rings.dma.flush(rctx, rflags, NULL);
182 }
183 rctx->rings.gfx.flush(rctx, rflags, fence);
184 }
185
186 static void r600_flush_dma_ring(void *ctx, unsigned flags,
187 struct pipe_fence_handle **fence)
188 {
189 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
190 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
191
192 if (!cs->cdw) {
193 return;
194 }
195
196 rctx->rings.dma.flushing = true;
197 rctx->ws->cs_flush(cs, flags, fence, 0);
198 rctx->rings.dma.flushing = false;
199 }
200
201 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
202 {
203 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
204 unsigned latest = rctx->ws->query_value(rctx->ws,
205 RADEON_GPU_RESET_COUNTER);
206
207 if (rctx->gpu_reset_counter == latest)
208 return PIPE_NO_RESET;
209
210 rctx->gpu_reset_counter = latest;
211 return PIPE_UNKNOWN_CONTEXT_RESET;
212 }
213
214 bool r600_common_context_init(struct r600_common_context *rctx,
215 struct r600_common_screen *rscreen)
216 {
217 util_slab_create(&rctx->pool_transfers,
218 sizeof(struct r600_transfer), 64,
219 UTIL_SLAB_SINGLETHREADED);
220
221 rctx->screen = rscreen;
222 rctx->ws = rscreen->ws;
223 rctx->family = rscreen->family;
224 rctx->chip_class = rscreen->chip_class;
225
226 if (rscreen->family == CHIP_HAWAII)
227 rctx->max_db = 16;
228 else if (rscreen->chip_class >= EVERGREEN)
229 rctx->max_db = 8;
230 else
231 rctx->max_db = 4;
232
233 rctx->b.transfer_map = u_transfer_map_vtbl;
234 rctx->b.transfer_flush_region = u_default_transfer_flush_region;
235 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
236 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
237 rctx->b.memory_barrier = r600_memory_barrier;
238 rctx->b.flush = r600_flush_from_st;
239
240 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
241 rctx->b.get_device_reset_status = r600_get_reset_status;
242 rctx->gpu_reset_counter =
243 rctx->ws->query_value(rctx->ws,
244 RADEON_GPU_RESET_COUNTER);
245 }
246
247 LIST_INITHEAD(&rctx->texture_buffers);
248
249 r600_init_context_texture_functions(rctx);
250 r600_streamout_init(rctx);
251 r600_query_init(rctx);
252 cayman_init_msaa(&rctx->b);
253
254 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
255 0, PIPE_USAGE_DEFAULT, TRUE);
256 if (!rctx->allocator_so_filled_size)
257 return false;
258
259 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
260 PIPE_BIND_INDEX_BUFFER |
261 PIPE_BIND_CONSTANT_BUFFER);
262 if (!rctx->uploader)
263 return false;
264
265 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
266 if (!rctx->ctx)
267 return false;
268
269 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
270 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
271 r600_flush_dma_ring,
272 rctx, NULL);
273 rctx->rings.dma.flush = r600_flush_dma_ring;
274 }
275
276 return true;
277 }
278
279 void r600_common_context_cleanup(struct r600_common_context *rctx)
280 {
281 if (rctx->rings.gfx.cs)
282 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
283 if (rctx->rings.dma.cs)
284 rctx->ws->cs_destroy(rctx->rings.dma.cs);
285 if (rctx->ctx)
286 rctx->ws->ctx_destroy(rctx->ctx);
287
288 if (rctx->uploader) {
289 u_upload_destroy(rctx->uploader);
290 }
291
292 util_slab_destroy(&rctx->pool_transfers);
293
294 if (rctx->allocator_so_filled_size) {
295 u_suballocator_destroy(rctx->allocator_so_filled_size);
296 }
297 }
298
299 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
300 {
301 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
302 struct r600_resource *rr = (struct r600_resource *)r;
303
304 if (r == NULL) {
305 return;
306 }
307
308 /*
309 * The idea is to compute a gross estimate of memory requirement of
310 * each draw call. After each draw call, memory will be precisely
311 * accounted. So the uncertainty is only on the current draw call.
312 * In practice this gave very good estimate (+/- 10% of the target
313 * memory limit).
314 */
315 if (rr->domains & RADEON_DOMAIN_GTT) {
316 rctx->gtt += rr->buf->size;
317 }
318 if (rr->domains & RADEON_DOMAIN_VRAM) {
319 rctx->vram += rr->buf->size;
320 }
321 }
322
323 /*
324 * pipe_screen
325 */
326
327 static const struct debug_named_value common_debug_options[] = {
328 /* logging */
329 { "tex", DBG_TEX, "Print texture info" },
330 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
331 { "compute", DBG_COMPUTE, "Print compute info" },
332 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
333 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
334 { "info", DBG_INFO, "Print driver information" },
335
336 /* shaders */
337 { "fs", DBG_FS, "Print fetch shaders" },
338 { "vs", DBG_VS, "Print vertex shaders" },
339 { "gs", DBG_GS, "Print geometry shaders" },
340 { "ps", DBG_PS, "Print pixel shaders" },
341 { "cs", DBG_CS, "Print compute shaders" },
342 { "tcs", DBG_TCS, "Print tessellation control shaders" },
343 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
344 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
345 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
346 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
347
348 /* features */
349 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
350 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
351 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
352 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
353 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
354 { "notiling", DBG_NO_TILING, "Disable tiling" },
355 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
356 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
357 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
358 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
359
360 DEBUG_NAMED_VALUE_END /* must be last */
361 };
362
363 static const char* r600_get_vendor(struct pipe_screen* pscreen)
364 {
365 return "X.Org";
366 }
367
368 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
369 {
370 return "AMD";
371 }
372
373 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
374 {
375 switch (rscreen->info.family) {
376 case CHIP_R600: return "AMD R600";
377 case CHIP_RV610: return "AMD RV610";
378 case CHIP_RV630: return "AMD RV630";
379 case CHIP_RV670: return "AMD RV670";
380 case CHIP_RV620: return "AMD RV620";
381 case CHIP_RV635: return "AMD RV635";
382 case CHIP_RS780: return "AMD RS780";
383 case CHIP_RS880: return "AMD RS880";
384 case CHIP_RV770: return "AMD RV770";
385 case CHIP_RV730: return "AMD RV730";
386 case CHIP_RV710: return "AMD RV710";
387 case CHIP_RV740: return "AMD RV740";
388 case CHIP_CEDAR: return "AMD CEDAR";
389 case CHIP_REDWOOD: return "AMD REDWOOD";
390 case CHIP_JUNIPER: return "AMD JUNIPER";
391 case CHIP_CYPRESS: return "AMD CYPRESS";
392 case CHIP_HEMLOCK: return "AMD HEMLOCK";
393 case CHIP_PALM: return "AMD PALM";
394 case CHIP_SUMO: return "AMD SUMO";
395 case CHIP_SUMO2: return "AMD SUMO2";
396 case CHIP_BARTS: return "AMD BARTS";
397 case CHIP_TURKS: return "AMD TURKS";
398 case CHIP_CAICOS: return "AMD CAICOS";
399 case CHIP_CAYMAN: return "AMD CAYMAN";
400 case CHIP_ARUBA: return "AMD ARUBA";
401 case CHIP_TAHITI: return "AMD TAHITI";
402 case CHIP_PITCAIRN: return "AMD PITCAIRN";
403 case CHIP_VERDE: return "AMD CAPE VERDE";
404 case CHIP_OLAND: return "AMD OLAND";
405 case CHIP_HAINAN: return "AMD HAINAN";
406 case CHIP_BONAIRE: return "AMD BONAIRE";
407 case CHIP_KAVERI: return "AMD KAVERI";
408 case CHIP_KABINI: return "AMD KABINI";
409 case CHIP_HAWAII: return "AMD HAWAII";
410 case CHIP_MULLINS: return "AMD MULLINS";
411 case CHIP_TONGA: return "AMD TONGA";
412 case CHIP_ICELAND: return "AMD ICELAND";
413 case CHIP_CARRIZO: return "AMD CARRIZO";
414 default: return "AMD unknown";
415 }
416 }
417
418 static const char* r600_get_name(struct pipe_screen* pscreen)
419 {
420 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
421
422 return rscreen->renderer_string;
423 }
424
425 static float r600_get_paramf(struct pipe_screen* pscreen,
426 enum pipe_capf param)
427 {
428 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
429
430 switch (param) {
431 case PIPE_CAPF_MAX_LINE_WIDTH:
432 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
433 case PIPE_CAPF_MAX_POINT_WIDTH:
434 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
435 if (rscreen->family >= CHIP_CEDAR)
436 return 16384.0f;
437 else
438 return 8192.0f;
439 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
440 return 16.0f;
441 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
442 return 16.0f;
443 case PIPE_CAPF_GUARD_BAND_LEFT:
444 case PIPE_CAPF_GUARD_BAND_TOP:
445 case PIPE_CAPF_GUARD_BAND_RIGHT:
446 case PIPE_CAPF_GUARD_BAND_BOTTOM:
447 return 0.0f;
448 }
449 return 0.0f;
450 }
451
452 static int r600_get_video_param(struct pipe_screen *screen,
453 enum pipe_video_profile profile,
454 enum pipe_video_entrypoint entrypoint,
455 enum pipe_video_cap param)
456 {
457 switch (param) {
458 case PIPE_VIDEO_CAP_SUPPORTED:
459 return vl_profile_supported(screen, profile, entrypoint);
460 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
461 return 1;
462 case PIPE_VIDEO_CAP_MAX_WIDTH:
463 case PIPE_VIDEO_CAP_MAX_HEIGHT:
464 return vl_video_buffer_max_size(screen);
465 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
466 return PIPE_FORMAT_NV12;
467 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
468 return false;
469 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
470 return false;
471 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
472 return true;
473 case PIPE_VIDEO_CAP_MAX_LEVEL:
474 return vl_level_supported(screen, profile);
475 default:
476 return 0;
477 }
478 }
479
480 const char *r600_get_llvm_processor_name(enum radeon_family family)
481 {
482 switch (family) {
483 case CHIP_R600:
484 case CHIP_RV630:
485 case CHIP_RV635:
486 case CHIP_RV670:
487 return "r600";
488 case CHIP_RV610:
489 case CHIP_RV620:
490 case CHIP_RS780:
491 case CHIP_RS880:
492 return "rs880";
493 case CHIP_RV710:
494 return "rv710";
495 case CHIP_RV730:
496 return "rv730";
497 case CHIP_RV740:
498 case CHIP_RV770:
499 return "rv770";
500 case CHIP_PALM:
501 case CHIP_CEDAR:
502 return "cedar";
503 case CHIP_SUMO:
504 case CHIP_SUMO2:
505 return "sumo";
506 case CHIP_REDWOOD:
507 return "redwood";
508 case CHIP_JUNIPER:
509 return "juniper";
510 case CHIP_HEMLOCK:
511 case CHIP_CYPRESS:
512 return "cypress";
513 case CHIP_BARTS:
514 return "barts";
515 case CHIP_TURKS:
516 return "turks";
517 case CHIP_CAICOS:
518 return "caicos";
519 case CHIP_CAYMAN:
520 case CHIP_ARUBA:
521 return "cayman";
522
523 case CHIP_TAHITI: return "tahiti";
524 case CHIP_PITCAIRN: return "pitcairn";
525 case CHIP_VERDE: return "verde";
526 case CHIP_OLAND: return "oland";
527 case CHIP_HAINAN: return "hainan";
528 case CHIP_BONAIRE: return "bonaire";
529 case CHIP_KABINI: return "kabini";
530 case CHIP_KAVERI: return "kaveri";
531 case CHIP_HAWAII: return "hawaii";
532 case CHIP_MULLINS:
533 #if HAVE_LLVM >= 0x0305
534 return "mullins";
535 #else
536 return "kabini";
537 #endif
538 case CHIP_TONGA: return "tonga";
539 case CHIP_ICELAND: return "iceland";
540 case CHIP_CARRIZO: return "carrizo";
541 default: return "";
542 }
543 }
544
545 static int r600_get_compute_param(struct pipe_screen *screen,
546 enum pipe_compute_cap param,
547 void *ret)
548 {
549 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
550
551 //TODO: select these params by asic
552 switch (param) {
553 case PIPE_COMPUTE_CAP_IR_TARGET: {
554 const char *gpu;
555 const char *triple;
556 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
557 triple = "r600--";
558 } else {
559 triple = "amdgcn--";
560 }
561 switch(rscreen->family) {
562 /* Clang < 3.6 is missing Hainan in its list of
563 * GPUs, so we need to use the name of a similar GPU.
564 */
565 #if HAVE_LLVM < 0x0306
566 case CHIP_HAINAN:
567 gpu = "oland";
568 break;
569 #endif
570 default:
571 gpu = r600_get_llvm_processor_name(rscreen->family);
572 break;
573 }
574 if (ret) {
575 sprintf(ret, "%s-%s", gpu, triple);
576 }
577 /* +2 for dash and terminating NIL byte */
578 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
579 }
580 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
581 if (ret) {
582 uint64_t *grid_dimension = ret;
583 grid_dimension[0] = 3;
584 }
585 return 1 * sizeof(uint64_t);
586
587 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
588 if (ret) {
589 uint64_t *grid_size = ret;
590 grid_size[0] = 65535;
591 grid_size[1] = 65535;
592 grid_size[2] = 1;
593 }
594 return 3 * sizeof(uint64_t) ;
595
596 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
597 if (ret) {
598 uint64_t *block_size = ret;
599 block_size[0] = 256;
600 block_size[1] = 256;
601 block_size[2] = 256;
602 }
603 return 3 * sizeof(uint64_t);
604
605 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
606 if (ret) {
607 uint64_t *max_threads_per_block = ret;
608 *max_threads_per_block = 256;
609 }
610 return sizeof(uint64_t);
611
612 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
613 if (ret) {
614 uint64_t *max_global_size = ret;
615 uint64_t max_mem_alloc_size;
616
617 r600_get_compute_param(screen,
618 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
619 &max_mem_alloc_size);
620
621 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
622 * 1/4 of the MAX_GLOBAL_SIZE. Since the
623 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
624 * make sure we never report more than
625 * 4 * MAX_MEM_ALLOC_SIZE.
626 */
627 *max_global_size = MIN2(4 * max_mem_alloc_size,
628 rscreen->info.gart_size +
629 rscreen->info.vram_size);
630 }
631 return sizeof(uint64_t);
632
633 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
634 if (ret) {
635 uint64_t *max_local_size = ret;
636 /* Value reported by the closed source driver. */
637 *max_local_size = 32768;
638 }
639 return sizeof(uint64_t);
640
641 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
642 if (ret) {
643 uint64_t *max_input_size = ret;
644 /* Value reported by the closed source driver. */
645 *max_input_size = 1024;
646 }
647 return sizeof(uint64_t);
648
649 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
650 if (ret) {
651 uint64_t *max_mem_alloc_size = ret;
652
653 /* XXX: The limit in older kernels is 256 MB. We
654 * should add a query here for newer kernels.
655 */
656 *max_mem_alloc_size = 256 * 1024 * 1024;
657 }
658 return sizeof(uint64_t);
659
660 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
661 if (ret) {
662 uint32_t *max_clock_frequency = ret;
663 *max_clock_frequency = rscreen->info.max_sclk;
664 }
665 return sizeof(uint32_t);
666
667 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
668 if (ret) {
669 uint32_t *max_compute_units = ret;
670 *max_compute_units = rscreen->info.max_compute_units;
671 }
672 return sizeof(uint32_t);
673
674 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
675 if (ret) {
676 uint32_t *images_supported = ret;
677 *images_supported = 0;
678 }
679 return sizeof(uint32_t);
680 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
681 break; /* unused */
682 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
683 if (ret) {
684 uint32_t *subgroup_size = ret;
685 *subgroup_size = r600_wavefront_size(rscreen->family);
686 }
687 return sizeof(uint32_t);
688 }
689
690 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
691 return 0;
692 }
693
694 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
695 {
696 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
697
698 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
699 rscreen->info.r600_clock_crystal_freq;
700 }
701
702 static int r600_get_driver_query_info(struct pipe_screen *screen,
703 unsigned index,
704 struct pipe_driver_query_info *info)
705 {
706 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
707 struct pipe_driver_query_info list[] = {
708 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
709 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
710 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
711 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
712 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
713 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
714 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
715 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
716 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
717 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
718 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
719 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
720 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
721 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
722 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
723 {"temperature", R600_QUERY_GPU_TEMPERATURE, {100}},
724 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
725 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
726 };
727 unsigned num_queries;
728
729 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
730 num_queries = Elements(list);
731 else if (rscreen->info.drm_major == 3)
732 num_queries = Elements(list) - 3;
733 else
734 num_queries = Elements(list) - 4;
735
736 if (!info)
737 return num_queries;
738
739 if (index >= num_queries)
740 return 0;
741
742 *info = list[index];
743 return 1;
744 }
745
746 static void r600_fence_reference(struct pipe_screen *screen,
747 struct pipe_fence_handle **ptr,
748 struct pipe_fence_handle *fence)
749 {
750 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
751
752 rws->fence_reference(ptr, fence);
753 }
754
755 static boolean r600_fence_finish(struct pipe_screen *screen,
756 struct pipe_fence_handle *fence,
757 uint64_t timeout)
758 {
759 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
760
761 return rws->fence_wait(rws, fence, timeout);
762 }
763
764 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
765 uint32_t tiling_config)
766 {
767 switch ((tiling_config & 0xe) >> 1) {
768 case 0:
769 rscreen->tiling_info.num_channels = 1;
770 break;
771 case 1:
772 rscreen->tiling_info.num_channels = 2;
773 break;
774 case 2:
775 rscreen->tiling_info.num_channels = 4;
776 break;
777 case 3:
778 rscreen->tiling_info.num_channels = 8;
779 break;
780 default:
781 return false;
782 }
783
784 switch ((tiling_config & 0x30) >> 4) {
785 case 0:
786 rscreen->tiling_info.num_banks = 4;
787 break;
788 case 1:
789 rscreen->tiling_info.num_banks = 8;
790 break;
791 default:
792 return false;
793
794 }
795 switch ((tiling_config & 0xc0) >> 6) {
796 case 0:
797 rscreen->tiling_info.group_bytes = 256;
798 break;
799 case 1:
800 rscreen->tiling_info.group_bytes = 512;
801 break;
802 default:
803 return false;
804 }
805 return true;
806 }
807
808 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
809 uint32_t tiling_config)
810 {
811 switch (tiling_config & 0xf) {
812 case 0:
813 rscreen->tiling_info.num_channels = 1;
814 break;
815 case 1:
816 rscreen->tiling_info.num_channels = 2;
817 break;
818 case 2:
819 rscreen->tiling_info.num_channels = 4;
820 break;
821 case 3:
822 rscreen->tiling_info.num_channels = 8;
823 break;
824 default:
825 return false;
826 }
827
828 switch ((tiling_config & 0xf0) >> 4) {
829 case 0:
830 rscreen->tiling_info.num_banks = 4;
831 break;
832 case 1:
833 rscreen->tiling_info.num_banks = 8;
834 break;
835 case 2:
836 rscreen->tiling_info.num_banks = 16;
837 break;
838 default:
839 return false;
840 }
841
842 switch ((tiling_config & 0xf00) >> 8) {
843 case 0:
844 rscreen->tiling_info.group_bytes = 256;
845 break;
846 case 1:
847 rscreen->tiling_info.group_bytes = 512;
848 break;
849 default:
850 return false;
851 }
852 return true;
853 }
854
855 static bool r600_init_tiling(struct r600_common_screen *rscreen)
856 {
857 uint32_t tiling_config = rscreen->info.r600_tiling_config;
858
859 /* set default group bytes, overridden by tiling info ioctl */
860 if (rscreen->chip_class <= R700) {
861 rscreen->tiling_info.group_bytes = 256;
862 } else {
863 rscreen->tiling_info.group_bytes = 512;
864 }
865
866 if (!tiling_config)
867 return true;
868
869 if (rscreen->chip_class <= R700) {
870 return r600_interpret_tiling(rscreen, tiling_config);
871 } else {
872 return evergreen_interpret_tiling(rscreen, tiling_config);
873 }
874 }
875
876 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
877 const struct pipe_resource *templ)
878 {
879 if (templ->target == PIPE_BUFFER) {
880 return r600_buffer_create(screen, templ, 4096);
881 } else {
882 return r600_texture_create(screen, templ);
883 }
884 }
885
886 bool r600_common_screen_init(struct r600_common_screen *rscreen,
887 struct radeon_winsys *ws)
888 {
889 char llvm_string[32] = {};
890
891 ws->query_info(ws, &rscreen->info);
892
893 #if HAVE_LLVM
894 snprintf(llvm_string, sizeof(llvm_string),
895 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
896 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
897 #endif
898
899 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
900 "%s (DRM %i.%i.%i%s)",
901 r600_get_chip_name(rscreen), rscreen->info.drm_major,
902 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
903 llvm_string);
904
905 rscreen->b.get_name = r600_get_name;
906 rscreen->b.get_vendor = r600_get_vendor;
907 rscreen->b.get_device_vendor = r600_get_device_vendor;
908 rscreen->b.get_compute_param = r600_get_compute_param;
909 rscreen->b.get_paramf = r600_get_paramf;
910 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
911 rscreen->b.get_timestamp = r600_get_timestamp;
912 rscreen->b.fence_finish = r600_fence_finish;
913 rscreen->b.fence_reference = r600_fence_reference;
914 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
915 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
916
917 if (rscreen->info.has_uvd) {
918 rscreen->b.get_video_param = rvid_get_video_param;
919 rscreen->b.is_video_format_supported = rvid_is_format_supported;
920 } else {
921 rscreen->b.get_video_param = r600_get_video_param;
922 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
923 }
924
925 r600_init_screen_texture_functions(rscreen);
926
927 rscreen->ws = ws;
928 rscreen->family = rscreen->info.family;
929 rscreen->chip_class = rscreen->info.chip_class;
930 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
931
932 if (!r600_init_tiling(rscreen)) {
933 return false;
934 }
935 util_format_s3tc_init();
936 pipe_mutex_init(rscreen->aux_context_lock);
937 pipe_mutex_init(rscreen->gpu_load_mutex);
938
939 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
940 rscreen->info.drm_major == 3) &&
941 (rscreen->debug_flags & DBG_TRACE_CS)) {
942 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
943 PIPE_BIND_CUSTOM,
944 PIPE_USAGE_STAGING,
945 4096);
946 if (rscreen->trace_bo) {
947 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
948 PIPE_TRANSFER_UNSYNCHRONIZED);
949 }
950 }
951
952 if (rscreen->debug_flags & DBG_INFO) {
953 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
954 printf("family = %i\n", rscreen->info.family);
955 printf("chip_class = %i\n", rscreen->info.chip_class);
956 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
957 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
958 printf("max_sclk = %i\n", rscreen->info.max_sclk);
959 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
960 printf("max_se = %i\n", rscreen->info.max_se);
961 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
962 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
963 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
964 printf("has_uvd = %i\n", rscreen->info.has_uvd);
965 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
966 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
967 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
968 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
969 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
970 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
971 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
972 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
973 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
974 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
975 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
976 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
977 }
978 return true;
979 }
980
981 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
982 {
983 r600_gpu_load_kill_thread(rscreen);
984
985 pipe_mutex_destroy(rscreen->gpu_load_mutex);
986 pipe_mutex_destroy(rscreen->aux_context_lock);
987 rscreen->aux_context->destroy(rscreen->aux_context);
988
989 if (rscreen->trace_bo)
990 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
991
992 rscreen->ws->destroy(rscreen->ws);
993 FREE(rscreen);
994 }
995
996 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
997 const struct tgsi_token *tokens)
998 {
999 /* Compute shader don't have tgsi_tokens */
1000 if (!tokens)
1001 return (rscreen->debug_flags & DBG_CS) != 0;
1002
1003 switch (tgsi_get_processor_type(tokens)) {
1004 case TGSI_PROCESSOR_VERTEX:
1005 return (rscreen->debug_flags & DBG_VS) != 0;
1006 case TGSI_PROCESSOR_TESS_CTRL:
1007 return (rscreen->debug_flags & DBG_TCS) != 0;
1008 case TGSI_PROCESSOR_TESS_EVAL:
1009 return (rscreen->debug_flags & DBG_TES) != 0;
1010 case TGSI_PROCESSOR_GEOMETRY:
1011 return (rscreen->debug_flags & DBG_GS) != 0;
1012 case TGSI_PROCESSOR_FRAGMENT:
1013 return (rscreen->debug_flags & DBG_PS) != 0;
1014 case TGSI_PROCESSOR_COMPUTE:
1015 return (rscreen->debug_flags & DBG_CS) != 0;
1016 default:
1017 return false;
1018 }
1019 }
1020
1021 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1022 unsigned offset, unsigned size, unsigned value,
1023 bool is_framebuffer)
1024 {
1025 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1026
1027 pipe_mutex_lock(rscreen->aux_context_lock);
1028 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1029 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1030 pipe_mutex_unlock(rscreen->aux_context_lock);
1031 }