projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: add an option for debugging VM faults
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
37 #include <inttypes.h>
38
39 #ifndef HAVE_LLVM
40 #define HAVE_LLVM 0
41 #endif
42
43 /*
44 * pipe_context
45 */
46
47 void r600_draw_rectangle(struct blitter_context *blitter,
48 int x1, int y1, int x2, int y2, float depth,
49 enum blitter_attrib_type type,
50 const union pipe_color_union *attrib)
51 {
52 struct r600_common_context *rctx =
53 (struct r600_common_context*)util_blitter_get_pipe(blitter);
54 struct pipe_viewport_state viewport;
55 struct pipe_resource *buf = NULL;
56 unsigned offset = 0;
57 float *vb;
58
59 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
60 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
61 return;
62 }
63
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
67
68 /* setup viewport */
69 viewport.scale[0] = 1.0f;
70 viewport.scale[1] = 1.0f;
71 viewport.scale[2] = 1.0f;
72 viewport.translate[0] = 0.0f;
73 viewport.translate[1] = 0.0f;
74 viewport.translate[2] = 0.0f;
75 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
76
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
81 if (!buf)
82 return;
83
84 vb[0] = x1;
85 vb[1] = y1;
86 vb[2] = depth;
87 vb[3] = 1;
88
89 vb[8] = x1;
90 vb[9] = y2;
91 vb[10] = depth;
92 vb[11] = 1;
93
94 vb[16] = x2;
95 vb[17] = y1;
96 vb[18] = depth;
97 vb[19] = 1;
98
99 if (attrib) {
100 memcpy(vb+4, attrib->f, sizeof(float)*4);
101 memcpy(vb+12, attrib->f, sizeof(float)*4);
102 memcpy(vb+20, attrib->f, sizeof(float)*4);
103 }
104
105 /* draw */
106 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
107 R600_PRIM_RECTANGLE_LIST, 3, 2);
108 pipe_resource_reference(&buf, NULL);
109 }
110
111 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
112 {
113 /* Flush if there's not enough space. */
114 if ((num_dw + ctx->rings.dma.cs->cdw) > ctx->rings.dma.cs->max_dw) {
115 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
116 assert((num_dw + ctx->rings.dma.cs->cdw) <= ctx->rings.dma.cs->max_dw);
117 }
118 }
119
120 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
121 {
122 }
123
124 void r600_preflush_suspend_features(struct r600_common_context *ctx)
125 {
126 /* Disable render condition. */
127 ctx->saved_render_cond = NULL;
128 ctx->saved_render_cond_cond = FALSE;
129 ctx->saved_render_cond_mode = 0;
130 if (ctx->current_render_cond) {
131 ctx->saved_render_cond = ctx->current_render_cond;
132 ctx->saved_render_cond_cond = ctx->current_render_cond_cond;
133 ctx->saved_render_cond_mode = ctx->current_render_cond_mode;
134 ctx->b.render_condition(&ctx->b, NULL, FALSE, 0);
135 }
136
137 /* suspend queries */
138 ctx->queries_suspended_for_flush = false;
139 if (ctx->num_cs_dw_nontimer_queries_suspend) {
140 r600_suspend_nontimer_queries(ctx);
141 r600_suspend_timer_queries(ctx);
142 ctx->queries_suspended_for_flush = true;
143 }
144
145 ctx->streamout.suspended = false;
146 if (ctx->streamout.begin_emitted) {
147 r600_emit_streamout_end(ctx);
148 ctx->streamout.suspended = true;
149 }
150 }
151
152 void r600_postflush_resume_features(struct r600_common_context *ctx)
153 {
154 if (ctx->streamout.suspended) {
155 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
156 r600_streamout_buffers_dirty(ctx);
157 }
158
159 /* resume queries */
160 if (ctx->queries_suspended_for_flush) {
161 r600_resume_nontimer_queries(ctx);
162 r600_resume_timer_queries(ctx);
163 }
164
165 /* Re-enable render condition. */
166 if (ctx->saved_render_cond) {
167 ctx->b.render_condition(&ctx->b, ctx->saved_render_cond,
168 ctx->saved_render_cond_cond,
169 ctx->saved_render_cond_mode);
170 }
171 }
172
173 static void r600_flush_from_st(struct pipe_context *ctx,
174 struct pipe_fence_handle **fence,
175 unsigned flags)
176 {
177 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
178 unsigned rflags = 0;
179
180 if (flags & PIPE_FLUSH_END_OF_FRAME)
181 rflags |= RADEON_FLUSH_END_OF_FRAME;
182
183 if (rctx->rings.dma.cs) {
184 rctx->rings.dma.flush(rctx, rflags, NULL);
185 }
186 rctx->rings.gfx.flush(rctx, rflags, fence);
187 }
188
189 static void r600_flush_dma_ring(void *ctx, unsigned flags,
190 struct pipe_fence_handle **fence)
191 {
192 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
193 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
194
195 if (!cs->cdw) {
196 return;
197 }
198
199 rctx->rings.dma.flushing = true;
200 rctx->ws->cs_flush(cs, flags, fence, 0);
201 rctx->rings.dma.flushing = false;
202 }
203
204 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
205 {
206 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
207 unsigned latest = rctx->ws->query_value(rctx->ws,
208 RADEON_GPU_RESET_COUNTER);
209
210 if (rctx->gpu_reset_counter == latest)
211 return PIPE_NO_RESET;
212
213 rctx->gpu_reset_counter = latest;
214 return PIPE_UNKNOWN_CONTEXT_RESET;
215 }
216
217 bool r600_common_context_init(struct r600_common_context *rctx,
218 struct r600_common_screen *rscreen)
219 {
220 util_slab_create(&rctx->pool_transfers,
221 sizeof(struct r600_transfer), 64,
222 UTIL_SLAB_SINGLETHREADED);
223
224 rctx->screen = rscreen;
225 rctx->ws = rscreen->ws;
226 rctx->family = rscreen->family;
227 rctx->chip_class = rscreen->chip_class;
228
229 if (rscreen->family == CHIP_HAWAII)
230 rctx->max_db = 16;
231 else if (rscreen->chip_class >= EVERGREEN)
232 rctx->max_db = 8;
233 else
234 rctx->max_db = 4;
235
236 rctx->b.transfer_map = u_transfer_map_vtbl;
237 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
238 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
239 rctx->b.transfer_inline_write = u_default_transfer_inline_write;
240 rctx->b.memory_barrier = r600_memory_barrier;
241 rctx->b.flush = r600_flush_from_st;
242
243 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
244 rctx->b.get_device_reset_status = r600_get_reset_status;
245 rctx->gpu_reset_counter =
246 rctx->ws->query_value(rctx->ws,
247 RADEON_GPU_RESET_COUNTER);
248 }
249
250 LIST_INITHEAD(&rctx->texture_buffers);
251
252 r600_init_context_texture_functions(rctx);
253 r600_streamout_init(rctx);
254 r600_query_init(rctx);
255 cayman_init_msaa(&rctx->b);
256
257 rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
258 0, PIPE_USAGE_DEFAULT, TRUE);
259 if (!rctx->allocator_so_filled_size)
260 return false;
261
262 rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
263 PIPE_BIND_INDEX_BUFFER |
264 PIPE_BIND_CONSTANT_BUFFER);
265 if (!rctx->uploader)
266 return false;
267
268 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
269 if (!rctx->ctx)
270 return false;
271
272 if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
273 rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
274 r600_flush_dma_ring,
275 rctx, NULL);
276 rctx->rings.dma.flush = r600_flush_dma_ring;
277 }
278
279 return true;
280 }
281
282 void r600_common_context_cleanup(struct r600_common_context *rctx)
283 {
284 if (rctx->rings.gfx.cs)
285 rctx->ws->cs_destroy(rctx->rings.gfx.cs);
286 if (rctx->rings.dma.cs)
287 rctx->ws->cs_destroy(rctx->rings.dma.cs);
288 if (rctx->ctx)
289 rctx->ws->ctx_destroy(rctx->ctx);
290
291 if (rctx->uploader) {
292 u_upload_destroy(rctx->uploader);
293 }
294
295 util_slab_destroy(&rctx->pool_transfers);
296
297 if (rctx->allocator_so_filled_size) {
298 u_suballocator_destroy(rctx->allocator_so_filled_size);
299 }
300 }
301
302 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
303 {
304 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
305 struct r600_resource *rr = (struct r600_resource *)r;
306
307 if (r == NULL) {
308 return;
309 }
310
311 /*
312 * The idea is to compute a gross estimate of memory requirement of
313 * each draw call. After each draw call, memory will be precisely
314 * accounted. So the uncertainty is only on the current draw call.
315 * In practice this gave very good estimate (+/- 10% of the target
316 * memory limit).
317 */
318 if (rr->domains & RADEON_DOMAIN_GTT) {
319 rctx->gtt += rr->buf->size;
320 }
321 if (rr->domains & RADEON_DOMAIN_VRAM) {
322 rctx->vram += rr->buf->size;
323 }
324 }
325
326 /*
327 * pipe_screen
328 */
329
330 static const struct debug_named_value common_debug_options[] = {
331 /* logging */
332 { "tex", DBG_TEX, "Print texture info" },
333 { "texmip", DBG_TEXMIP, "Print texture info (mipmapped only)" },
334 { "compute", DBG_COMPUTE, "Print compute info" },
335 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
336 { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
337 { "info", DBG_INFO, "Print driver information" },
338
339 /* shaders */
340 { "fs", DBG_FS, "Print fetch shaders" },
341 { "vs", DBG_VS, "Print vertex shaders" },
342 { "gs", DBG_GS, "Print geometry shaders" },
343 { "ps", DBG_PS, "Print pixel shaders" },
344 { "cs", DBG_CS, "Print compute shaders" },
345 { "tcs", DBG_TCS, "Print tessellation control shaders" },
346 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
347 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
348 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
349 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
350
351 /* features */
352 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
353 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
354 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
355 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
356 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
357 { "notiling", DBG_NO_TILING, "Disable tiling" },
358 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
359 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
360 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
361 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
362 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
363
364 DEBUG_NAMED_VALUE_END /* must be last */
365 };
366
367 static const char* r600_get_vendor(struct pipe_screen* pscreen)
368 {
369 return "X.Org";
370 }
371
372 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
373 {
374 return "AMD";
375 }
376
377 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
378 {
379 switch (rscreen->info.family) {
380 case CHIP_R600: return "AMD R600";
381 case CHIP_RV610: return "AMD RV610";
382 case CHIP_RV630: return "AMD RV630";
383 case CHIP_RV670: return "AMD RV670";
384 case CHIP_RV620: return "AMD RV620";
385 case CHIP_RV635: return "AMD RV635";
386 case CHIP_RS780: return "AMD RS780";
387 case CHIP_RS880: return "AMD RS880";
388 case CHIP_RV770: return "AMD RV770";
389 case CHIP_RV730: return "AMD RV730";
390 case CHIP_RV710: return "AMD RV710";
391 case CHIP_RV740: return "AMD RV740";
392 case CHIP_CEDAR: return "AMD CEDAR";
393 case CHIP_REDWOOD: return "AMD REDWOOD";
394 case CHIP_JUNIPER: return "AMD JUNIPER";
395 case CHIP_CYPRESS: return "AMD CYPRESS";
396 case CHIP_HEMLOCK: return "AMD HEMLOCK";
397 case CHIP_PALM: return "AMD PALM";
398 case CHIP_SUMO: return "AMD SUMO";
399 case CHIP_SUMO2: return "AMD SUMO2";
400 case CHIP_BARTS: return "AMD BARTS";
401 case CHIP_TURKS: return "AMD TURKS";
402 case CHIP_CAICOS: return "AMD CAICOS";
403 case CHIP_CAYMAN: return "AMD CAYMAN";
404 case CHIP_ARUBA: return "AMD ARUBA";
405 case CHIP_TAHITI: return "AMD TAHITI";
406 case CHIP_PITCAIRN: return "AMD PITCAIRN";
407 case CHIP_VERDE: return "AMD CAPE VERDE";
408 case CHIP_OLAND: return "AMD OLAND";
409 case CHIP_HAINAN: return "AMD HAINAN";
410 case CHIP_BONAIRE: return "AMD BONAIRE";
411 case CHIP_KAVERI: return "AMD KAVERI";
412 case CHIP_KABINI: return "AMD KABINI";
413 case CHIP_HAWAII: return "AMD HAWAII";
414 case CHIP_MULLINS: return "AMD MULLINS";
415 case CHIP_TONGA: return "AMD TONGA";
416 case CHIP_ICELAND: return "AMD ICELAND";
417 case CHIP_CARRIZO: return "AMD CARRIZO";
418 case CHIP_FIJI: return "AMD FIJI";
419 default: return "AMD unknown";
420 }
421 }
422
423 static const char* r600_get_name(struct pipe_screen* pscreen)
424 {
425 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
426
427 return rscreen->renderer_string;
428 }
429
430 static float r600_get_paramf(struct pipe_screen* pscreen,
431 enum pipe_capf param)
432 {
433 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
434
435 switch (param) {
436 case PIPE_CAPF_MAX_LINE_WIDTH:
437 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
438 case PIPE_CAPF_MAX_POINT_WIDTH:
439 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
440 if (rscreen->family >= CHIP_CEDAR)
441 return 16384.0f;
442 else
443 return 8192.0f;
444 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
445 return 16.0f;
446 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
447 return 16.0f;
448 case PIPE_CAPF_GUARD_BAND_LEFT:
449 case PIPE_CAPF_GUARD_BAND_TOP:
450 case PIPE_CAPF_GUARD_BAND_RIGHT:
451 case PIPE_CAPF_GUARD_BAND_BOTTOM:
452 return 0.0f;
453 }
454 return 0.0f;
455 }
456
457 static int r600_get_video_param(struct pipe_screen *screen,
458 enum pipe_video_profile profile,
459 enum pipe_video_entrypoint entrypoint,
460 enum pipe_video_cap param)
461 {
462 switch (param) {
463 case PIPE_VIDEO_CAP_SUPPORTED:
464 return vl_profile_supported(screen, profile, entrypoint);
465 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
466 return 1;
467 case PIPE_VIDEO_CAP_MAX_WIDTH:
468 case PIPE_VIDEO_CAP_MAX_HEIGHT:
469 return vl_video_buffer_max_size(screen);
470 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
471 return PIPE_FORMAT_NV12;
472 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
473 return false;
474 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
475 return false;
476 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
477 return true;
478 case PIPE_VIDEO_CAP_MAX_LEVEL:
479 return vl_level_supported(screen, profile);
480 default:
481 return 0;
482 }
483 }
484
485 const char *r600_get_llvm_processor_name(enum radeon_family family)
486 {
487 switch (family) {
488 case CHIP_R600:
489 case CHIP_RV630:
490 case CHIP_RV635:
491 case CHIP_RV670:
492 return "r600";
493 case CHIP_RV610:
494 case CHIP_RV620:
495 case CHIP_RS780:
496 case CHIP_RS880:
497 return "rs880";
498 case CHIP_RV710:
499 return "rv710";
500 case CHIP_RV730:
501 return "rv730";
502 case CHIP_RV740:
503 case CHIP_RV770:
504 return "rv770";
505 case CHIP_PALM:
506 case CHIP_CEDAR:
507 return "cedar";
508 case CHIP_SUMO:
509 case CHIP_SUMO2:
510 return "sumo";
511 case CHIP_REDWOOD:
512 return "redwood";
513 case CHIP_JUNIPER:
514 return "juniper";
515 case CHIP_HEMLOCK:
516 case CHIP_CYPRESS:
517 return "cypress";
518 case CHIP_BARTS:
519 return "barts";
520 case CHIP_TURKS:
521 return "turks";
522 case CHIP_CAICOS:
523 return "caicos";
524 case CHIP_CAYMAN:
525 case CHIP_ARUBA:
526 return "cayman";
527
528 case CHIP_TAHITI: return "tahiti";
529 case CHIP_PITCAIRN: return "pitcairn";
530 case CHIP_VERDE: return "verde";
531 case CHIP_OLAND: return "oland";
532 case CHIP_HAINAN: return "hainan";
533 case CHIP_BONAIRE: return "bonaire";
534 case CHIP_KABINI: return "kabini";
535 case CHIP_KAVERI: return "kaveri";
536 case CHIP_HAWAII: return "hawaii";
537 case CHIP_MULLINS:
538 return "mullins";
539 case CHIP_TONGA: return "tonga";
540 case CHIP_ICELAND: return "iceland";
541 case CHIP_CARRIZO: return "carrizo";
542 case CHIP_FIJI: return "fiji";
543 default: return "";
544 }
545 }
546
547 static int r600_get_compute_param(struct pipe_screen *screen,
548 enum pipe_compute_cap param,
549 void *ret)
550 {
551 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
552
553 //TODO: select these params by asic
554 switch (param) {
555 case PIPE_COMPUTE_CAP_IR_TARGET: {
556 const char *gpu;
557 const char *triple;
558 if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) {
559 triple = "r600--";
560 } else {
561 triple = "amdgcn--";
562 }
563 switch(rscreen->family) {
564 /* Clang < 3.6 is missing Hainan in its list of
565 * GPUs, so we need to use the name of a similar GPU.
566 */
567 #if HAVE_LLVM < 0x0306
568 case CHIP_HAINAN:
569 gpu = "oland";
570 break;
571 #endif
572 default:
573 gpu = r600_get_llvm_processor_name(rscreen->family);
574 break;
575 }
576 if (ret) {
577 sprintf(ret, "%s-%s", gpu, triple);
578 }
579 /* +2 for dash and terminating NIL byte */
580 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
581 }
582 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
583 if (ret) {
584 uint64_t *grid_dimension = ret;
585 grid_dimension[0] = 3;
586 }
587 return 1 * sizeof(uint64_t);
588
589 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
590 if (ret) {
591 uint64_t *grid_size = ret;
592 grid_size[0] = 65535;
593 grid_size[1] = 65535;
594 grid_size[2] = 1;
595 }
596 return 3 * sizeof(uint64_t) ;
597
598 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
599 if (ret) {
600 uint64_t *block_size = ret;
601 block_size[0] = 256;
602 block_size[1] = 256;
603 block_size[2] = 256;
604 }
605 return 3 * sizeof(uint64_t);
606
607 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
608 if (ret) {
609 uint64_t *max_threads_per_block = ret;
610 *max_threads_per_block = 256;
611 }
612 return sizeof(uint64_t);
613
614 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
615 if (ret) {
616 uint64_t *max_global_size = ret;
617 uint64_t max_mem_alloc_size;
618
619 r600_get_compute_param(screen,
620 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
621 &max_mem_alloc_size);
622
623 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
624 * 1/4 of the MAX_GLOBAL_SIZE. Since the
625 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
626 * make sure we never report more than
627 * 4 * MAX_MEM_ALLOC_SIZE.
628 */
629 *max_global_size = MIN2(4 * max_mem_alloc_size,
630 rscreen->info.gart_size +
631 rscreen->info.vram_size);
632 }
633 return sizeof(uint64_t);
634
635 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
636 if (ret) {
637 uint64_t *max_local_size = ret;
638 /* Value reported by the closed source driver. */
639 *max_local_size = 32768;
640 }
641 return sizeof(uint64_t);
642
643 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
644 if (ret) {
645 uint64_t *max_input_size = ret;
646 /* Value reported by the closed source driver. */
647 *max_input_size = 1024;
648 }
649 return sizeof(uint64_t);
650
651 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
652 if (ret) {
653 uint64_t *max_mem_alloc_size = ret;
654
655 /* XXX: The limit in older kernels is 256 MB. We
656 * should add a query here for newer kernels.
657 */
658 *max_mem_alloc_size = 256 * 1024 * 1024;
659 }
660 return sizeof(uint64_t);
661
662 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
663 if (ret) {
664 uint32_t *max_clock_frequency = ret;
665 *max_clock_frequency = rscreen->info.max_sclk;
666 }
667 return sizeof(uint32_t);
668
669 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
670 if (ret) {
671 uint32_t *max_compute_units = ret;
672 *max_compute_units = rscreen->info.max_compute_units;
673 }
674 return sizeof(uint32_t);
675
676 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
677 if (ret) {
678 uint32_t *images_supported = ret;
679 *images_supported = 0;
680 }
681 return sizeof(uint32_t);
682 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
683 break; /* unused */
684 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
685 if (ret) {
686 uint32_t *subgroup_size = ret;
687 *subgroup_size = r600_wavefront_size(rscreen->family);
688 }
689 return sizeof(uint32_t);
690 }
691
692 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
693 return 0;
694 }
695
696 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
697 {
698 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
699
700 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
701 rscreen->info.r600_clock_crystal_freq;
702 }
703
704 static int r600_get_driver_query_info(struct pipe_screen *screen,
705 unsigned index,
706 struct pipe_driver_query_info *info)
707 {
708 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
709 struct pipe_driver_query_info list[] = {
710 {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
711 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
712 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
713 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
714 {"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
715 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
716 {"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
717 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
718 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
719 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES, {0}},
720 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES,
721 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
722 {"VRAM-usage", R600_QUERY_VRAM_USAGE, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
723 {"GTT-usage", R600_QUERY_GTT_USAGE, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
724 {"GPU-load", R600_QUERY_GPU_LOAD, {100}},
725 {"temperature", R600_QUERY_GPU_TEMPERATURE, {125}},
726 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
727 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK, {0}, PIPE_DRIVER_QUERY_TYPE_HZ},
728 };
729 unsigned num_queries;
730
731 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
732 num_queries = Elements(list);
733 else if (rscreen->info.drm_major == 3)
734 num_queries = Elements(list) - 3;
735 else
736 num_queries = Elements(list) - 4;
737
738 if (!info)
739 return num_queries;
740
741 if (index >= num_queries)
742 return 0;
743
744 *info = list[index];
745 return 1;
746 }
747
748 static void r600_fence_reference(struct pipe_screen *screen,
749 struct pipe_fence_handle **ptr,
750 struct pipe_fence_handle *fence)
751 {
752 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
753
754 rws->fence_reference(ptr, fence);
755 }
756
757 static boolean r600_fence_finish(struct pipe_screen *screen,
758 struct pipe_fence_handle *fence,
759 uint64_t timeout)
760 {
761 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
762
763 return rws->fence_wait(rws, fence, timeout);
764 }
765
766 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
767 uint32_t tiling_config)
768 {
769 switch ((tiling_config & 0xe) >> 1) {
770 case 0:
771 rscreen->tiling_info.num_channels = 1;
772 break;
773 case 1:
774 rscreen->tiling_info.num_channels = 2;
775 break;
776 case 2:
777 rscreen->tiling_info.num_channels = 4;
778 break;
779 case 3:
780 rscreen->tiling_info.num_channels = 8;
781 break;
782 default:
783 return false;
784 }
785
786 switch ((tiling_config & 0x30) >> 4) {
787 case 0:
788 rscreen->tiling_info.num_banks = 4;
789 break;
790 case 1:
791 rscreen->tiling_info.num_banks = 8;
792 break;
793 default:
794 return false;
795
796 }
797 switch ((tiling_config & 0xc0) >> 6) {
798 case 0:
799 rscreen->tiling_info.group_bytes = 256;
800 break;
801 case 1:
802 rscreen->tiling_info.group_bytes = 512;
803 break;
804 default:
805 return false;
806 }
807 return true;
808 }
809
810 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
811 uint32_t tiling_config)
812 {
813 switch (tiling_config & 0xf) {
814 case 0:
815 rscreen->tiling_info.num_channels = 1;
816 break;
817 case 1:
818 rscreen->tiling_info.num_channels = 2;
819 break;
820 case 2:
821 rscreen->tiling_info.num_channels = 4;
822 break;
823 case 3:
824 rscreen->tiling_info.num_channels = 8;
825 break;
826 default:
827 return false;
828 }
829
830 switch ((tiling_config & 0xf0) >> 4) {
831 case 0:
832 rscreen->tiling_info.num_banks = 4;
833 break;
834 case 1:
835 rscreen->tiling_info.num_banks = 8;
836 break;
837 case 2:
838 rscreen->tiling_info.num_banks = 16;
839 break;
840 default:
841 return false;
842 }
843
844 switch ((tiling_config & 0xf00) >> 8) {
845 case 0:
846 rscreen->tiling_info.group_bytes = 256;
847 break;
848 case 1:
849 rscreen->tiling_info.group_bytes = 512;
850 break;
851 default:
852 return false;
853 }
854 return true;
855 }
856
857 static bool r600_init_tiling(struct r600_common_screen *rscreen)
858 {
859 uint32_t tiling_config = rscreen->info.r600_tiling_config;
860
861 /* set default group bytes, overridden by tiling info ioctl */
862 if (rscreen->chip_class <= R700) {
863 rscreen->tiling_info.group_bytes = 256;
864 } else {
865 rscreen->tiling_info.group_bytes = 512;
866 }
867
868 if (!tiling_config)
869 return true;
870
871 if (rscreen->chip_class <= R700) {
872 return r600_interpret_tiling(rscreen, tiling_config);
873 } else {
874 return evergreen_interpret_tiling(rscreen, tiling_config);
875 }
876 }
877
878 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
879 const struct pipe_resource *templ)
880 {
881 if (templ->target == PIPE_BUFFER) {
882 return r600_buffer_create(screen, templ, 4096);
883 } else {
884 return r600_texture_create(screen, templ);
885 }
886 }
887
888 bool r600_common_screen_init(struct r600_common_screen *rscreen,
889 struct radeon_winsys *ws)
890 {
891 char llvm_string[32] = {};
892
893 ws->query_info(ws, &rscreen->info);
894
895 #if HAVE_LLVM
896 snprintf(llvm_string, sizeof(llvm_string),
897 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
898 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
899 #endif
900
901 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
902 "%s (DRM %i.%i.%i%s)",
903 r600_get_chip_name(rscreen), rscreen->info.drm_major,
904 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
905 llvm_string);
906
907 rscreen->b.get_name = r600_get_name;
908 rscreen->b.get_vendor = r600_get_vendor;
909 rscreen->b.get_device_vendor = r600_get_device_vendor;
910 rscreen->b.get_compute_param = r600_get_compute_param;
911 rscreen->b.get_paramf = r600_get_paramf;
912 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
913 rscreen->b.get_timestamp = r600_get_timestamp;
914 rscreen->b.fence_finish = r600_fence_finish;
915 rscreen->b.fence_reference = r600_fence_reference;
916 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
917 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
918
919 if (rscreen->info.has_uvd) {
920 rscreen->b.get_video_param = rvid_get_video_param;
921 rscreen->b.is_video_format_supported = rvid_is_format_supported;
922 } else {
923 rscreen->b.get_video_param = r600_get_video_param;
924 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
925 }
926
927 r600_init_screen_texture_functions(rscreen);
928
929 rscreen->ws = ws;
930 rscreen->family = rscreen->info.family;
931 rscreen->chip_class = rscreen->info.chip_class;
932 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
933
934 if (!r600_init_tiling(rscreen)) {
935 return false;
936 }
937 util_format_s3tc_init();
938 pipe_mutex_init(rscreen->aux_context_lock);
939 pipe_mutex_init(rscreen->gpu_load_mutex);
940
941 if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
942 rscreen->info.drm_major == 3) &&
943 (rscreen->debug_flags & DBG_TRACE_CS)) {
944 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
945 PIPE_BIND_CUSTOM,
946 PIPE_USAGE_STAGING,
947 4096);
948 if (rscreen->trace_bo) {
949 rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
950 PIPE_TRANSFER_UNSYNCHRONIZED);
951 }
952 }
953
954 if (rscreen->debug_flags & DBG_INFO) {
955 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
956 printf("family = %i\n", rscreen->info.family);
957 printf("chip_class = %i\n", rscreen->info.chip_class);
958 printf("gart_size = %i MB\n", (int)(rscreen->info.gart_size >> 20));
959 printf("vram_size = %i MB\n", (int)(rscreen->info.vram_size >> 20));
960 printf("max_sclk = %i\n", rscreen->info.max_sclk);
961 printf("max_compute_units = %i\n", rscreen->info.max_compute_units);
962 printf("max_se = %i\n", rscreen->info.max_se);
963 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
964 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
965 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
966 printf("has_uvd = %i\n", rscreen->info.has_uvd);
967 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
968 printf("r600_num_backends = %i\n", rscreen->info.r600_num_backends);
969 printf("r600_clock_crystal_freq = %i\n", rscreen->info.r600_clock_crystal_freq);
970 printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
971 printf("r600_num_tile_pipes = %i\n", rscreen->info.r600_num_tile_pipes);
972 printf("r600_max_pipes = %i\n", rscreen->info.r600_max_pipes);
973 printf("r600_virtual_address = %i\n", rscreen->info.r600_virtual_address);
974 printf("r600_has_dma = %i\n", rscreen->info.r600_has_dma);
975 printf("r600_backend_map = %i\n", rscreen->info.r600_backend_map);
976 printf("r600_backend_map_valid = %i\n", rscreen->info.r600_backend_map_valid);
977 printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
978 printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
979 }
980 return true;
981 }
982
983 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
984 {
985 r600_gpu_load_kill_thread(rscreen);
986
987 pipe_mutex_destroy(rscreen->gpu_load_mutex);
988 pipe_mutex_destroy(rscreen->aux_context_lock);
989 rscreen->aux_context->destroy(rscreen->aux_context);
990
991 if (rscreen->trace_bo)
992 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
993
994 rscreen->ws->destroy(rscreen->ws);
995 FREE(rscreen);
996 }
997
998 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
999 const struct tgsi_token *tokens)
1000 {
1001 /* Compute shader don't have tgsi_tokens */
1002 if (!tokens)
1003 return (rscreen->debug_flags & DBG_CS) != 0;
1004
1005 switch (tgsi_get_processor_type(tokens)) {
1006 case TGSI_PROCESSOR_VERTEX:
1007 return (rscreen->debug_flags & DBG_VS) != 0;
1008 case TGSI_PROCESSOR_TESS_CTRL:
1009 return (rscreen->debug_flags & DBG_TCS) != 0;
1010 case TGSI_PROCESSOR_TESS_EVAL:
1011 return (rscreen->debug_flags & DBG_TES) != 0;
1012 case TGSI_PROCESSOR_GEOMETRY:
1013 return (rscreen->debug_flags & DBG_GS) != 0;
1014 case TGSI_PROCESSOR_FRAGMENT:
1015 return (rscreen->debug_flags & DBG_PS) != 0;
1016 case TGSI_PROCESSOR_COMPUTE:
1017 return (rscreen->debug_flags & DBG_CS) != 0;
1018 default:
1019 return false;
1020 }
1021 }
1022
1023 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1024 unsigned offset, unsigned size, unsigned value,
1025 bool is_framebuffer)
1026 {
1027 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1028
1029 pipe_mutex_lock(rscreen->aux_context_lock);
1030 rctx->clear_buffer(&rctx->b, dst, offset, size, value, is_framebuffer);
1031 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1032 pipe_mutex_unlock(rscreen->aux_context_lock);
1033 }