2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_memory.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_upload_mgr.h"
34 #include "vl/vl_decoder.h"
35 #include "vl/vl_video_buffer.h"
36 #include "radeon/radeon_video.h"
47 void r600_draw_rectangle(struct blitter_context
*blitter
,
48 int x1
, int y1
, int x2
, int y2
, float depth
,
49 enum blitter_attrib_type type
,
50 const union pipe_color_union
*attrib
)
52 struct r600_common_context
*rctx
=
53 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
54 struct pipe_viewport_state viewport
;
55 struct pipe_resource
*buf
= NULL
;
59 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
60 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
64 /* Some operations (like color resolve on r6xx) don't work
65 * with the conventional primitive types.
66 * One that works is PT_RECTLIST, which we use here. */
69 viewport
.scale
[0] = 1.0f
;
70 viewport
.scale
[1] = 1.0f
;
71 viewport
.scale
[2] = 1.0f
;
72 viewport
.translate
[0] = 0.0f
;
73 viewport
.translate
[1] = 0.0f
;
74 viewport
.translate
[2] = 0.0f
;
75 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
77 /* Upload vertices. The hw rectangle has only 3 vertices,
78 * I guess the 4th one is derived from the first 3.
79 * The vertex specification should match u_blitter's vertex element state. */
80 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
97 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
98 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
99 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
103 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
104 R600_PRIM_RECTANGLE_LIST
, 3, 2);
105 pipe_resource_reference(&buf
, NULL
);
108 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
)
110 /* Flush if there's not enough space. */
111 if ((num_dw
+ ctx
->rings
.dma
.cs
->cdw
) > ctx
->rings
.dma
.cs
->max_dw
) {
112 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
113 assert((num_dw
+ ctx
->rings
.dma
.cs
->cdw
) <= ctx
->rings
.dma
.cs
->max_dw
);
117 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
121 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
123 /* Disable render condition. */
124 ctx
->saved_render_cond
= NULL
;
125 ctx
->saved_render_cond_cond
= FALSE
;
126 ctx
->saved_render_cond_mode
= 0;
127 if (ctx
->current_render_cond
) {
128 ctx
->saved_render_cond
= ctx
->current_render_cond
;
129 ctx
->saved_render_cond_cond
= ctx
->current_render_cond_cond
;
130 ctx
->saved_render_cond_mode
= ctx
->current_render_cond_mode
;
131 ctx
->b
.render_condition(&ctx
->b
, NULL
, FALSE
, 0);
134 /* suspend queries */
135 ctx
->queries_suspended_for_flush
= false;
136 if (ctx
->num_cs_dw_nontimer_queries_suspend
) {
137 r600_suspend_nontimer_queries(ctx
);
138 r600_suspend_timer_queries(ctx
);
139 ctx
->queries_suspended_for_flush
= true;
142 ctx
->streamout
.suspended
= false;
143 if (ctx
->streamout
.begin_emitted
) {
144 r600_emit_streamout_end(ctx
);
145 ctx
->streamout
.suspended
= true;
149 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
151 if (ctx
->streamout
.suspended
) {
152 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
153 r600_streamout_buffers_dirty(ctx
);
157 if (ctx
->queries_suspended_for_flush
) {
158 r600_resume_nontimer_queries(ctx
);
159 r600_resume_timer_queries(ctx
);
162 /* Re-enable render condition. */
163 if (ctx
->saved_render_cond
) {
164 ctx
->b
.render_condition(&ctx
->b
, ctx
->saved_render_cond
,
165 ctx
->saved_render_cond_cond
,
166 ctx
->saved_render_cond_mode
);
170 static void r600_flush_from_st(struct pipe_context
*ctx
,
171 struct pipe_fence_handle
**fence
,
174 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
177 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
178 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
180 if (rctx
->rings
.dma
.cs
) {
181 rctx
->rings
.dma
.flush(rctx
, rflags
, NULL
);
183 rctx
->rings
.gfx
.flush(rctx
, rflags
, fence
);
186 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
187 struct pipe_fence_handle
**fence
)
189 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
190 struct radeon_winsys_cs
*cs
= rctx
->rings
.dma
.cs
;
196 rctx
->rings
.dma
.flushing
= true;
197 rctx
->ws
->cs_flush(cs
, flags
, fence
, 0);
198 rctx
->rings
.dma
.flushing
= false;
201 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
203 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
204 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
205 RADEON_GPU_RESET_COUNTER
);
207 if (rctx
->gpu_reset_counter
== latest
)
208 return PIPE_NO_RESET
;
210 rctx
->gpu_reset_counter
= latest
;
211 return PIPE_UNKNOWN_CONTEXT_RESET
;
214 bool r600_common_context_init(struct r600_common_context
*rctx
,
215 struct r600_common_screen
*rscreen
)
217 util_slab_create(&rctx
->pool_transfers
,
218 sizeof(struct r600_transfer
), 64,
219 UTIL_SLAB_SINGLETHREADED
);
221 rctx
->screen
= rscreen
;
222 rctx
->ws
= rscreen
->ws
;
223 rctx
->family
= rscreen
->family
;
224 rctx
->chip_class
= rscreen
->chip_class
;
226 if (rscreen
->family
== CHIP_HAWAII
)
228 else if (rscreen
->chip_class
>= EVERGREEN
)
233 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
234 rctx
->b
.transfer_flush_region
= u_default_transfer_flush_region
;
235 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
236 rctx
->b
.transfer_inline_write
= u_default_transfer_inline_write
;
237 rctx
->b
.memory_barrier
= r600_memory_barrier
;
238 rctx
->b
.flush
= r600_flush_from_st
;
240 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
241 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
242 rctx
->gpu_reset_counter
=
243 rctx
->ws
->query_value(rctx
->ws
,
244 RADEON_GPU_RESET_COUNTER
);
247 LIST_INITHEAD(&rctx
->texture_buffers
);
249 r600_init_context_texture_functions(rctx
);
250 r600_streamout_init(rctx
);
251 r600_query_init(rctx
);
252 cayman_init_msaa(&rctx
->b
);
254 rctx
->allocator_so_filled_size
= u_suballocator_create(&rctx
->b
, 4096, 4,
255 0, PIPE_USAGE_DEFAULT
, TRUE
);
256 if (!rctx
->allocator_so_filled_size
)
259 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024, 256,
260 PIPE_BIND_INDEX_BUFFER
|
261 PIPE_BIND_CONSTANT_BUFFER
);
265 if (rscreen
->info
.r600_has_dma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
266 rctx
->rings
.dma
.cs
= rctx
->ws
->cs_create(rctx
->ws
, RING_DMA
,
269 rctx
->rings
.dma
.flush
= r600_flush_dma_ring
;
275 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
277 if (rctx
->rings
.gfx
.cs
) {
278 rctx
->ws
->cs_destroy(rctx
->rings
.gfx
.cs
);
280 if (rctx
->rings
.dma
.cs
) {
281 rctx
->ws
->cs_destroy(rctx
->rings
.dma
.cs
);
284 if (rctx
->uploader
) {
285 u_upload_destroy(rctx
->uploader
);
288 util_slab_destroy(&rctx
->pool_transfers
);
290 if (rctx
->allocator_so_filled_size
) {
291 u_suballocator_destroy(rctx
->allocator_so_filled_size
);
295 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
297 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
298 struct r600_resource
*rr
= (struct r600_resource
*)r
;
305 * The idea is to compute a gross estimate of memory requirement of
306 * each draw call. After each draw call, memory will be precisely
307 * accounted. So the uncertainty is only on the current draw call.
308 * In practice this gave very good estimate (+/- 10% of the target
311 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
312 rctx
->gtt
+= rr
->buf
->size
;
314 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
315 rctx
->vram
+= rr
->buf
->size
;
323 static const struct debug_named_value common_debug_options
[] = {
325 { "tex", DBG_TEX
, "Print texture info" },
326 { "texmip", DBG_TEXMIP
, "Print texture info (mipmapped only)" },
327 { "compute", DBG_COMPUTE
, "Print compute info" },
328 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
329 { "trace_cs", DBG_TRACE_CS
, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
330 { "info", DBG_INFO
, "Print driver information" },
333 { "fs", DBG_FS
, "Print fetch shaders" },
334 { "vs", DBG_VS
, "Print vertex shaders" },
335 { "gs", DBG_GS
, "Print geometry shaders" },
336 { "ps", DBG_PS
, "Print pixel shaders" },
337 { "cs", DBG_CS
, "Print compute shaders" },
338 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
339 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
340 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
341 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
342 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
345 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
346 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
347 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
348 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
349 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
350 { "notiling", DBG_NO_TILING
, "Disable tiling" },
351 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
352 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
353 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
355 DEBUG_NAMED_VALUE_END
/* must be last */
358 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
363 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
368 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
370 switch (rscreen
->info
.family
) {
371 case CHIP_R600
: return "AMD R600";
372 case CHIP_RV610
: return "AMD RV610";
373 case CHIP_RV630
: return "AMD RV630";
374 case CHIP_RV670
: return "AMD RV670";
375 case CHIP_RV620
: return "AMD RV620";
376 case CHIP_RV635
: return "AMD RV635";
377 case CHIP_RS780
: return "AMD RS780";
378 case CHIP_RS880
: return "AMD RS880";
379 case CHIP_RV770
: return "AMD RV770";
380 case CHIP_RV730
: return "AMD RV730";
381 case CHIP_RV710
: return "AMD RV710";
382 case CHIP_RV740
: return "AMD RV740";
383 case CHIP_CEDAR
: return "AMD CEDAR";
384 case CHIP_REDWOOD
: return "AMD REDWOOD";
385 case CHIP_JUNIPER
: return "AMD JUNIPER";
386 case CHIP_CYPRESS
: return "AMD CYPRESS";
387 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
388 case CHIP_PALM
: return "AMD PALM";
389 case CHIP_SUMO
: return "AMD SUMO";
390 case CHIP_SUMO2
: return "AMD SUMO2";
391 case CHIP_BARTS
: return "AMD BARTS";
392 case CHIP_TURKS
: return "AMD TURKS";
393 case CHIP_CAICOS
: return "AMD CAICOS";
394 case CHIP_CAYMAN
: return "AMD CAYMAN";
395 case CHIP_ARUBA
: return "AMD ARUBA";
396 case CHIP_TAHITI
: return "AMD TAHITI";
397 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
398 case CHIP_VERDE
: return "AMD CAPE VERDE";
399 case CHIP_OLAND
: return "AMD OLAND";
400 case CHIP_HAINAN
: return "AMD HAINAN";
401 case CHIP_BONAIRE
: return "AMD BONAIRE";
402 case CHIP_KAVERI
: return "AMD KAVERI";
403 case CHIP_KABINI
: return "AMD KABINI";
404 case CHIP_HAWAII
: return "AMD HAWAII";
405 case CHIP_MULLINS
: return "AMD MULLINS";
406 default: return "AMD unknown";
410 static const char* r600_get_name(struct pipe_screen
* pscreen
)
412 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
414 return rscreen
->renderer_string
;
417 static float r600_get_paramf(struct pipe_screen
* pscreen
,
418 enum pipe_capf param
)
420 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
423 case PIPE_CAPF_MAX_LINE_WIDTH
:
424 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
425 case PIPE_CAPF_MAX_POINT_WIDTH
:
426 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
427 if (rscreen
->family
>= CHIP_CEDAR
)
431 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
433 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
435 case PIPE_CAPF_GUARD_BAND_LEFT
:
436 case PIPE_CAPF_GUARD_BAND_TOP
:
437 case PIPE_CAPF_GUARD_BAND_RIGHT
:
438 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
444 static int r600_get_video_param(struct pipe_screen
*screen
,
445 enum pipe_video_profile profile
,
446 enum pipe_video_entrypoint entrypoint
,
447 enum pipe_video_cap param
)
450 case PIPE_VIDEO_CAP_SUPPORTED
:
451 return vl_profile_supported(screen
, profile
, entrypoint
);
452 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
454 case PIPE_VIDEO_CAP_MAX_WIDTH
:
455 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
456 return vl_video_buffer_max_size(screen
);
457 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
458 return PIPE_FORMAT_NV12
;
459 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
461 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
463 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
465 case PIPE_VIDEO_CAP_MAX_LEVEL
:
466 return vl_level_supported(screen
, profile
);
472 const char *r600_get_llvm_processor_name(enum radeon_family family
)
515 case CHIP_TAHITI
: return "tahiti";
516 case CHIP_PITCAIRN
: return "pitcairn";
517 case CHIP_VERDE
: return "verde";
518 case CHIP_OLAND
: return "oland";
519 case CHIP_HAINAN
: return "hainan";
520 case CHIP_BONAIRE
: return "bonaire";
521 case CHIP_KABINI
: return "kabini";
522 case CHIP_KAVERI
: return "kaveri";
523 case CHIP_HAWAII
: return "hawaii";
525 #if HAVE_LLVM >= 0x0305
534 static int r600_get_compute_param(struct pipe_screen
*screen
,
535 enum pipe_compute_cap param
,
538 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
540 //TODO: select these params by asic
542 case PIPE_COMPUTE_CAP_IR_TARGET
: {
545 if (rscreen
->family
<= CHIP_ARUBA
|| HAVE_LLVM
< 0x0306) {
550 switch(rscreen
->family
) {
551 /* Clang < 3.6 is missing Hainan in its list of
552 * GPUs, so we need to use the name of a similar GPU.
554 #if HAVE_LLVM < 0x0306
560 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
564 sprintf(ret
, "%s-%s", gpu
, triple
);
566 /* +2 for dash and terminating NIL byte */
567 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
569 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
571 uint64_t *grid_dimension
= ret
;
572 grid_dimension
[0] = 3;
574 return 1 * sizeof(uint64_t);
576 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
578 uint64_t *grid_size
= ret
;
579 grid_size
[0] = 65535;
580 grid_size
[1] = 65535;
583 return 3 * sizeof(uint64_t) ;
585 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
587 uint64_t *block_size
= ret
;
592 return 3 * sizeof(uint64_t);
594 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
596 uint64_t *max_threads_per_block
= ret
;
597 *max_threads_per_block
= 256;
599 return sizeof(uint64_t);
601 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
603 uint64_t *max_global_size
= ret
;
604 uint64_t max_mem_alloc_size
;
606 r600_get_compute_param(screen
,
607 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
608 &max_mem_alloc_size
);
610 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
611 * 1/4 of the MAX_GLOBAL_SIZE. Since the
612 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
613 * make sure we never report more than
614 * 4 * MAX_MEM_ALLOC_SIZE.
616 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
617 rscreen
->info
.gart_size
+
618 rscreen
->info
.vram_size
);
620 return sizeof(uint64_t);
622 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
624 uint64_t *max_local_size
= ret
;
625 /* Value reported by the closed source driver. */
626 *max_local_size
= 32768;
628 return sizeof(uint64_t);
630 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
632 uint64_t *max_input_size
= ret
;
633 /* Value reported by the closed source driver. */
634 *max_input_size
= 1024;
636 return sizeof(uint64_t);
638 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
640 uint64_t *max_mem_alloc_size
= ret
;
642 /* XXX: The limit in older kernels is 256 MB. We
643 * should add a query here for newer kernels.
645 *max_mem_alloc_size
= 256 * 1024 * 1024;
647 return sizeof(uint64_t);
649 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
651 uint32_t *max_clock_frequency
= ret
;
652 *max_clock_frequency
= rscreen
->info
.max_sclk
;
654 return sizeof(uint32_t);
656 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
658 uint32_t *max_compute_units
= ret
;
659 *max_compute_units
= rscreen
->info
.max_compute_units
;
661 return sizeof(uint32_t);
663 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
665 uint32_t *images_supported
= ret
;
666 *images_supported
= 0;
668 return sizeof(uint32_t);
669 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
671 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
673 uint32_t *subgroup_size
= ret
;
674 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
676 return sizeof(uint32_t);
679 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
683 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
685 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
687 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
688 rscreen
->info
.r600_clock_crystal_freq
;
691 static int r600_get_driver_query_info(struct pipe_screen
*screen
,
693 struct pipe_driver_query_info
*info
)
695 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
696 struct pipe_driver_query_info list
[] = {
697 {"num-compilations", R600_QUERY_NUM_COMPILATIONS
, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64
,
698 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
},
699 {"num-shaders-created", R600_QUERY_NUM_SHADERS_CREATED
, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64
,
700 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
},
701 {"draw-calls", R600_QUERY_DRAW_CALLS
, {0}},
702 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM
, {rscreen
->info
.vram_size
}, PIPE_DRIVER_QUERY_TYPE_BYTES
},
703 {"requested-GTT", R600_QUERY_REQUESTED_GTT
, {rscreen
->info
.gart_size
}, PIPE_DRIVER_QUERY_TYPE_BYTES
},
704 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME
, {0}, PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
,
705 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
},
706 {"num-cs-flushes", R600_QUERY_NUM_CS_FLUSHES
, {0}},
707 {"num-bytes-moved", R600_QUERY_NUM_BYTES_MOVED
, {0}, PIPE_DRIVER_QUERY_TYPE_BYTES
,
708 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
},
709 {"VRAM-usage", R600_QUERY_VRAM_USAGE
, {rscreen
->info
.vram_size
}, PIPE_DRIVER_QUERY_TYPE_BYTES
},
710 {"GTT-usage", R600_QUERY_GTT_USAGE
, {rscreen
->info
.gart_size
}, PIPE_DRIVER_QUERY_TYPE_BYTES
},
711 {"temperature", R600_QUERY_GPU_TEMPERATURE
, {100}},
712 {"shader-clock", R600_QUERY_CURRENT_GPU_SCLK
, {0}, PIPE_DRIVER_QUERY_TYPE_HZ
},
713 {"memory-clock", R600_QUERY_CURRENT_GPU_MCLK
, {0}, PIPE_DRIVER_QUERY_TYPE_HZ
},
714 {"GPU-load", R600_QUERY_GPU_LOAD
, {100}}
716 unsigned num_queries
;
718 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 42)
719 num_queries
= Elements(list
);
726 if (index
>= num_queries
)
733 static void r600_fence_reference(struct pipe_screen
*screen
,
734 struct pipe_fence_handle
**ptr
,
735 struct pipe_fence_handle
*fence
)
737 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
739 rws
->fence_reference(ptr
, fence
);
742 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
743 struct pipe_fence_handle
*fence
,
746 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
748 return rws
->fence_wait(rws
, fence
, timeout
);
751 static bool r600_interpret_tiling(struct r600_common_screen
*rscreen
,
752 uint32_t tiling_config
)
754 switch ((tiling_config
& 0xe) >> 1) {
756 rscreen
->tiling_info
.num_channels
= 1;
759 rscreen
->tiling_info
.num_channels
= 2;
762 rscreen
->tiling_info
.num_channels
= 4;
765 rscreen
->tiling_info
.num_channels
= 8;
771 switch ((tiling_config
& 0x30) >> 4) {
773 rscreen
->tiling_info
.num_banks
= 4;
776 rscreen
->tiling_info
.num_banks
= 8;
782 switch ((tiling_config
& 0xc0) >> 6) {
784 rscreen
->tiling_info
.group_bytes
= 256;
787 rscreen
->tiling_info
.group_bytes
= 512;
795 static bool evergreen_interpret_tiling(struct r600_common_screen
*rscreen
,
796 uint32_t tiling_config
)
798 switch (tiling_config
& 0xf) {
800 rscreen
->tiling_info
.num_channels
= 1;
803 rscreen
->tiling_info
.num_channels
= 2;
806 rscreen
->tiling_info
.num_channels
= 4;
809 rscreen
->tiling_info
.num_channels
= 8;
815 switch ((tiling_config
& 0xf0) >> 4) {
817 rscreen
->tiling_info
.num_banks
= 4;
820 rscreen
->tiling_info
.num_banks
= 8;
823 rscreen
->tiling_info
.num_banks
= 16;
829 switch ((tiling_config
& 0xf00) >> 8) {
831 rscreen
->tiling_info
.group_bytes
= 256;
834 rscreen
->tiling_info
.group_bytes
= 512;
842 static bool r600_init_tiling(struct r600_common_screen
*rscreen
)
844 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
846 /* set default group bytes, overridden by tiling info ioctl */
847 if (rscreen
->chip_class
<= R700
) {
848 rscreen
->tiling_info
.group_bytes
= 256;
850 rscreen
->tiling_info
.group_bytes
= 512;
856 if (rscreen
->chip_class
<= R700
) {
857 return r600_interpret_tiling(rscreen
, tiling_config
);
859 return evergreen_interpret_tiling(rscreen
, tiling_config
);
863 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
864 const struct pipe_resource
*templ
)
866 if (templ
->target
== PIPE_BUFFER
) {
867 return r600_buffer_create(screen
, templ
, 4096);
869 return r600_texture_create(screen
, templ
);
873 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
874 struct radeon_winsys
*ws
)
876 char llvm_string
[32] = {};
878 ws
->query_info(ws
, &rscreen
->info
);
881 snprintf(llvm_string
, sizeof(llvm_string
),
882 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
883 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
885 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
886 "%s (DRM %i.%i.%i%s)",
887 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
888 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
891 rscreen
->b
.get_name
= r600_get_name
;
892 rscreen
->b
.get_vendor
= r600_get_vendor
;
893 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
894 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
895 rscreen
->b
.get_paramf
= r600_get_paramf
;
896 rscreen
->b
.get_driver_query_info
= r600_get_driver_query_info
;
897 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
898 rscreen
->b
.fence_finish
= r600_fence_finish
;
899 rscreen
->b
.fence_reference
= r600_fence_reference
;
900 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
901 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
903 if (rscreen
->info
.has_uvd
) {
904 rscreen
->b
.get_video_param
= rvid_get_video_param
;
905 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
907 rscreen
->b
.get_video_param
= r600_get_video_param
;
908 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
911 r600_init_screen_texture_functions(rscreen
);
914 rscreen
->family
= rscreen
->info
.family
;
915 rscreen
->chip_class
= rscreen
->info
.chip_class
;
916 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
918 if (!r600_init_tiling(rscreen
)) {
921 util_format_s3tc_init();
922 pipe_mutex_init(rscreen
->aux_context_lock
);
923 pipe_mutex_init(rscreen
->gpu_load_mutex
);
925 if (rscreen
->info
.drm_minor
>= 28 && (rscreen
->debug_flags
& DBG_TRACE_CS
)) {
926 rscreen
->trace_bo
= (struct r600_resource
*)pipe_buffer_create(&rscreen
->b
,
930 if (rscreen
->trace_bo
) {
931 rscreen
->trace_ptr
= rscreen
->ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
932 PIPE_TRANSFER_UNSYNCHRONIZED
);
936 if (rscreen
->debug_flags
& DBG_INFO
) {
937 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
938 printf("family = %i\n", rscreen
->info
.family
);
939 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
940 printf("gart_size = %i MB\n", (int)(rscreen
->info
.gart_size
>> 20));
941 printf("vram_size = %i MB\n", (int)(rscreen
->info
.vram_size
>> 20));
942 printf("max_sclk = %i\n", rscreen
->info
.max_sclk
);
943 printf("max_compute_units = %i\n", rscreen
->info
.max_compute_units
);
944 printf("max_se = %i\n", rscreen
->info
.max_se
);
945 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
946 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
947 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
948 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
949 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
950 printf("r600_num_backends = %i\n", rscreen
->info
.r600_num_backends
);
951 printf("r600_clock_crystal_freq = %i\n", rscreen
->info
.r600_clock_crystal_freq
);
952 printf("r600_tiling_config = 0x%x\n", rscreen
->info
.r600_tiling_config
);
953 printf("r600_num_tile_pipes = %i\n", rscreen
->info
.r600_num_tile_pipes
);
954 printf("r600_max_pipes = %i\n", rscreen
->info
.r600_max_pipes
);
955 printf("r600_virtual_address = %i\n", rscreen
->info
.r600_virtual_address
);
956 printf("r600_has_dma = %i\n", rscreen
->info
.r600_has_dma
);
957 printf("r600_backend_map = %i\n", rscreen
->info
.r600_backend_map
);
958 printf("r600_backend_map_valid = %i\n", rscreen
->info
.r600_backend_map_valid
);
959 printf("si_tile_mode_array_valid = %i\n", rscreen
->info
.si_tile_mode_array_valid
);
960 printf("cik_macrotile_mode_array_valid = %i\n", rscreen
->info
.cik_macrotile_mode_array_valid
);
965 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
967 r600_gpu_load_kill_thread(rscreen
);
969 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
970 pipe_mutex_destroy(rscreen
->aux_context_lock
);
971 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
973 if (rscreen
->trace_bo
)
974 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
976 rscreen
->ws
->destroy(rscreen
->ws
);
980 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
981 const struct tgsi_token
*tokens
)
983 /* Compute shader don't have tgsi_tokens */
985 return (rscreen
->debug_flags
& DBG_CS
) != 0;
987 switch (tgsi_get_processor_type(tokens
)) {
988 case TGSI_PROCESSOR_VERTEX
:
989 return (rscreen
->debug_flags
& DBG_VS
) != 0;
990 case TGSI_PROCESSOR_TESS_CTRL
:
991 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
992 case TGSI_PROCESSOR_TESS_EVAL
:
993 return (rscreen
->debug_flags
& DBG_TES
) != 0;
994 case TGSI_PROCESSOR_GEOMETRY
:
995 return (rscreen
->debug_flags
& DBG_GS
) != 0;
996 case TGSI_PROCESSOR_FRAGMENT
:
997 return (rscreen
->debug_flags
& DBG_PS
) != 0;
998 case TGSI_PROCESSOR_COMPUTE
:
999 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1005 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1006 unsigned offset
, unsigned size
, unsigned value
,
1007 bool is_framebuffer
)
1009 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1011 pipe_mutex_lock(rscreen
->aux_context_lock
);
1012 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, is_framebuffer
);
1013 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1014 pipe_mutex_unlock(rscreen
->aux_context_lock
);