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gallium/radeon: use TCC line size as alignment in other places
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #ifndef MESA_LLVM_VERSION_PATCH
47 #define MESA_LLVM_VERSION_PATCH 0
48 #endif
49
50 struct r600_multi_fence {
51 struct pipe_reference reference;
52 struct pipe_fence_handle *gfx;
53 struct pipe_fence_handle *sdma;
54
55 /* If the context wasn't flushed at fence creation, this is non-NULL. */
56 struct {
57 struct r600_common_context *ctx;
58 unsigned ib_index;
59 } gfx_unflushed;
60 };
61
62 /*
63 * shader binary helpers.
64 */
65 void radeon_shader_binary_init(struct radeon_shader_binary *b)
66 {
67 memset(b, 0, sizeof(*b));
68 }
69
70 void radeon_shader_binary_clean(struct radeon_shader_binary *b)
71 {
72 if (!b)
73 return;
74 FREE(b->code);
75 FREE(b->config);
76 FREE(b->rodata);
77 FREE(b->global_symbol_offsets);
78 FREE(b->relocs);
79 FREE(b->disasm_string);
80 FREE(b->llvm_ir_string);
81 }
82
83 /*
84 * pipe_context
85 */
86
87 /**
88 * Write an EOP event.
89 *
90 * \param event EVENT_TYPE_*
91 * \param event_flags Optional cache flush flags (TC)
92 * \param data_sel 1 = fence, 3 = timestamp
93 * \param buf Buffer
94 * \param va GPU address
95 * \param old_value Previous fence value (for a bug workaround)
96 * \param new_value Fence value to write for this event.
97 */
98 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
99 unsigned event, unsigned event_flags,
100 unsigned data_sel,
101 struct r600_resource *buf, uint64_t va,
102 uint32_t old_fence, uint32_t new_fence)
103 {
104 struct radeon_winsys_cs *cs = ctx->gfx.cs;
105 unsigned op = EVENT_TYPE(event) |
106 EVENT_INDEX(5) |
107 event_flags;
108
109 if (ctx->chip_class == CIK ||
110 ctx->chip_class == VI) {
111 /* Two EOP events are required to make all engines go idle
112 * (and optional cache flushes executed) before the timestamp
113 * is written.
114 */
115 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
116 radeon_emit(cs, op);
117 radeon_emit(cs, va);
118 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
119 radeon_emit(cs, old_fence); /* immediate data */
120 radeon_emit(cs, 0); /* unused */
121 }
122
123 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
124 radeon_emit(cs, op);
125 radeon_emit(cs, va);
126 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
127 radeon_emit(cs, new_fence); /* immediate data */
128 radeon_emit(cs, 0); /* unused */
129
130 if (buf)
131 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
132 RADEON_PRIO_QUERY);
133 }
134
135 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
136 {
137 unsigned dwords = 6;
138
139 if (screen->chip_class == CIK ||
140 screen->chip_class == VI)
141 dwords *= 2;
142
143 if (!screen->info.has_virtual_memory)
144 dwords += 2;
145
146 return dwords;
147 }
148
149 void r600_gfx_wait_fence(struct r600_common_context *ctx,
150 uint64_t va, uint32_t ref, uint32_t mask)
151 {
152 struct radeon_winsys_cs *cs = ctx->gfx.cs;
153
154 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
155 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
156 radeon_emit(cs, va);
157 radeon_emit(cs, va >> 32);
158 radeon_emit(cs, ref); /* reference value */
159 radeon_emit(cs, mask); /* mask */
160 radeon_emit(cs, 4); /* poll interval */
161 }
162
163 void r600_draw_rectangle(struct blitter_context *blitter,
164 int x1, int y1, int x2, int y2, float depth,
165 enum blitter_attrib_type type,
166 const union pipe_color_union *attrib)
167 {
168 struct r600_common_context *rctx =
169 (struct r600_common_context*)util_blitter_get_pipe(blitter);
170 struct pipe_viewport_state viewport;
171 struct pipe_resource *buf = NULL;
172 unsigned offset = 0;
173 float *vb;
174
175 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
176 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
177 return;
178 }
179
180 /* Some operations (like color resolve on r6xx) don't work
181 * with the conventional primitive types.
182 * One that works is PT_RECTLIST, which we use here. */
183
184 /* setup viewport */
185 viewport.scale[0] = 1.0f;
186 viewport.scale[1] = 1.0f;
187 viewport.scale[2] = 1.0f;
188 viewport.translate[0] = 0.0f;
189 viewport.translate[1] = 0.0f;
190 viewport.translate[2] = 0.0f;
191 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
192
193 /* Upload vertices. The hw rectangle has only 3 vertices,
194 * I guess the 4th one is derived from the first 3.
195 * The vertex specification should match u_blitter's vertex element state. */
196 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
197 rctx->screen->info.tcc_cache_line_size,
198 &offset, &buf, (void**)&vb);
199 if (!buf)
200 return;
201
202 vb[0] = x1;
203 vb[1] = y1;
204 vb[2] = depth;
205 vb[3] = 1;
206
207 vb[8] = x1;
208 vb[9] = y2;
209 vb[10] = depth;
210 vb[11] = 1;
211
212 vb[16] = x2;
213 vb[17] = y1;
214 vb[18] = depth;
215 vb[19] = 1;
216
217 if (attrib) {
218 memcpy(vb+4, attrib->f, sizeof(float)*4);
219 memcpy(vb+12, attrib->f, sizeof(float)*4);
220 memcpy(vb+20, attrib->f, sizeof(float)*4);
221 }
222
223 /* draw */
224 util_draw_vertex_buffer(&rctx->b, NULL, buf, blitter->vb_slot, offset,
225 R600_PRIM_RECTANGLE_LIST, 3, 2);
226 pipe_resource_reference(&buf, NULL);
227 }
228
229 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
230 {
231 struct radeon_winsys_cs *cs = rctx->dma.cs;
232
233 /* NOP waits for idle on Evergreen and later. */
234 if (rctx->chip_class >= CIK)
235 radeon_emit(cs, 0x00000000); /* NOP */
236 else if (rctx->chip_class >= EVERGREEN)
237 radeon_emit(cs, 0xf0000000); /* NOP */
238 else {
239 /* TODO: R600-R700 should use the FENCE packet.
240 * CS checker support is required. */
241 }
242 }
243
244 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
245 struct r600_resource *dst, struct r600_resource *src)
246 {
247 uint64_t vram = ctx->dma.cs->used_vram;
248 uint64_t gtt = ctx->dma.cs->used_gart;
249
250 if (dst) {
251 vram += dst->vram_usage;
252 gtt += dst->gart_usage;
253 }
254 if (src) {
255 vram += src->vram_usage;
256 gtt += src->gart_usage;
257 }
258
259 /* Flush the GFX IB if DMA depends on it. */
260 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
261 ((dst &&
262 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
263 RADEON_USAGE_READWRITE)) ||
264 (src &&
265 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
266 RADEON_USAGE_WRITE))))
267 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
268
269 /* Flush if there's not enough space, or if the memory usage per IB
270 * is too large.
271 *
272 * IBs using too little memory are limited by the IB submission overhead.
273 * IBs using too much memory are limited by the kernel/TTM overhead.
274 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
275 *
276 * This heuristic makes sure that DMA requests are executed
277 * very soon after the call is made and lowers memory usage.
278 * It improves texture upload performance by keeping the DMA
279 * engine busy while uploads are being submitted.
280 */
281 num_dw++; /* for emit_wait_idle below */
282 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
283 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
284 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
285 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
286 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
287 }
288
289 /* Wait for idle if either buffer has been used in the IB before to
290 * prevent read-after-write hazards.
291 */
292 if ((dst &&
293 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
294 RADEON_USAGE_READWRITE)) ||
295 (src &&
296 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
297 RADEON_USAGE_WRITE)))
298 r600_dma_emit_wait_idle(ctx);
299
300 /* If GPUVM is not supported, the CS checker needs 2 entries
301 * in the buffer list per packet, which has to be done manually.
302 */
303 if (ctx->screen->info.has_virtual_memory) {
304 if (dst)
305 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
306 RADEON_USAGE_WRITE,
307 RADEON_PRIO_SDMA_BUFFER);
308 if (src)
309 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
310 RADEON_USAGE_READ,
311 RADEON_PRIO_SDMA_BUFFER);
312 }
313
314 /* this function is called before all DMA calls, so increment this. */
315 ctx->num_dma_calls++;
316 }
317
318 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
319 {
320 }
321
322 void r600_preflush_suspend_features(struct r600_common_context *ctx)
323 {
324 /* suspend queries */
325 if (!LIST_IS_EMPTY(&ctx->active_queries))
326 r600_suspend_queries(ctx);
327
328 ctx->streamout.suspended = false;
329 if (ctx->streamout.begin_emitted) {
330 r600_emit_streamout_end(ctx);
331 ctx->streamout.suspended = true;
332 }
333 }
334
335 void r600_postflush_resume_features(struct r600_common_context *ctx)
336 {
337 if (ctx->streamout.suspended) {
338 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
339 r600_streamout_buffers_dirty(ctx);
340 }
341
342 /* resume queries */
343 if (!LIST_IS_EMPTY(&ctx->active_queries))
344 r600_resume_queries(ctx);
345 }
346
347 static void r600_flush_from_st(struct pipe_context *ctx,
348 struct pipe_fence_handle **fence,
349 unsigned flags)
350 {
351 struct pipe_screen *screen = ctx->screen;
352 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
353 struct radeon_winsys *ws = rctx->ws;
354 unsigned rflags = 0;
355 struct pipe_fence_handle *gfx_fence = NULL;
356 struct pipe_fence_handle *sdma_fence = NULL;
357 bool deferred_fence = false;
358
359 if (flags & PIPE_FLUSH_END_OF_FRAME)
360 rflags |= RADEON_FLUSH_END_OF_FRAME;
361 if (flags & PIPE_FLUSH_DEFERRED)
362 rflags |= RADEON_FLUSH_ASYNC;
363
364 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
365 if (rctx->dma.cs)
366 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
367
368 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
369 if (fence)
370 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
371 if (!(rflags & RADEON_FLUSH_ASYNC))
372 ws->cs_sync_flush(rctx->gfx.cs);
373 } else {
374 /* Instead of flushing, create a deferred fence. Constraints:
375 * - The state tracker must allow a deferred flush.
376 * - The state tracker must request a fence.
377 * Thread safety in fence_finish must be ensured by the state tracker.
378 */
379 if (flags & PIPE_FLUSH_DEFERRED && fence) {
380 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
381 deferred_fence = true;
382 } else {
383 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
384 }
385 }
386
387 /* Both engines can signal out of order, so we need to keep both fences. */
388 if (fence) {
389 struct r600_multi_fence *multi_fence =
390 CALLOC_STRUCT(r600_multi_fence);
391 if (!multi_fence)
392 return;
393
394 multi_fence->reference.count = 1;
395 /* If both fences are NULL, fence_finish will always return true. */
396 multi_fence->gfx = gfx_fence;
397 multi_fence->sdma = sdma_fence;
398
399 if (deferred_fence) {
400 multi_fence->gfx_unflushed.ctx = rctx;
401 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
402 }
403
404 screen->fence_reference(screen, fence, NULL);
405 *fence = (struct pipe_fence_handle*)multi_fence;
406 }
407 }
408
409 static void r600_flush_dma_ring(void *ctx, unsigned flags,
410 struct pipe_fence_handle **fence)
411 {
412 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
413 struct radeon_winsys_cs *cs = rctx->dma.cs;
414 struct radeon_saved_cs saved;
415 bool check_vm =
416 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
417 rctx->check_vm_faults;
418
419 if (!radeon_emitted(cs, 0)) {
420 if (fence)
421 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
422 return;
423 }
424
425 if (check_vm)
426 radeon_save_cs(rctx->ws, cs, &saved);
427
428 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
429 if (fence)
430 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
431
432 if (check_vm) {
433 /* Use conservative timeout 800ms, after which we won't wait any
434 * longer and assume the GPU is hung.
435 */
436 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
437
438 rctx->check_vm_faults(rctx, &saved, RING_DMA);
439 radeon_clear_saved_cs(&saved);
440 }
441 }
442
443 /**
444 * Store a linearized copy of all chunks of \p cs together with the buffer
445 * list in \p saved.
446 */
447 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
448 struct radeon_saved_cs *saved)
449 {
450 void *buf;
451 unsigned i;
452
453 /* Save the IB chunks. */
454 saved->num_dw = cs->prev_dw + cs->current.cdw;
455 saved->ib = MALLOC(4 * saved->num_dw);
456 if (!saved->ib)
457 goto oom;
458
459 buf = saved->ib;
460 for (i = 0; i < cs->num_prev; ++i) {
461 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
462 buf += cs->prev[i].cdw;
463 }
464 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
465
466 /* Save the buffer list. */
467 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
468 saved->bo_list = CALLOC(saved->bo_count,
469 sizeof(saved->bo_list[0]));
470 if (!saved->bo_list) {
471 FREE(saved->ib);
472 goto oom;
473 }
474 ws->cs_get_buffer_list(cs, saved->bo_list);
475
476 return;
477
478 oom:
479 fprintf(stderr, "%s: out of memory\n", __func__);
480 memset(saved, 0, sizeof(*saved));
481 }
482
483 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
484 {
485 FREE(saved->ib);
486 FREE(saved->bo_list);
487
488 memset(saved, 0, sizeof(*saved));
489 }
490
491 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
492 {
493 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
494 unsigned latest = rctx->ws->query_value(rctx->ws,
495 RADEON_GPU_RESET_COUNTER);
496
497 if (rctx->gpu_reset_counter == latest)
498 return PIPE_NO_RESET;
499
500 rctx->gpu_reset_counter = latest;
501 return PIPE_UNKNOWN_CONTEXT_RESET;
502 }
503
504 static void r600_set_debug_callback(struct pipe_context *ctx,
505 const struct pipe_debug_callback *cb)
506 {
507 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
508
509 if (cb)
510 rctx->debug = *cb;
511 else
512 memset(&rctx->debug, 0, sizeof(rctx->debug));
513 }
514
515 static void r600_set_device_reset_callback(struct pipe_context *ctx,
516 const struct pipe_device_reset_callback *cb)
517 {
518 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
519
520 if (cb)
521 rctx->device_reset_callback = *cb;
522 else
523 memset(&rctx->device_reset_callback, 0,
524 sizeof(rctx->device_reset_callback));
525 }
526
527 bool r600_check_device_reset(struct r600_common_context *rctx)
528 {
529 enum pipe_reset_status status;
530
531 if (!rctx->device_reset_callback.reset)
532 return false;
533
534 if (!rctx->b.get_device_reset_status)
535 return false;
536
537 status = rctx->b.get_device_reset_status(&rctx->b);
538 if (status == PIPE_NO_RESET)
539 return false;
540
541 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
542 return true;
543 }
544
545 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
546 struct pipe_resource *dst,
547 uint64_t offset, uint64_t size,
548 unsigned value)
549 {
550 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
551
552 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
553 }
554
555 bool r600_common_context_init(struct r600_common_context *rctx,
556 struct r600_common_screen *rscreen,
557 unsigned context_flags)
558 {
559 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
560
561 rctx->screen = rscreen;
562 rctx->ws = rscreen->ws;
563 rctx->family = rscreen->family;
564 rctx->chip_class = rscreen->chip_class;
565
566 rctx->b.invalidate_resource = r600_invalidate_resource;
567 rctx->b.transfer_map = u_transfer_map_vtbl;
568 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
569 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
570 rctx->b.texture_subdata = u_default_texture_subdata;
571 rctx->b.memory_barrier = r600_memory_barrier;
572 rctx->b.flush = r600_flush_from_st;
573 rctx->b.set_debug_callback = r600_set_debug_callback;
574 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
575
576 /* evergreen_compute.c has a special codepath for global buffers.
577 * Everything else can use the direct path.
578 */
579 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
580 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
581 rctx->b.buffer_subdata = u_default_buffer_subdata;
582 else
583 rctx->b.buffer_subdata = r600_buffer_subdata;
584
585 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
586 rctx->b.get_device_reset_status = r600_get_reset_status;
587 rctx->gpu_reset_counter =
588 rctx->ws->query_value(rctx->ws,
589 RADEON_GPU_RESET_COUNTER);
590 }
591
592 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
593
594 r600_init_context_texture_functions(rctx);
595 r600_init_viewport_functions(rctx);
596 r600_streamout_init(rctx);
597 r600_query_init(rctx);
598 cayman_init_msaa(&rctx->b);
599
600 rctx->allocator_zeroed_memory =
601 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
602 0, PIPE_USAGE_DEFAULT, 0, true);
603 if (!rctx->allocator_zeroed_memory)
604 return false;
605
606 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
607 0, PIPE_USAGE_STREAM);
608 if (!rctx->b.stream_uploader)
609 return false;
610 rctx->b.const_uploader = rctx->b.stream_uploader;
611
612 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
613 if (!rctx->ctx)
614 return false;
615
616 if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
617 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
618 r600_flush_dma_ring,
619 rctx);
620 rctx->dma.flush = r600_flush_dma_ring;
621 }
622
623 return true;
624 }
625
626 void r600_common_context_cleanup(struct r600_common_context *rctx)
627 {
628 unsigned i,j;
629
630 /* Release DCC stats. */
631 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
632 assert(!rctx->dcc_stats[i].query_active);
633
634 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
635 if (rctx->dcc_stats[i].ps_stats[j])
636 rctx->b.destroy_query(&rctx->b,
637 rctx->dcc_stats[i].ps_stats[j]);
638
639 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
640 }
641
642 if (rctx->query_result_shader)
643 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
644
645 if (rctx->gfx.cs)
646 rctx->ws->cs_destroy(rctx->gfx.cs);
647 if (rctx->dma.cs)
648 rctx->ws->cs_destroy(rctx->dma.cs);
649 if (rctx->ctx)
650 rctx->ws->ctx_destroy(rctx->ctx);
651
652 if (rctx->b.stream_uploader) {
653 u_upload_destroy(rctx->b.stream_uploader);
654 }
655
656 slab_destroy_child(&rctx->pool_transfers);
657
658 if (rctx->allocator_zeroed_memory) {
659 u_suballocator_destroy(rctx->allocator_zeroed_memory);
660 }
661 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
662 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
663 }
664
665 /*
666 * pipe_screen
667 */
668
669 static const struct debug_named_value common_debug_options[] = {
670 /* logging */
671 { "tex", DBG_TEX, "Print texture info" },
672 { "compute", DBG_COMPUTE, "Print compute info" },
673 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
674 { "info", DBG_INFO, "Print driver information" },
675
676 /* shaders */
677 { "fs", DBG_FS, "Print fetch shaders" },
678 { "vs", DBG_VS, "Print vertex shaders" },
679 { "gs", DBG_GS, "Print geometry shaders" },
680 { "ps", DBG_PS, "Print pixel shaders" },
681 { "cs", DBG_CS, "Print compute shaders" },
682 { "tcs", DBG_TCS, "Print tessellation control shaders" },
683 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
684 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
685 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
686 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
687 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
688 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
689 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
690
691 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
692
693 /* features */
694 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
695 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
696 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
697 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
698 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
699 { "notiling", DBG_NO_TILING, "Disable tiling" },
700 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
701 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
702 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
703 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
704 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
705 { "nodcc", DBG_NO_DCC, "Disable DCC." },
706 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
707 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
708 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
709 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
710 { "noce", DBG_NO_CE, "Disable the constant engine"},
711 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
712 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
713
714 DEBUG_NAMED_VALUE_END /* must be last */
715 };
716
717 static const char* r600_get_vendor(struct pipe_screen* pscreen)
718 {
719 return "X.Org";
720 }
721
722 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
723 {
724 return "AMD";
725 }
726
727 static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
728 {
729 switch (rscreen->info.family) {
730 case CHIP_R600: return "AMD R600";
731 case CHIP_RV610: return "AMD RV610";
732 case CHIP_RV630: return "AMD RV630";
733 case CHIP_RV670: return "AMD RV670";
734 case CHIP_RV620: return "AMD RV620";
735 case CHIP_RV635: return "AMD RV635";
736 case CHIP_RS780: return "AMD RS780";
737 case CHIP_RS880: return "AMD RS880";
738 case CHIP_RV770: return "AMD RV770";
739 case CHIP_RV730: return "AMD RV730";
740 case CHIP_RV710: return "AMD RV710";
741 case CHIP_RV740: return "AMD RV740";
742 case CHIP_CEDAR: return "AMD CEDAR";
743 case CHIP_REDWOOD: return "AMD REDWOOD";
744 case CHIP_JUNIPER: return "AMD JUNIPER";
745 case CHIP_CYPRESS: return "AMD CYPRESS";
746 case CHIP_HEMLOCK: return "AMD HEMLOCK";
747 case CHIP_PALM: return "AMD PALM";
748 case CHIP_SUMO: return "AMD SUMO";
749 case CHIP_SUMO2: return "AMD SUMO2";
750 case CHIP_BARTS: return "AMD BARTS";
751 case CHIP_TURKS: return "AMD TURKS";
752 case CHIP_CAICOS: return "AMD CAICOS";
753 case CHIP_CAYMAN: return "AMD CAYMAN";
754 case CHIP_ARUBA: return "AMD ARUBA";
755 case CHIP_TAHITI: return "AMD TAHITI";
756 case CHIP_PITCAIRN: return "AMD PITCAIRN";
757 case CHIP_VERDE: return "AMD CAPE VERDE";
758 case CHIP_OLAND: return "AMD OLAND";
759 case CHIP_HAINAN: return "AMD HAINAN";
760 case CHIP_BONAIRE: return "AMD BONAIRE";
761 case CHIP_KAVERI: return "AMD KAVERI";
762 case CHIP_KABINI: return "AMD KABINI";
763 case CHIP_HAWAII: return "AMD HAWAII";
764 case CHIP_MULLINS: return "AMD MULLINS";
765 case CHIP_TONGA: return "AMD TONGA";
766 case CHIP_ICELAND: return "AMD ICELAND";
767 case CHIP_CARRIZO: return "AMD CARRIZO";
768 case CHIP_FIJI: return "AMD FIJI";
769 case CHIP_POLARIS10: return "AMD POLARIS10";
770 case CHIP_POLARIS11: return "AMD POLARIS11";
771 case CHIP_POLARIS12: return "AMD POLARIS12";
772 case CHIP_STONEY: return "AMD STONEY";
773 default: return "AMD unknown";
774 }
775 }
776
777 static const char* r600_get_name(struct pipe_screen* pscreen)
778 {
779 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
780
781 return rscreen->renderer_string;
782 }
783
784 static float r600_get_paramf(struct pipe_screen* pscreen,
785 enum pipe_capf param)
786 {
787 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
788
789 switch (param) {
790 case PIPE_CAPF_MAX_LINE_WIDTH:
791 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
792 case PIPE_CAPF_MAX_POINT_WIDTH:
793 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
794 if (rscreen->family >= CHIP_CEDAR)
795 return 16384.0f;
796 else
797 return 8192.0f;
798 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
799 return 16.0f;
800 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
801 return 16.0f;
802 case PIPE_CAPF_GUARD_BAND_LEFT:
803 case PIPE_CAPF_GUARD_BAND_TOP:
804 case PIPE_CAPF_GUARD_BAND_RIGHT:
805 case PIPE_CAPF_GUARD_BAND_BOTTOM:
806 return 0.0f;
807 }
808 return 0.0f;
809 }
810
811 static int r600_get_video_param(struct pipe_screen *screen,
812 enum pipe_video_profile profile,
813 enum pipe_video_entrypoint entrypoint,
814 enum pipe_video_cap param)
815 {
816 switch (param) {
817 case PIPE_VIDEO_CAP_SUPPORTED:
818 return vl_profile_supported(screen, profile, entrypoint);
819 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
820 return 1;
821 case PIPE_VIDEO_CAP_MAX_WIDTH:
822 case PIPE_VIDEO_CAP_MAX_HEIGHT:
823 return vl_video_buffer_max_size(screen);
824 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
825 return PIPE_FORMAT_NV12;
826 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
827 return false;
828 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
829 return false;
830 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
831 return true;
832 case PIPE_VIDEO_CAP_MAX_LEVEL:
833 return vl_level_supported(screen, profile);
834 default:
835 return 0;
836 }
837 }
838
839 const char *r600_get_llvm_processor_name(enum radeon_family family)
840 {
841 switch (family) {
842 case CHIP_R600:
843 case CHIP_RV630:
844 case CHIP_RV635:
845 case CHIP_RV670:
846 return "r600";
847 case CHIP_RV610:
848 case CHIP_RV620:
849 case CHIP_RS780:
850 case CHIP_RS880:
851 return "rs880";
852 case CHIP_RV710:
853 return "rv710";
854 case CHIP_RV730:
855 return "rv730";
856 case CHIP_RV740:
857 case CHIP_RV770:
858 return "rv770";
859 case CHIP_PALM:
860 case CHIP_CEDAR:
861 return "cedar";
862 case CHIP_SUMO:
863 case CHIP_SUMO2:
864 return "sumo";
865 case CHIP_REDWOOD:
866 return "redwood";
867 case CHIP_JUNIPER:
868 return "juniper";
869 case CHIP_HEMLOCK:
870 case CHIP_CYPRESS:
871 return "cypress";
872 case CHIP_BARTS:
873 return "barts";
874 case CHIP_TURKS:
875 return "turks";
876 case CHIP_CAICOS:
877 return "caicos";
878 case CHIP_CAYMAN:
879 case CHIP_ARUBA:
880 return "cayman";
881
882 case CHIP_TAHITI: return "tahiti";
883 case CHIP_PITCAIRN: return "pitcairn";
884 case CHIP_VERDE: return "verde";
885 case CHIP_OLAND: return "oland";
886 case CHIP_HAINAN: return "hainan";
887 case CHIP_BONAIRE: return "bonaire";
888 case CHIP_KABINI: return "kabini";
889 case CHIP_KAVERI: return "kaveri";
890 case CHIP_HAWAII: return "hawaii";
891 case CHIP_MULLINS:
892 return "mullins";
893 case CHIP_TONGA: return "tonga";
894 case CHIP_ICELAND: return "iceland";
895 case CHIP_CARRIZO: return "carrizo";
896 case CHIP_FIJI:
897 return HAVE_LLVM >= 0x0308 ? "fiji" : "carrizo";
898 case CHIP_STONEY:
899 return HAVE_LLVM >= 0x0308 ? "stoney" : "carrizo";
900 case CHIP_POLARIS10:
901 return HAVE_LLVM >= 0x0309 ? "polaris10" : "carrizo";
902 case CHIP_POLARIS11:
903 case CHIP_POLARIS12: /* same as polaris11 */
904 return HAVE_LLVM >= 0x0309 ? "polaris11" : "carrizo";
905 default:
906 return "";
907 }
908 }
909
910 static int r600_get_compute_param(struct pipe_screen *screen,
911 enum pipe_shader_ir ir_type,
912 enum pipe_compute_cap param,
913 void *ret)
914 {
915 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
916
917 //TODO: select these params by asic
918 switch (param) {
919 case PIPE_COMPUTE_CAP_IR_TARGET: {
920 const char *gpu;
921 const char *triple;
922 if (rscreen->family <= CHIP_ARUBA) {
923 triple = "r600--";
924 } else {
925 if (HAVE_LLVM < 0x0400) {
926 triple = "amdgcn--";
927 } else {
928 triple = "amdgcn-mesa-mesa3d";
929 }
930 }
931 switch(rscreen->family) {
932 /* Clang < 3.6 is missing Hainan in its list of
933 * GPUs, so we need to use the name of a similar GPU.
934 */
935 default:
936 gpu = r600_get_llvm_processor_name(rscreen->family);
937 break;
938 }
939 if (ret) {
940 sprintf(ret, "%s-%s", gpu, triple);
941 }
942 /* +2 for dash and terminating NIL byte */
943 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
944 }
945 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
946 if (ret) {
947 uint64_t *grid_dimension = ret;
948 grid_dimension[0] = 3;
949 }
950 return 1 * sizeof(uint64_t);
951
952 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
953 if (ret) {
954 uint64_t *grid_size = ret;
955 grid_size[0] = 65535;
956 grid_size[1] = 65535;
957 grid_size[2] = 65535;
958 }
959 return 3 * sizeof(uint64_t) ;
960
961 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
962 if (ret) {
963 uint64_t *block_size = ret;
964 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
965 ir_type == PIPE_SHADER_IR_TGSI) {
966 block_size[0] = 2048;
967 block_size[1] = 2048;
968 block_size[2] = 2048;
969 } else {
970 block_size[0] = 256;
971 block_size[1] = 256;
972 block_size[2] = 256;
973 }
974 }
975 return 3 * sizeof(uint64_t);
976
977 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
978 if (ret) {
979 uint64_t *max_threads_per_block = ret;
980 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
981 ir_type == PIPE_SHADER_IR_TGSI)
982 *max_threads_per_block = 2048;
983 else
984 *max_threads_per_block = 256;
985 }
986 return sizeof(uint64_t);
987 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
988 if (ret) {
989 uint32_t *address_bits = ret;
990 address_bits[0] = 32;
991 if (rscreen->chip_class >= SI)
992 address_bits[0] = 64;
993 }
994 return 1 * sizeof(uint32_t);
995
996 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
997 if (ret) {
998 uint64_t *max_global_size = ret;
999 uint64_t max_mem_alloc_size;
1000
1001 r600_get_compute_param(screen, ir_type,
1002 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1003 &max_mem_alloc_size);
1004
1005 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1006 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1007 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1008 * make sure we never report more than
1009 * 4 * MAX_MEM_ALLOC_SIZE.
1010 */
1011 *max_global_size = MIN2(4 * max_mem_alloc_size,
1012 MAX2(rscreen->info.gart_size,
1013 rscreen->info.vram_size));
1014 }
1015 return sizeof(uint64_t);
1016
1017 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1018 if (ret) {
1019 uint64_t *max_local_size = ret;
1020 /* Value reported by the closed source driver. */
1021 *max_local_size = 32768;
1022 }
1023 return sizeof(uint64_t);
1024
1025 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1026 if (ret) {
1027 uint64_t *max_input_size = ret;
1028 /* Value reported by the closed source driver. */
1029 *max_input_size = 1024;
1030 }
1031 return sizeof(uint64_t);
1032
1033 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1034 if (ret) {
1035 uint64_t *max_mem_alloc_size = ret;
1036
1037 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1038 }
1039 return sizeof(uint64_t);
1040
1041 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1042 if (ret) {
1043 uint32_t *max_clock_frequency = ret;
1044 *max_clock_frequency = rscreen->info.max_shader_clock;
1045 }
1046 return sizeof(uint32_t);
1047
1048 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1049 if (ret) {
1050 uint32_t *max_compute_units = ret;
1051 *max_compute_units = rscreen->info.num_good_compute_units;
1052 }
1053 return sizeof(uint32_t);
1054
1055 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1056 if (ret) {
1057 uint32_t *images_supported = ret;
1058 *images_supported = 0;
1059 }
1060 return sizeof(uint32_t);
1061 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1062 break; /* unused */
1063 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1064 if (ret) {
1065 uint32_t *subgroup_size = ret;
1066 *subgroup_size = r600_wavefront_size(rscreen->family);
1067 }
1068 return sizeof(uint32_t);
1069 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1070 if (ret) {
1071 uint64_t *max_variable_threads_per_block = ret;
1072 if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
1073 ir_type == PIPE_SHADER_IR_TGSI)
1074 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1075 else
1076 *max_variable_threads_per_block = 0;
1077 }
1078 return sizeof(uint64_t);
1079 }
1080
1081 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1082 return 0;
1083 }
1084
1085 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1086 {
1087 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1088
1089 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1090 rscreen->info.clock_crystal_freq;
1091 }
1092
1093 static void r600_fence_reference(struct pipe_screen *screen,
1094 struct pipe_fence_handle **dst,
1095 struct pipe_fence_handle *src)
1096 {
1097 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1098 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1099 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1100
1101 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1102 ws->fence_reference(&(*rdst)->gfx, NULL);
1103 ws->fence_reference(&(*rdst)->sdma, NULL);
1104 FREE(*rdst);
1105 }
1106 *rdst = rsrc;
1107 }
1108
1109 static boolean r600_fence_finish(struct pipe_screen *screen,
1110 struct pipe_context *ctx,
1111 struct pipe_fence_handle *fence,
1112 uint64_t timeout)
1113 {
1114 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1115 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1116 struct r600_common_context *rctx =
1117 ctx ? (struct r600_common_context*)ctx : NULL;
1118 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1119
1120 if (rfence->sdma) {
1121 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1122 return false;
1123
1124 /* Recompute the timeout after waiting. */
1125 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1126 int64_t time = os_time_get_nano();
1127 timeout = abs_timeout > time ? abs_timeout - time : 0;
1128 }
1129 }
1130
1131 if (!rfence->gfx)
1132 return true;
1133
1134 /* Flush the gfx IB if it hasn't been flushed yet. */
1135 if (rctx &&
1136 rfence->gfx_unflushed.ctx == rctx &&
1137 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1138 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1139 rfence->gfx_unflushed.ctx = NULL;
1140
1141 if (!timeout)
1142 return false;
1143
1144 /* Recompute the timeout after all that. */
1145 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1146 int64_t time = os_time_get_nano();
1147 timeout = abs_timeout > time ? abs_timeout - time : 0;
1148 }
1149 }
1150
1151 return rws->fence_wait(rws, rfence->gfx, timeout);
1152 }
1153
1154 static void r600_query_memory_info(struct pipe_screen *screen,
1155 struct pipe_memory_info *info)
1156 {
1157 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1158 struct radeon_winsys *ws = rscreen->ws;
1159 unsigned vram_usage, gtt_usage;
1160
1161 info->total_device_memory = rscreen->info.vram_size / 1024;
1162 info->total_staging_memory = rscreen->info.gart_size / 1024;
1163
1164 /* The real TTM memory usage is somewhat random, because:
1165 *
1166 * 1) TTM delays freeing memory, because it can only free it after
1167 * fences expire.
1168 *
1169 * 2) The memory usage can be really low if big VRAM evictions are
1170 * taking place, but the real usage is well above the size of VRAM.
1171 *
1172 * Instead, return statistics of this process.
1173 */
1174 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1175 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1176
1177 info->avail_device_memory =
1178 vram_usage <= info->total_device_memory ?
1179 info->total_device_memory - vram_usage : 0;
1180 info->avail_staging_memory =
1181 gtt_usage <= info->total_staging_memory ?
1182 info->total_staging_memory - gtt_usage : 0;
1183
1184 info->device_memory_evicted =
1185 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1186
1187 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1188 info->nr_device_memory_evictions =
1189 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1190 else
1191 /* Just return the number of evicted 64KB pages. */
1192 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1193 }
1194
1195 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1196 const struct pipe_resource *templ)
1197 {
1198 if (templ->target == PIPE_BUFFER) {
1199 return r600_buffer_create(screen, templ, 256);
1200 } else {
1201 return r600_texture_create(screen, templ);
1202 }
1203 }
1204
1205 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1206 struct radeon_winsys *ws)
1207 {
1208 char llvm_string[32] = {}, kernel_version[128] = {};
1209 struct utsname uname_data;
1210
1211 ws->query_info(ws, &rscreen->info);
1212
1213 if (uname(&uname_data) == 0)
1214 snprintf(kernel_version, sizeof(kernel_version),
1215 " / %s", uname_data.release);
1216
1217 if (HAVE_LLVM > 0) {
1218 snprintf(llvm_string, sizeof(llvm_string),
1219 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1220 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1221 }
1222
1223 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1224 "%s (DRM %i.%i.%i%s%s)",
1225 r600_get_chip_name(rscreen), rscreen->info.drm_major,
1226 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1227 kernel_version, llvm_string);
1228
1229 rscreen->b.get_name = r600_get_name;
1230 rscreen->b.get_vendor = r600_get_vendor;
1231 rscreen->b.get_device_vendor = r600_get_device_vendor;
1232 rscreen->b.get_compute_param = r600_get_compute_param;
1233 rscreen->b.get_paramf = r600_get_paramf;
1234 rscreen->b.get_timestamp = r600_get_timestamp;
1235 rscreen->b.fence_finish = r600_fence_finish;
1236 rscreen->b.fence_reference = r600_fence_reference;
1237 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1238 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1239 rscreen->b.query_memory_info = r600_query_memory_info;
1240
1241 if (rscreen->info.has_uvd) {
1242 rscreen->b.get_video_param = rvid_get_video_param;
1243 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1244 } else {
1245 rscreen->b.get_video_param = r600_get_video_param;
1246 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1247 }
1248
1249 r600_init_screen_texture_functions(rscreen);
1250 r600_init_screen_query_functions(rscreen);
1251
1252 rscreen->ws = ws;
1253 rscreen->family = rscreen->info.family;
1254 rscreen->chip_class = rscreen->info.chip_class;
1255 rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1256
1257 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1258
1259 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1260 if (rscreen->force_aniso >= 0) {
1261 printf("radeon: Forcing anisotropy filter to %ix\n",
1262 /* round down to a power of two */
1263 1 << util_logbase2(rscreen->force_aniso));
1264 }
1265
1266 util_format_s3tc_init();
1267 pipe_mutex_init(rscreen->aux_context_lock);
1268 pipe_mutex_init(rscreen->gpu_load_mutex);
1269
1270 if (rscreen->debug_flags & DBG_INFO) {
1271 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1272 printf("family = %i (%s)\n", rscreen->info.family,
1273 r600_get_chip_name(rscreen));
1274 printf("chip_class = %i\n", rscreen->info.chip_class);
1275 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1276 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1277 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1278 printf("max_alloc_size = %i MB\n",
1279 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1280 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1281 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1282 printf("has_sdma = %i\n", rscreen->info.has_sdma);
1283 printf("has_uvd = %i\n", rscreen->info.has_uvd);
1284 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1285 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1286 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1287 printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
1288 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1289 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1290 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1291 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1292 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1293
1294 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1295 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1296 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1297 printf("max_se = %i\n", rscreen->info.max_se);
1298 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1299
1300 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1301 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1302 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1303 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1304 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1305 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1306 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1307 }
1308 return true;
1309 }
1310
1311 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1312 {
1313 r600_perfcounters_destroy(rscreen);
1314 r600_gpu_load_kill_thread(rscreen);
1315
1316 pipe_mutex_destroy(rscreen->gpu_load_mutex);
1317 pipe_mutex_destroy(rscreen->aux_context_lock);
1318 rscreen->aux_context->destroy(rscreen->aux_context);
1319
1320 slab_destroy_parent(&rscreen->pool_transfers);
1321
1322 rscreen->ws->destroy(rscreen->ws);
1323 FREE(rscreen);
1324 }
1325
1326 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1327 unsigned processor)
1328 {
1329 switch (processor) {
1330 case PIPE_SHADER_VERTEX:
1331 return (rscreen->debug_flags & DBG_VS) != 0;
1332 case PIPE_SHADER_TESS_CTRL:
1333 return (rscreen->debug_flags & DBG_TCS) != 0;
1334 case PIPE_SHADER_TESS_EVAL:
1335 return (rscreen->debug_flags & DBG_TES) != 0;
1336 case PIPE_SHADER_GEOMETRY:
1337 return (rscreen->debug_flags & DBG_GS) != 0;
1338 case PIPE_SHADER_FRAGMENT:
1339 return (rscreen->debug_flags & DBG_PS) != 0;
1340 case PIPE_SHADER_COMPUTE:
1341 return (rscreen->debug_flags & DBG_CS) != 0;
1342 default:
1343 return false;
1344 }
1345 }
1346
1347 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1348 {
1349 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1350 r600_can_dump_shader(rscreen, processor);
1351 }
1352
1353 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1354 uint64_t offset, uint64_t size, unsigned value)
1355 {
1356 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1357
1358 pipe_mutex_lock(rscreen->aux_context_lock);
1359 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1360 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1361 pipe_mutex_unlock(rscreen->aux_context_lock);
1362 }